1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "MipsInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Mips profiles and nodes
22 //===----------------------------------------------------------------------===//
24 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
25 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
30 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
31 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
32 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
33 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def SDT_MipsDivRem : SDTypeProfile<0, 2,
40 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
42 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
44 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
46 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
47 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
48 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
49 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
112 // Pointer to dynamically allocated stack area.
113 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
114 [SDNPHasChain, SDNPInGlue]>;
116 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
118 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
119 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
121 //===----------------------------------------------------------------------===//
122 // Mips Instruction Predicate Definitions.
123 //===----------------------------------------------------------------------===//
124 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
125 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
126 def HasSwap : Predicate<"Subtarget.hasSwap()">;
127 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
128 def HasMips32 : Predicate<"Subtarget.hasMips32()">;
129 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
130 def HasMips64 : Predicate<"Subtarget.hasMips64()">;
131 def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
132 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
133 def IsN64 : Predicate<"Subtarget.isABI_N64()">;
134 def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
136 //===----------------------------------------------------------------------===//
137 // Mips Operand, Complex Patterns and Transformations Definitions.
138 //===----------------------------------------------------------------------===//
140 // Instruction operand types
141 def jmptarget : Operand<OtherVT> {
142 let EncoderMethod = "getJumpTargetOpValue";
144 def brtarget : Operand<OtherVT> {
145 let EncoderMethod = "getBranchTargetOpValue";
146 let OperandType = "OPERAND_PCREL";
148 def calltarget : Operand<iPTR> {
149 let EncoderMethod = "getJumpTargetOpValue";
151 def calltarget64: Operand<i64>;
152 def simm16 : Operand<i32>;
153 def simm16_64 : Operand<i64>;
154 def shamt : Operand<i32>;
157 def uimm16 : Operand<i32> {
158 let PrintMethod = "printUnsignedImm";
162 def mem : Operand<i32> {
163 let PrintMethod = "printMemOperand";
164 let MIOperandInfo = (ops CPURegs, simm16);
165 let EncoderMethod = "getMemEncoding";
168 def mem64 : Operand<i64> {
169 let PrintMethod = "printMemOperand";
170 let MIOperandInfo = (ops CPU64Regs, simm16_64);
173 def mem_ea : Operand<i32> {
174 let PrintMethod = "printMemOperandEA";
175 let MIOperandInfo = (ops CPURegs, simm16);
176 let EncoderMethod = "getMemEncoding";
179 def mem_ea_64 : Operand<i64> {
180 let PrintMethod = "printMemOperandEA";
181 let MIOperandInfo = (ops CPU64Regs, simm16_64);
182 let EncoderMethod = "getMemEncoding";
185 // size operand of ext instruction
186 def size_ext : Operand<i32> {
187 let EncoderMethod = "getSizeExtEncoding";
190 // size operand of ins instruction
191 def size_ins : Operand<i32> {
192 let EncoderMethod = "getSizeInsEncoding";
195 // Transformation Function - get the lower 16 bits.
196 def LO16 : SDNodeXForm<imm, [{
197 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
200 // Transformation Function - get the higher 16 bits.
201 def HI16 : SDNodeXForm<imm, [{
202 return getI32Imm((unsigned)N->getZExtValue() >> 16);
205 // Node immediate fits as 16-bit sign extended on target immediate.
207 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
209 // Node immediate fits as 16-bit zero extended on target immediate.
210 // The LO16 param means that only the lower 16 bits of the node
211 // immediate are caught.
213 def immZExt16 : PatLeaf<(imm), [{
214 if (N->getValueType(0) == MVT::i32)
215 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
217 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
220 // shamt field must fit in 5 bits.
221 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
223 // Mips Address Mode! SDNode frameindex could possibily be a match
224 // since load and store instructions from stack used it.
225 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
227 //===----------------------------------------------------------------------===//
228 // Pattern fragment for load/store
229 //===----------------------------------------------------------------------===//
230 class UnalignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
231 LoadSDNode *LD = cast<LoadSDNode>(N);
232 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
235 class AlignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
236 LoadSDNode *LD = cast<LoadSDNode>(N);
237 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
240 class UnalignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
241 (Node node:$val, node:$ptr), [{
242 StoreSDNode *SD = cast<StoreSDNode>(N);
243 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
246 class AlignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
247 (Node node:$val, node:$ptr), [{
248 StoreSDNode *SD = cast<StoreSDNode>(N);
249 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
252 // Load/Store PatFrags.
253 def sextloadi16_a : AlignedLoad<sextloadi16>;
254 def zextloadi16_a : AlignedLoad<zextloadi16>;
255 def extloadi16_a : AlignedLoad<extloadi16>;
256 def load_a : AlignedLoad<load>;
257 def sextloadi32_a : AlignedLoad<sextloadi32>;
258 def zextloadi32_a : AlignedLoad<zextloadi32>;
259 def extloadi32_a : AlignedLoad<extloadi32>;
260 def truncstorei16_a : AlignedStore<truncstorei16>;
261 def store_a : AlignedStore<store>;
262 def truncstorei32_a : AlignedStore<truncstorei32>;
263 def sextloadi16_u : UnalignedLoad<sextloadi16>;
264 def zextloadi16_u : UnalignedLoad<zextloadi16>;
265 def extloadi16_u : UnalignedLoad<extloadi16>;
266 def load_u : UnalignedLoad<load>;
267 def sextloadi32_u : UnalignedLoad<sextloadi32>;
268 def zextloadi32_u : UnalignedLoad<zextloadi32>;
269 def extloadi32_u : UnalignedLoad<extloadi32>;
270 def truncstorei16_u : UnalignedStore<truncstorei16>;
271 def store_u : UnalignedStore<store>;
272 def truncstorei32_u : UnalignedStore<truncstorei32>;
274 //===----------------------------------------------------------------------===//
275 // Instructions specific format
276 //===----------------------------------------------------------------------===//
278 // Arithmetic and logical instructions with 3 register operands.
279 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
280 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
281 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
282 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
283 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
285 let isCommutable = isComm;
288 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
289 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
290 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
291 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
293 let isCommutable = isComm;
296 // Arithmetic and logical instructions with 2 register operands.
297 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
298 Operand Od, PatLeaf imm_type, RegisterClass RC> :
299 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
300 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
301 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
303 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
304 Operand Od, PatLeaf imm_type, RegisterClass RC> :
305 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
306 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
308 // Arithmetic Multiply ADD/SUB
309 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
310 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
311 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
312 !strconcat(instr_asm, "\t$rs, $rt"),
313 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
316 let isCommutable = isComm;
320 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
321 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
322 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
323 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
325 let isCommutable = 1;
329 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
330 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
332 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
333 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
334 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
338 // 32-bit shift instructions.
339 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
341 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
343 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
344 SDNode OpNode, RegisterClass RC>:
345 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
346 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
347 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
348 let shamt = isRotate;
351 // Load Upper Imediate
352 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
353 FI<op, (outs RC:$rt), (ins Imm:$imm16),
354 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
358 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
359 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
361 let Inst{25-21} = addr{20-16};
362 let Inst{15-0} = addr{15-0};
366 let canFoldAsLoad = 1 in
367 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
368 Operand MemOpnd, bit Pseudo>:
369 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
370 !strconcat(instr_asm, "\t$rt, $addr"),
371 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
372 let isPseudo = Pseudo;
375 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
376 Operand MemOpnd, bit Pseudo>:
377 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
378 !strconcat(instr_asm, "\t$rt, $addr"),
379 [(OpNode RC:$rt, addr:$addr)], IIStore> {
380 let isPseudo = Pseudo;
384 let canFoldAsLoad = 1 in
385 class LoadX<bits<6> op, RegisterClass RC,
387 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
392 class StoreX<bits<6> op, RegisterClass RC,
394 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
400 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
402 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
404 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
409 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
411 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
413 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
418 multiclass LoadX32<bits<6> op> {
419 def #NAME# : LoadX<op, CPURegs, mem>,
421 def _P8 : LoadX<op, CPURegs, mem64>,
425 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
427 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
429 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
434 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
436 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
438 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
443 multiclass StoreX32<bits<6> op> {
444 def #NAME# : StoreX<op, CPURegs, mem>,
446 def _P8 : StoreX<op, CPURegs, mem64>,
450 // Conditional Branch
451 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
452 CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
453 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
454 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
456 let isTerminator = 1;
457 let hasDelaySlot = 1;
460 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
462 CBranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
463 !strconcat(instr_asm, "\t$rs, $imm16"),
464 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
467 let isTerminator = 1;
468 let hasDelaySlot = 1;
472 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
474 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
475 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
476 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
481 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
482 PatLeaf imm_type, RegisterClass RC>:
483 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
484 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
485 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
488 // Unconditional branch
489 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
490 class JumpFJ<bits<6> op, string instr_asm>:
491 FJ<op, (outs), (ins jmptarget:$target),
492 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
494 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
495 isIndirectBranch = 1 in
496 class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
497 FR<op, func, (outs), (ins RC:$rs),
498 !strconcat(instr_asm, "\t$rs"), [(brind RC:$rs)], IIBranch> {
504 // Jump and Link (Call)
505 let isCall=1, hasDelaySlot=1,
506 // All calls clobber the non-callee saved registers...
507 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
508 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
509 class JumpLink<bits<6> op, string instr_asm>:
510 FJ<op, (outs), (ins calltarget:$target, variable_ops),
511 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
514 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
515 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
516 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch> {
522 class BranchLink<string instr_asm>:
523 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$imm16, variable_ops),
524 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
528 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
529 RegisterClass RC, list<Register> DefRegs>:
530 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
531 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
534 let isCommutable = 1;
538 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
539 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
541 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
542 RegisterClass RC, list<Register> DefRegs>:
543 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
544 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
545 [(op RC:$rs, RC:$rt)], itin> {
551 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
552 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
555 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
556 list<Register> UseRegs>:
557 FR<0x00, func, (outs RC:$rd), (ins),
558 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
565 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
566 list<Register> DefRegs>:
567 FR<0x00, func, (outs), (ins RC:$rs),
568 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
575 class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
576 FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
577 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
579 // Count Leading Ones/Zeros in Word
580 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
581 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
582 !strconcat(instr_asm, "\t$rd, $rs"),
583 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
584 Requires<[HasBitCount]> {
589 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
590 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
591 !strconcat(instr_asm, "\t$rd, $rs"),
592 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
593 Requires<[HasBitCount]> {
598 // Sign Extend in Register.
599 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>:
600 FR<0x1f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
601 !strconcat(instr_asm, "\t$rd, $rt"),
602 [(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> {
605 let Predicates = [HasSEInReg];
609 class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
610 FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt),
611 !strconcat(instr_asm, "\t$rd, $rt"),
612 [(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> {
615 let Predicates = [HasSwap];
619 class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
620 "rdhwr\t$rt, $rd", [], IIAlu> {
626 class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
627 list<dag> pattern, InstrItinClass itin>:
628 FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
629 pattern, itin>, Requires<[HasMips32r2]> {
636 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
637 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
639 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
640 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
641 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
643 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
644 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, Requires<[NotN64]>;
645 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, Requires<[IsN64]>;
648 // Atomic Compare & Swap.
649 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
651 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
652 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
653 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
655 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
656 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, Requires<[NotN64]>;
657 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, Requires<[IsN64]>;
660 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
661 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
662 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
666 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
667 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
668 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
670 let Constraints = "$rt = $dst";
673 //===----------------------------------------------------------------------===//
674 // Pseudo instructions
675 //===----------------------------------------------------------------------===//
677 // As stack alignment is always done with addiu, we need a 16-bit immediate
678 let Defs = [SP], Uses = [SP] in {
679 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
680 "!ADJCALLSTACKDOWN $amt",
681 [(callseq_start timm:$amt)]>;
682 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
683 "!ADJCALLSTACKUP $amt1",
684 [(callseq_end timm:$amt1, timm:$amt2)]>;
687 // Some assembly macros need to avoid pseudoinstructions and assembler
688 // automatic reodering, we should reorder ourselves.
689 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
690 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
691 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
692 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
694 // These macros are inserted to prevent GAS from complaining
695 // when using the AT register.
696 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
697 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
699 // When handling PIC code the assembler needs .cpload and .cprestore
700 // directives. If the real instructions corresponding these directives
701 // are used, we have the same behavior, but get also a bunch of warnings
702 // from the assembler.
703 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
704 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
706 let usesCustomInserter = 1 in {
707 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
708 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
709 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
710 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
711 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
712 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
713 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
714 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
715 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
716 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
717 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
718 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
719 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
720 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
721 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
722 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
723 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
724 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
726 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
727 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
728 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
730 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
731 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
732 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
735 //===----------------------------------------------------------------------===//
736 // Instruction definition
737 //===----------------------------------------------------------------------===//
739 //===----------------------------------------------------------------------===//
740 // MipsI Instructions
741 //===----------------------------------------------------------------------===//
743 /// Arithmetic Instructions (ALU Immediate)
744 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
745 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
746 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
747 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
748 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
749 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
750 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
751 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
753 /// Arithmetic Instructions (3-Operand, R-Type)
754 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
755 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
756 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
757 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
758 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
759 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
760 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
761 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
762 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
763 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
765 /// Shift Instructions
766 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
767 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
768 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
769 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
770 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
771 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
773 // Rotate Instructions
774 let Predicates = [HasMips32r2] in {
775 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
776 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
779 /// Load and Store Instructions
781 defm LB : LoadM32<0x20, "lb", sextloadi8>;
782 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
783 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
784 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
785 defm LW : LoadM32<0x23, "lw", load_a>;
786 defm SB : StoreM32<0x28, "sb", truncstorei8>;
787 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
788 defm SW : StoreM32<0x2b, "sw", store_a>;
791 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
792 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
793 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
794 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
795 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
797 /// Primitives for unaligned
798 defm LWL : LoadX32<0x22>;
799 defm LWR : LoadX32<0x26>;
800 defm SWL : StoreX32<0x2A>;
801 defm SWR : StoreX32<0x2E>;
803 let hasSideEffects = 1 in
804 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
805 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
810 let Inst{10-6} = stype;
814 /// Load-linked, Store-conditional
815 def LL : LLBase<0x30, "ll", CPURegs, mem>, Requires<[NotN64]>;
816 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]>;
817 def SC : SCBase<0x38, "sc", CPURegs, mem>, Requires<[NotN64]>;
818 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>;
820 /// Jump and Branch Instructions
821 def J : JumpFJ<0x02, "j">;
822 def JR : JumpFR<0x00, 0x08, "jr", CPURegs>;
823 def JAL : JumpLink<0x03, "jal">;
824 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
825 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
826 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
827 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
828 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
829 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
830 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
833 def BGEZAL : BranchLink<"bgezal">;
835 def BLTZAL : BranchLink<"bltzal">;
837 let isReturn=1, isTerminator=1, hasDelaySlot=1,
838 isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
839 def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
840 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
842 /// Multiply and Divide Instructions.
843 def MULT : Mult32<0x18, "mult", IIImul>;
844 def MULTu : Mult32<0x19, "multu", IIImul>;
845 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
846 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
848 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
849 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
850 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
851 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
853 /// Sign Ext In Register Instructions.
854 def SEB : SignExtInReg<0x10, "seb", i8>;
855 def SEH : SignExtInReg<0x18, "seh", i16>;
858 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
859 def CLO : CountLeading1<0x21, "clo", CPURegs>;
862 def WSBW : ByteSwap<0x20, 0x2, "wsbw">;
866 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
868 // FrameIndexes are legalized when they are operands from load/store
869 // instructions. The same not happens for stack address copies, so an
870 // add op with mem ComplexPattern is used and the stack address copy
871 // can be matched. It's similar to Sparc LEA_ADDRi
872 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
874 // DynAlloc node points to dynamically allocated stack space.
875 // $sp is added to the list of implicitly used registers to prevent dead code
876 // elimination from removing instructions that modify $sp.
878 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
881 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
882 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
883 def MSUB : MArithR<4, "msub", MipsMSub>;
884 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
886 // MUL is a assembly macro in the current used ISAs. In recent ISA's
887 // it is a real instruction.
888 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
889 Requires<[HasMips32]>;
891 def RDHWR : ReadHardware;
893 def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
894 (ins CPURegs:$rs, uimm16:$pos, size_ext:$sz),
896 (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
899 let Constraints = "$src = $rt" in
900 def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
901 (ins CPURegs:$rs, uimm16:$pos, size_ins:$sz, CPURegs:$src),
903 (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
907 //===----------------------------------------------------------------------===//
908 // Arbitrary patterns that map to one or more instructions
909 //===----------------------------------------------------------------------===//
912 def : Pat<(i32 immSExt16:$in),
913 (ADDiu ZERO, imm:$in)>;
914 def : Pat<(i32 immZExt16:$in),
915 (ORi ZERO, imm:$in)>;
917 // Arbitrary immediates
918 def : Pat<(i32 imm:$imm),
919 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
922 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
923 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
924 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
925 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
926 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
927 (ADDiu CPURegs:$src, imm:$imm)>;
930 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
931 (JAL tglobaladdr:$dst)>;
932 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
933 (JAL texternalsym:$dst)>;
934 //def : Pat<(MipsJmpLink CPURegs:$dst),
935 // (JALR CPURegs:$dst)>;
938 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
939 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
940 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
941 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
943 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
944 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
945 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
946 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
948 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
949 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
950 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
951 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
952 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
953 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
954 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
955 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
958 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
959 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
960 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
961 (ADDiu CPURegs:$gp, tconstpool:$in)>;
964 def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
965 (ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
968 def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
969 def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
970 def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
971 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
974 class WrapperPICPat<SDNode node>:
975 Pat<(MipsWrapperPIC node:$in),
976 (ADDiu GP, node:$in)>;
978 def : WrapperPICPat<tglobaladdr>;
979 def : WrapperPICPat<tconstpool>;
980 def : WrapperPICPat<texternalsym>;
981 def : WrapperPICPat<tblockaddress>;
982 def : WrapperPICPat<tjumptable>;
984 // Mips does not have "not", so we expand our way
985 def : Pat<(not CPURegs:$in),
986 (NOR CPURegs:$in, ZERO)>;
988 // extended load and stores
989 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
990 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
991 def : Pat<(extloadi16_a addr:$src), (LHu addr:$src)>;
992 def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>;
995 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
998 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
999 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1000 Instruction SLTiuOp, Register ZEROReg> {
1001 def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1002 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1003 def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1004 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1006 def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1007 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1008 def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1009 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1010 def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1011 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1012 def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1013 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1015 def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1016 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1017 def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1018 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1020 def : Pat<(brcond RC:$cond, bb:$dst),
1021 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1024 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1027 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1028 Instruction SLTuOp, Register ZEROReg> {
1029 def : Pat<(seteq RC:$lhs, RC:$rhs),
1030 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1031 def : Pat<(setne RC:$lhs, RC:$rhs),
1032 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1035 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1036 def : Pat<(setle RC:$lhs, RC:$rhs),
1037 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1038 def : Pat<(setule RC:$lhs, RC:$rhs),
1039 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1042 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1043 def : Pat<(setgt RC:$lhs, RC:$rhs),
1044 (SLTOp RC:$rhs, RC:$lhs)>;
1045 def : Pat<(setugt RC:$lhs, RC:$rhs),
1046 (SLTuOp RC:$rhs, RC:$lhs)>;
1049 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1050 def : Pat<(setge RC:$lhs, RC:$rhs),
1051 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1052 def : Pat<(setuge RC:$lhs, RC:$rhs),
1053 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1056 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1057 Instruction SLTiuOp> {
1058 def : Pat<(setge RC:$lhs, immSExt16:$rhs),
1059 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1060 def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
1061 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1064 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1065 defm : SetlePats<CPURegs, SLT, SLTu>;
1066 defm : SetgtPats<CPURegs, SLT, SLTu>;
1067 defm : SetgePats<CPURegs, SLT, SLTu>;
1068 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1070 // select MipsDynAlloc
1071 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1073 //===----------------------------------------------------------------------===//
1074 // Floating Point Support
1075 //===----------------------------------------------------------------------===//
1077 include "MipsInstrFPU.td"
1078 include "Mips64InstrInfo.td"
1079 include "MipsCondMov.td"