1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
55 // Hi and Lo nodes are used to handle global addresses. Used on
56 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
57 // static model. (nothing to do with Mips Registers Hi and Lo)
58 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
59 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
60 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
62 // TlsGd node is used to handle General Dynamic TLS
63 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
65 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
66 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
67 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
70 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
73 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
75 // These are target-independent nodes, but have target-specific formats.
76 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
77 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
78 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
79 [SDNPHasChain, SDNPSideEffect,
80 SDNPOptInGlue, SDNPOutGlue]>;
83 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
84 [SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
93 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
95 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
98 // Target constant nodes that are not part of any isel patterns and remain
99 // unchanged can cause instructions with illegal operands to be emitted.
100 // Wrapper node patterns give the instruction selector a chance to replace
101 // target constant nodes that would otherwise remain unchanged with ADDiu
102 // nodes. Without these wrapper node patterns, the following conditional move
103 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
105 // movn %got(d)($gp), %got(c)($gp), $4
106 // This instruction is illegal since movn can take only register operands.
108 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
110 // Pointer to dynamically allocated stack area.
111 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
112 [SDNPHasChain, SDNPInGlue]>;
114 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
116 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
117 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
119 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
122 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
123 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
125 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
126 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
127 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
129 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
133 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 //===----------------------------------------------------------------------===//
137 // Mips Instruction Predicate Definitions.
138 //===----------------------------------------------------------------------===//
139 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
140 AssemblerPredicate<"FeatureSEInReg">;
141 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
142 AssemblerPredicate<"FeatureBitCount">;
143 def HasSwap : Predicate<"Subtarget.hasSwap()">,
144 AssemblerPredicate<"FeatureSwap">;
145 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
146 AssemblerPredicate<"FeatureCondMov">;
147 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
148 AssemblerPredicate<"FeatureMips32">;
149 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
150 AssemblerPredicate<"FeatureMips32r2">;
151 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
152 AssemblerPredicate<"FeatureMips64">;
153 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
154 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
155 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
156 AssemblerPredicate<"!FeatureMips64">;
157 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
158 AssemblerPredicate<"FeatureMips64r2">;
159 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
160 AssemblerPredicate<"FeatureN64">;
161 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
162 AssemblerPredicate<"!FeatureN64">;
163 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
164 AssemblerPredicate<"FeatureMips16">;
165 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
166 AssemblerPredicate<"FeatureMips32">;
167 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
168 AssemblerPredicate<"FeatureMips32">;
169 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
170 AssemblerPredicate<"FeatureMips32">;
171 def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
172 AssemblerPredicate<"!FeatureMips16">;
174 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
175 let Predicates = [HasStandardEncoding];
178 //===----------------------------------------------------------------------===//
179 // Instruction format superclass
180 //===----------------------------------------------------------------------===//
182 include "MipsInstrFormats.td"
184 //===----------------------------------------------------------------------===//
185 // Mips Operand, Complex Patterns and Transformations Definitions.
186 //===----------------------------------------------------------------------===//
188 // Instruction operand types
189 def jmptarget : Operand<OtherVT> {
190 let EncoderMethod = "getJumpTargetOpValue";
192 def brtarget : Operand<OtherVT> {
193 let EncoderMethod = "getBranchTargetOpValue";
194 let OperandType = "OPERAND_PCREL";
195 let DecoderMethod = "DecodeBranchTarget";
197 def calltarget : Operand<iPTR> {
198 let EncoderMethod = "getJumpTargetOpValue";
200 def calltarget64: Operand<i64>;
201 def simm16 : Operand<i32> {
202 let DecoderMethod= "DecodeSimm16";
204 def simm16_64 : Operand<i64>;
205 def shamt : Operand<i32>;
208 def uimm16 : Operand<i32> {
209 let PrintMethod = "printUnsignedImm";
212 def MipsMemAsmOperand : AsmOperandClass {
214 let ParserMethod = "parseMemOperand";
218 def mem : Operand<i32> {
219 let PrintMethod = "printMemOperand";
220 let MIOperandInfo = (ops CPURegs, simm16);
221 let EncoderMethod = "getMemEncoding";
222 let ParserMatchClass = MipsMemAsmOperand;
225 def mem64 : Operand<i64> {
226 let PrintMethod = "printMemOperand";
227 let MIOperandInfo = (ops CPU64Regs, simm16_64);
228 let EncoderMethod = "getMemEncoding";
229 let ParserMatchClass = MipsMemAsmOperand;
232 def mem_ea : Operand<i32> {
233 let PrintMethod = "printMemOperandEA";
234 let MIOperandInfo = (ops CPURegs, simm16);
235 let EncoderMethod = "getMemEncoding";
238 def mem_ea_64 : Operand<i64> {
239 let PrintMethod = "printMemOperandEA";
240 let MIOperandInfo = (ops CPU64Regs, simm16_64);
241 let EncoderMethod = "getMemEncoding";
244 // size operand of ext instruction
245 def size_ext : Operand<i32> {
246 let EncoderMethod = "getSizeExtEncoding";
247 let DecoderMethod = "DecodeExtSize";
250 // size operand of ins instruction
251 def size_ins : Operand<i32> {
252 let EncoderMethod = "getSizeInsEncoding";
253 let DecoderMethod = "DecodeInsSize";
256 // Transformation Function - get the lower 16 bits.
257 def LO16 : SDNodeXForm<imm, [{
258 return getImm(N, N->getZExtValue() & 0xFFFF);
261 // Transformation Function - get the higher 16 bits.
262 def HI16 : SDNodeXForm<imm, [{
263 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
266 // Node immediate fits as 16-bit sign extended on target immediate.
268 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
270 // Node immediate fits as 16-bit zero extended on target immediate.
271 // The LO16 param means that only the lower 16 bits of the node
272 // immediate are caught.
274 def immZExt16 : PatLeaf<(imm), [{
275 if (N->getValueType(0) == MVT::i32)
276 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
278 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
281 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
282 def immLow16Zero : PatLeaf<(imm), [{
283 int64_t Val = N->getSExtValue();
284 return isInt<32>(Val) && !(Val & 0xffff);
287 // shamt field must fit in 5 bits.
288 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
290 // Mips Address Mode! SDNode frameindex could possibily be a match
291 // since load and store instructions from stack used it.
293 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
295 //===----------------------------------------------------------------------===//
296 // Pattern fragment for load/store
297 //===----------------------------------------------------------------------===//
298 class UnalignedLoad<PatFrag Node> :
299 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
300 LoadSDNode *LD = cast<LoadSDNode>(N);
301 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
304 class AlignedLoad<PatFrag Node> :
305 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
306 LoadSDNode *LD = cast<LoadSDNode>(N);
307 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
310 class UnalignedStore<PatFrag Node> :
311 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
312 StoreSDNode *SD = cast<StoreSDNode>(N);
313 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
316 class AlignedStore<PatFrag Node> :
317 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
318 StoreSDNode *SD = cast<StoreSDNode>(N);
319 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
322 // Load/Store PatFrags.
323 def sextloadi16_a : AlignedLoad<sextloadi16>;
324 def zextloadi16_a : AlignedLoad<zextloadi16>;
325 def extloadi16_a : AlignedLoad<extloadi16>;
326 def load_a : AlignedLoad<load>;
327 def sextloadi32_a : AlignedLoad<sextloadi32>;
328 def zextloadi32_a : AlignedLoad<zextloadi32>;
329 def extloadi32_a : AlignedLoad<extloadi32>;
330 def truncstorei16_a : AlignedStore<truncstorei16>;
331 def store_a : AlignedStore<store>;
332 def truncstorei32_a : AlignedStore<truncstorei32>;
333 def sextloadi16_u : UnalignedLoad<sextloadi16>;
334 def zextloadi16_u : UnalignedLoad<zextloadi16>;
335 def extloadi16_u : UnalignedLoad<extloadi16>;
336 def load_u : UnalignedLoad<load>;
337 def sextloadi32_u : UnalignedLoad<sextloadi32>;
338 def zextloadi32_u : UnalignedLoad<zextloadi32>;
339 def extloadi32_u : UnalignedLoad<extloadi32>;
340 def truncstorei16_u : UnalignedStore<truncstorei16>;
341 def store_u : UnalignedStore<store>;
342 def truncstorei32_u : UnalignedStore<truncstorei32>;
344 //===----------------------------------------------------------------------===//
345 // Instructions specific format
346 //===----------------------------------------------------------------------===//
348 // Arithmetic and logical instructions with 3 register operands.
349 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
350 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
351 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
352 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
353 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
355 let isCommutable = isComm;
356 let isReMaterializable = 1;
359 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
360 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
361 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
362 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
364 let isCommutable = isComm;
367 // Arithmetic and logical instructions with 2 register operands.
368 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
369 Operand Od, PatLeaf imm_type, RegisterClass RC> :
370 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
371 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
372 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
373 let isReMaterializable = 1;
376 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
377 Operand Od, PatLeaf imm_type, RegisterClass RC> :
378 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
379 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
381 // Arithmetic Multiply ADD/SUB
382 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
383 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
384 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
385 !strconcat(instr_asm, "\t$rs, $rt"),
386 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
389 let isCommutable = isComm;
393 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
394 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
395 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
396 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
398 let isCommutable = 1;
402 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
403 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
405 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
406 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
407 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
411 // 32-bit shift instructions.
412 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
414 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
416 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
417 SDNode OpNode, RegisterClass RC>:
418 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
419 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
420 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
421 let shamt = isRotate;
424 // Load Upper Imediate
425 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
426 FI<op, (outs RC:$rt), (ins Imm:$imm16),
427 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
429 let neverHasSideEffects = 1;
430 let isReMaterializable = 1;
433 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
434 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
436 let Inst{25-21} = addr{20-16};
437 let Inst{15-0} = addr{15-0};
438 let DecoderMethod = "DecodeMem";
442 let canFoldAsLoad = 1 in
443 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
444 Operand MemOpnd, bit Pseudo>:
445 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
446 !strconcat(instr_asm, "\t$rt, $addr"),
447 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
448 let isPseudo = Pseudo;
451 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
452 Operand MemOpnd, bit Pseudo>:
453 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
454 !strconcat(instr_asm, "\t$rt, $addr"),
455 [(OpNode RC:$rt, addr:$addr)], IIStore> {
456 let isPseudo = Pseudo;
460 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
462 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
463 Requires<[NotN64, HasStandardEncoding]>;
464 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
465 Requires<[IsN64, HasStandardEncoding]> {
466 let DecoderNamespace = "Mips64";
467 let isCodeGenOnly = 1;
472 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
474 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
475 Requires<[NotN64, HasStandardEncoding]>;
476 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
477 Requires<[IsN64, HasStandardEncoding]> {
478 let DecoderNamespace = "Mips64";
479 let isCodeGenOnly = 1;
484 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
486 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
487 Requires<[NotN64, HasStandardEncoding]>;
488 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
489 Requires<[IsN64, HasStandardEncoding]> {
490 let DecoderNamespace = "Mips64";
491 let isCodeGenOnly = 1;
496 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
498 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
499 Requires<[NotN64, HasStandardEncoding]>;
500 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
501 Requires<[IsN64, HasStandardEncoding]> {
502 let DecoderNamespace = "Mips64";
503 let isCodeGenOnly = 1;
507 // Load/Store Left/Right
508 let canFoldAsLoad = 1 in
509 class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
510 RegisterClass RC, Operand MemOpnd> :
511 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
512 !strconcat(instr_asm, "\t$rt, $addr"),
513 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
514 string Constraints = "$src = $rt";
517 class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
518 RegisterClass RC, Operand MemOpnd>:
519 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
520 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
523 // 32-bit load left/right.
524 multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
525 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
526 Requires<[NotN64, HasStandardEncoding]>;
527 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
528 Requires<[IsN64, HasStandardEncoding]> {
529 let DecoderNamespace = "Mips64";
530 let isCodeGenOnly = 1;
534 // 64-bit load left/right.
535 multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
536 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
537 Requires<[NotN64, HasStandardEncoding]>;
538 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
539 Requires<[IsN64, HasStandardEncoding]> {
540 let DecoderNamespace = "Mips64";
541 let isCodeGenOnly = 1;
545 // 32-bit store left/right.
546 multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
547 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
548 Requires<[NotN64, HasStandardEncoding]>;
549 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
550 Requires<[IsN64, HasStandardEncoding]> {
551 let DecoderNamespace = "Mips64";
552 let isCodeGenOnly = 1;
556 // 64-bit store left/right.
557 multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
558 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
559 Requires<[NotN64, HasStandardEncoding]>;
560 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
561 Requires<[IsN64, HasStandardEncoding]> {
562 let DecoderNamespace = "Mips64";
563 let isCodeGenOnly = 1;
567 // Conditional Branch
568 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
569 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
570 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
571 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
573 let isTerminator = 1;
574 let hasDelaySlot = 1;
578 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
580 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
581 !strconcat(instr_asm, "\t$rs, $imm16"),
582 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
585 let isTerminator = 1;
586 let hasDelaySlot = 1;
591 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
593 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
594 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
595 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
600 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
601 PatLeaf imm_type, RegisterClass RC>:
602 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
603 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
604 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
608 class JumpFJ<bits<6> op, string instr_asm>:
609 FJ<op, (outs), (ins jmptarget:$target),
610 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> {
614 let hasDelaySlot = 1;
615 let Predicates = [RelocStatic, HasStandardEncoding];
616 let DecoderMethod = "DecodeJumpTarget";
620 // Unconditional branch
621 class UncondBranch<bits<6> op, string instr_asm>:
622 BranchBase<op, (outs), (ins brtarget:$imm16),
623 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
627 let isTerminator = 1;
629 let hasDelaySlot = 1;
630 let Predicates = [RelocPIC, HasStandardEncoding];
634 // Base class for indirect branch and return instruction classes.
635 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
636 class JumpFR<RegisterClass RC, list<dag> pattern>:
637 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", pattern, IIBranch> {
644 class IndirectBranch<RegisterClass RC>: JumpFR<RC, [(brind RC:$rs)]> {
646 let isIndirectBranch = 1;
649 // Return instruction
650 class RetBase<RegisterClass RC>: JumpFR<RC, []> {
652 let isCodeGenOnly = 1;
654 let hasExtraSrcRegAllocReq = 1;
657 // Jump and Link (Call)
658 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
659 class JumpLink<bits<6> op, string instr_asm>:
660 FJ<op, (outs), (ins calltarget:$target),
661 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
663 let DecoderMethod = "DecodeJumpTarget";
666 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
668 FR<op, func, (outs), (ins RC:$rs),
669 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
675 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
676 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
677 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
683 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
684 RegisterClass RC, list<Register> DefRegs>:
685 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
686 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
689 let isCommutable = 1;
691 let neverHasSideEffects = 1;
694 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
695 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
697 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
698 RegisterClass RC, list<Register> DefRegs>:
699 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
700 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
701 [(op RC:$rs, RC:$rt)], itin> {
707 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
708 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
711 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
712 list<Register> UseRegs>:
713 FR<0x00, func, (outs RC:$rd), (ins),
714 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
719 let neverHasSideEffects = 1;
722 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
723 list<Register> DefRegs>:
724 FR<0x00, func, (outs), (ins RC:$rs),
725 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
730 let neverHasSideEffects = 1;
733 class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
734 FMem<opc, (outs RC:$rt), (ins Mem:$addr),
735 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
736 let isCodeGenOnly = 1;
739 // Count Leading Ones/Zeros in Word
740 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
741 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
742 !strconcat(instr_asm, "\t$rd, $rs"),
743 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
744 Requires<[HasBitCount, HasStandardEncoding]> {
749 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
750 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
751 !strconcat(instr_asm, "\t$rd, $rs"),
752 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
753 Requires<[HasBitCount, HasStandardEncoding]> {
758 // Sign Extend in Register.
759 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
761 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
762 !strconcat(instr_asm, "\t$rd, $rt"),
763 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
766 let Predicates = [HasSEInReg, HasStandardEncoding];
770 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
771 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
772 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
775 let Predicates = [HasSwap, HasStandardEncoding];
776 let neverHasSideEffects = 1;
780 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
781 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
782 "rdhwr\t$rt, $rd", [], IIAlu> {
788 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
789 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
790 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
791 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
796 let Predicates = [HasMips32r2, HasStandardEncoding];
799 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
800 FR<0x1f, _funct, (outs RC:$rt),
801 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
802 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
803 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
809 let Predicates = [HasMips32r2, HasStandardEncoding];
810 let Constraints = "$src = $rt";
813 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
814 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
816 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
817 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
818 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
820 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
821 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
822 Requires<[NotN64, HasStandardEncoding]>;
823 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
824 Requires<[IsN64, HasStandardEncoding]> {
825 let DecoderNamespace = "Mips64";
829 // Atomic Compare & Swap.
830 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
832 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
833 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
834 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
836 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
837 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
838 Requires<[NotN64, HasStandardEncoding]>;
839 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
840 Requires<[IsN64, HasStandardEncoding]> {
841 let DecoderNamespace = "Mips64";
845 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
846 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
847 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
851 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
852 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
853 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
855 let Constraints = "$rt = $dst";
858 //===----------------------------------------------------------------------===//
859 // Pseudo instructions
860 //===----------------------------------------------------------------------===//
863 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
864 def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>;
866 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
867 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
868 "!ADJCALLSTACKDOWN $amt",
869 [(callseq_start timm:$amt)]>;
870 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
871 "!ADJCALLSTACKUP $amt1",
872 [(callseq_end timm:$amt1, timm:$amt2)]>;
875 // When handling PIC code the assembler needs .cpload and .cprestore
876 // directives. If the real instructions corresponding these directives
877 // are used, we have the same behavior, but get also a bunch of warnings
878 // from the assembler.
879 let neverHasSideEffects = 1 in
880 def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp),
881 ".cprestore\t$loc", []>;
883 let usesCustomInserter = 1 in {
884 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
885 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
886 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
887 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
888 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
889 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
890 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
891 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
892 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
893 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
894 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
895 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
896 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
897 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
898 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
899 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
900 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
901 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
903 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
904 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
905 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
907 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
908 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
909 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
912 //===----------------------------------------------------------------------===//
913 // Instruction definition
914 //===----------------------------------------------------------------------===//
916 //===----------------------------------------------------------------------===//
917 // MipsI Instructions
918 //===----------------------------------------------------------------------===//
920 /// Arithmetic Instructions (ALU Immediate)
921 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
922 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
923 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
924 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
925 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
926 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
927 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
928 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
930 /// Arithmetic Instructions (3-Operand, R-Type)
931 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
932 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
933 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
934 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
935 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
936 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
937 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
938 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
939 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
940 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
942 /// Shift Instructions
943 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
944 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
945 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
946 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
947 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
948 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
950 // Rotate Instructions
951 let Predicates = [HasMips32r2, HasStandardEncoding] in {
952 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
953 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
956 /// Load and Store Instructions
958 defm LB : LoadM32<0x20, "lb", sextloadi8>;
959 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
960 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
961 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
962 defm LW : LoadM32<0x23, "lw", load_a>;
963 defm SB : StoreM32<0x28, "sb", truncstorei8>;
964 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
965 defm SW : StoreM32<0x2b, "sw", store_a>;
968 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
969 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
970 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
971 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
972 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
974 /// load/store left/right
975 defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
976 defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
977 defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
978 defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
980 let hasSideEffects = 1 in
981 def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
982 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
987 let Inst{10-6} = stype;
991 /// Load-linked, Store-conditional
992 def LL : LLBase<0x30, "ll", CPURegs, mem>,
993 Requires<[NotN64, HasStandardEncoding]>;
994 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
995 Requires<[IsN64, HasStandardEncoding]> {
996 let DecoderNamespace = "Mips64";
999 def SC : SCBase<0x38, "sc", CPURegs, mem>,
1000 Requires<[NotN64, HasStandardEncoding]>;
1001 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
1002 Requires<[IsN64, HasStandardEncoding]> {
1003 let DecoderNamespace = "Mips64";
1006 /// Jump and Branch Instructions
1007 def J : JumpFJ<0x02, "j">;
1008 def JR : IndirectBranch<CPURegs>;
1009 def B : UncondBranch<0x04, "b">;
1010 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
1011 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
1012 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
1013 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
1014 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
1015 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
1017 let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
1018 hasDelaySlot = 1, Defs = [RA] in
1019 def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
1021 def JAL : JumpLink<0x03, "jal">;
1022 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
1023 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
1024 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
1026 def RET : RetBase<CPURegs>;
1028 /// Multiply and Divide Instructions.
1029 def MULT : Mult32<0x18, "mult", IIImul>;
1030 def MULTu : Mult32<0x19, "multu", IIImul>;
1031 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
1032 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
1034 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
1035 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
1036 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
1037 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
1039 /// Sign Ext In Register Instructions.
1040 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
1041 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
1044 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
1045 def CLO : CountLeading1<0x21, "clo", CPURegs>;
1047 /// Word Swap Bytes Within Halfwords
1048 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
1052 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
1054 // FrameIndexes are legalized when they are operands from load/store
1055 // instructions. The same not happens for stack address copies, so an
1056 // add op with mem ComplexPattern is used and the stack address copy
1057 // can be matched. It's similar to Sparc LEA_ADDRi
1058 def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
1060 // DynAlloc node points to dynamically allocated stack space.
1061 // $sp is added to the list of implicitly used registers to prevent dead code
1062 // elimination from removing instructions that modify $sp.
1064 def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
1067 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
1068 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
1069 def MSUB : MArithR<4, "msub", MipsMSub>;
1070 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
1072 // MUL is a assembly macro in the current used ISAs. In recent ISA's
1073 // it is a real instruction.
1074 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
1075 Requires<[HasMips32, HasStandardEncoding]>;
1077 def RDHWR : ReadHardware<CPURegs, HWRegs>;
1079 def EXT : ExtBase<0, "ext", CPURegs>;
1080 def INS : InsBase<4, "ins", CPURegs>;
1082 //===----------------------------------------------------------------------===//
1083 // Instruction aliases
1084 //===----------------------------------------------------------------------===//
1085 def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
1086 def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
1087 def : InstAlias<"addu $rs,$rt,$imm",
1088 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1089 def : InstAlias<"add $rs,$rt,$imm",
1090 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1091 def : InstAlias<"and $rs,$rt,$imm",
1092 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1093 def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
1094 def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
1095 def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
1096 def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
1097 def : InstAlias<"slt $rs,$rt,$imm",
1098 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1099 def : InstAlias<"xor $rs,$rt,$imm",
1100 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1102 //===----------------------------------------------------------------------===//
1103 // Arbitrary patterns that map to one or more instructions
1104 //===----------------------------------------------------------------------===//
1107 def : MipsPat<(i32 immSExt16:$in),
1108 (ADDiu ZERO, imm:$in)>;
1109 def : MipsPat<(i32 immZExt16:$in),
1110 (ORi ZERO, imm:$in)>;
1111 def : MipsPat<(i32 immLow16Zero:$in),
1112 (LUi (HI16 imm:$in))>;
1114 // Arbitrary immediates
1115 def : MipsPat<(i32 imm:$imm),
1116 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1118 // Carry MipsPatterns
1119 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1120 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1121 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1122 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1123 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1124 (ADDiu CPURegs:$src, imm:$imm)>;
1127 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1128 (JAL tglobaladdr:$dst)>;
1129 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1130 (JAL texternalsym:$dst)>;
1131 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1132 // (JALR CPURegs:$dst)>;
1135 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1136 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1137 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1138 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1139 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1141 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1142 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1143 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1144 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1145 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1147 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1148 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1149 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1150 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1151 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1152 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1153 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1154 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1155 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1156 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1159 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1160 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1161 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1162 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1165 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1166 MipsPat<(MipsWrapper RC:$gp, node:$in),
1167 (ADDiuOp RC:$gp, node:$in)>;
1169 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1170 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1171 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1172 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1173 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1174 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1176 // Mips does not have "not", so we expand our way
1177 def : MipsPat<(not CPURegs:$in),
1178 (NOR CPURegs:$in, ZERO)>;
1181 let Predicates = [NotN64, HasStandardEncoding] in {
1182 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1183 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1184 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
1185 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
1187 let Predicates = [IsN64, HasStandardEncoding] in {
1188 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1189 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1190 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
1191 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
1195 let Predicates = [NotN64, HasStandardEncoding] in {
1196 def : MipsPat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1197 def : MipsPat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
1199 let Predicates = [IsN64, HasStandardEncoding] in {
1200 def : MipsPat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1201 def : MipsPat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
1205 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1206 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1207 Instruction SLTiuOp, Register ZEROReg> {
1208 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1209 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1210 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1211 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1213 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1214 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1215 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1216 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1217 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1218 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1219 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1220 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1222 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1223 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1224 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1225 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1227 def : MipsPat<(brcond RC:$cond, bb:$dst),
1228 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1231 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1234 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1235 Instruction SLTuOp, Register ZEROReg> {
1236 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1237 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1238 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1239 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1242 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1243 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1244 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1245 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1246 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1249 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1250 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1251 (SLTOp RC:$rhs, RC:$lhs)>;
1252 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1253 (SLTuOp RC:$rhs, RC:$lhs)>;
1256 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1257 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1258 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1259 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1260 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1263 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1264 Instruction SLTiuOp> {
1265 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1266 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1267 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1268 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1271 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1272 defm : SetlePats<CPURegs, SLT, SLTu>;
1273 defm : SetgtPats<CPURegs, SLT, SLTu>;
1274 defm : SetgePats<CPURegs, SLT, SLTu>;
1275 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1277 // select MipsDynAlloc
1278 def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1281 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1283 //===----------------------------------------------------------------------===//
1284 // Floating Point Support
1285 //===----------------------------------------------------------------------===//
1287 include "MipsInstrFPU.td"
1288 include "Mips64InstrInfo.td"
1289 include "MipsCondMov.td"
1294 include "Mips16InstrFormats.td"
1295 include "Mips16InstrInfo.td"