1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "MipsInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Mips profiles and nodes
22 //===----------------------------------------------------------------------===//
24 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
25 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
30 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
31 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
32 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
33 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def SDT_MipsDivRem : SDTypeProfile<0, 2,
41 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
42 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
45 // Hi and Lo nodes are used to handle global addresses. Used on
46 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
47 // static model. (nothing to do with Mips Registers Hi and Lo)
48 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
49 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
50 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
53 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
56 // These are target-independent nodes, but have target-specific formats.
57 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
58 [SDNPHasChain, SDNPOutGlue]>;
59 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
60 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
63 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
64 [SDNPOptInGlue, SDNPOutGlue]>;
65 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
66 [SDNPOptInGlue, SDNPOutGlue]>;
67 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
68 [SDNPOptInGlue, SDNPOutGlue]>;
69 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
70 [SDNPOptInGlue, SDNPOutGlue]>;
73 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
75 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
78 //===----------------------------------------------------------------------===//
79 // Mips Instruction Predicate Definitions.
80 //===----------------------------------------------------------------------===//
81 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
82 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
83 def HasSwap : Predicate<"Subtarget.hasSwap()">;
84 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
85 def IsMips32 : Predicate<"Subtarget.isMips32()">;
86 def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
88 //===----------------------------------------------------------------------===//
89 // Mips Operand, Complex Patterns and Transformations Definitions.
90 //===----------------------------------------------------------------------===//
92 // Instruction operand types
93 def brtarget : Operand<OtherVT>;
94 def calltarget : Operand<i32>;
95 def simm16 : Operand<i32>;
96 def shamt : Operand<i32>;
99 def uimm16 : Operand<i32> {
100 let PrintMethod = "printUnsignedImm";
104 def mem : Operand<i32> {
105 let PrintMethod = "printMemOperand";
106 let MIOperandInfo = (ops simm16, CPURegs);
109 // Transformation Function - get the lower 16 bits.
110 def LO16 : SDNodeXForm<imm, [{
111 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
114 // Transformation Function - get the higher 16 bits.
115 def HI16 : SDNodeXForm<imm, [{
116 return getI32Imm((unsigned)N->getZExtValue() >> 16);
119 // Node immediate fits as 16-bit sign extended on target immediate.
121 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
123 // Node immediate fits as 16-bit zero extended on target immediate.
124 // The LO16 param means that only the lower 16 bits of the node
125 // immediate are caught.
127 def immZExt16 : PatLeaf<(imm), [{
128 if (N->getValueType(0) == MVT::i32)
129 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
131 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
134 // shamt field must fit in 5 bits.
135 def immZExt5 : PatLeaf<(imm), [{
136 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
139 // Mips Address Mode! SDNode frameindex could possibily be a match
140 // since load and store instructions from stack used it.
141 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
143 //===----------------------------------------------------------------------===//
144 // Instructions specific format
145 //===----------------------------------------------------------------------===//
147 // Arithmetic 3 register operands
148 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
149 InstrItinClass itin, bit isComm = 0>:
150 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
151 !strconcat(instr_asm, "\t$dst, $b, $c"),
152 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin> {
153 let isCommutable = isComm;
156 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm, bit isComm = 0>:
157 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
158 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu> {
159 let isCommutable = isComm;
162 // Arithmetic 2 register operands
163 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
164 Operand Od, PatLeaf imm_type> :
165 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
166 !strconcat(instr_asm, "\t$dst, $b, $c"),
167 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
169 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
170 Operand Od, PatLeaf imm_type> :
171 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
172 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
174 // Arithmetic Multiply ADD/SUB
175 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
176 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
177 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
178 !strconcat(instr_asm, "\t$rs, $rt"),
179 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
180 let isCommutable = isComm;
184 let isCommutable = 1 in
185 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
186 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
187 !strconcat(instr_asm, "\t$dst, $b, $c"),
188 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
190 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
191 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
192 !strconcat(instr_asm, "\t$dst, $b, $c"),
193 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
195 let isCommutable = 1 in
196 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
197 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
198 !strconcat(instr_asm, "\t$dst, $b, $c"),
199 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
202 class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
204 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
205 !strconcat(instr_asm, "\t$dst, $b, $c"),
206 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu> {
210 class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
212 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
213 !strconcat(instr_asm, "\t$dst, $b, $c"),
214 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
218 // Load Upper Imediate
219 class LoadUpper<bits<6> op, string instr_asm>:
223 !strconcat(instr_asm, "\t$dst, $imm"),
227 let canFoldAsLoad = 1, hasDelaySlot = 1 in
228 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
229 FI<op, (outs CPURegs:$dst), (ins mem:$addr),
230 !strconcat(instr_asm, "\t$dst, $addr"),
231 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
233 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
234 FI<op, (outs), (ins CPURegs:$dst, mem:$addr),
235 !strconcat(instr_asm, "\t$dst, $addr"),
236 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
238 // Conditional Branch
239 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
240 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
241 FI<op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
242 !strconcat(instr_asm, "\t$a, $b, $offset"),
243 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
246 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
247 FI<op, (outs), (ins CPURegs:$src, brtarget:$offset),
248 !strconcat(instr_asm, "\t$src, $offset"),
249 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
254 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
256 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
257 !strconcat(instr_asm, "\t$dst, $b, $c"),
258 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
261 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
262 Operand Od, PatLeaf imm_type>:
263 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
264 !strconcat(instr_asm, "\t$dst, $b, $c"),
265 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
268 // Unconditional branch
269 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
270 class JumpFJ<bits<6> op, string instr_asm>:
271 FJ<op, (outs), (ins brtarget:$target),
272 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
274 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
275 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
276 FR<op, func, (outs), (ins CPURegs:$target),
277 !strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
279 // Jump and Link (Call)
280 let isCall=1, hasDelaySlot=1,
281 // All calls clobber the non-callee saved registers...
282 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
283 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
284 class JumpLink<bits<6> op, string instr_asm>:
285 FJ<op, (outs), (ins calltarget:$target, variable_ops),
286 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
290 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
291 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
292 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
294 class BranchLink<string instr_asm>:
295 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
296 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
300 let Defs = [HI, LO] in {
301 let isCommutable = 1 in
302 class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
303 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
304 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
306 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
307 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
308 !strconcat(instr_asm, "\t$$zero, $a, $b"),
309 [(op CPURegs:$a, CPURegs:$b)], itin>;
313 class MoveFromLOHI<bits<6> func, string instr_asm>:
314 FR<0x00, func, (outs CPURegs:$dst), (ins),
315 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
317 class MoveToLOHI<bits<6> func, string instr_asm>:
318 FR<0x00, func, (outs), (ins CPURegs:$src),
319 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
321 class EffectiveAddress<string instr_asm> :
322 FI<0x09, (outs CPURegs:$dst), (ins mem:$addr),
323 instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
325 // Count Leading Ones/Zeros in Word
326 class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
327 FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
328 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
329 Requires<[HasBitCount]> {
334 // Sign Extend in Register.
335 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
336 FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
337 !strconcat(instr_asm, "\t$dst, $src"),
338 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
341 class ByteSwap<bits<6> func, string instr_asm>:
342 FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
343 !strconcat(instr_asm, "\t$dst, $src"),
344 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
347 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
348 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
349 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
352 //===----------------------------------------------------------------------===//
353 // Pseudo instructions
354 //===----------------------------------------------------------------------===//
356 // As stack alignment is always done with addiu, we need a 16-bit immediate
357 let Defs = [SP], Uses = [SP] in {
358 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
359 "!ADJCALLSTACKDOWN $amt",
360 [(callseq_start timm:$amt)]>;
361 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
362 "!ADJCALLSTACKUP $amt1",
363 [(callseq_end timm:$amt1, timm:$amt2)]>;
366 // Some assembly macros need to avoid pseudoinstructions and assembler
367 // automatic reodering, we should reorder ourselves.
368 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
369 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
370 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
371 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
373 // These macros are inserted to prevent GAS from complaining
374 // when using the AT register.
375 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
376 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
378 // When handling PIC code the assembler needs .cpload and .cprestore
379 // directives. If the real instructions corresponding these directives
380 // are used, we have the same behavior, but get also a bunch of warnings
381 // from the assembler.
382 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
383 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
385 //===----------------------------------------------------------------------===//
386 // Instruction definition
387 //===----------------------------------------------------------------------===//
389 //===----------------------------------------------------------------------===//
390 // MipsI Instructions
391 //===----------------------------------------------------------------------===//
393 /// Arithmetic Instructions (ALU Immediate)
394 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
395 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
396 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
397 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
398 def ANDi : LogicI<0x0c, "andi", and>;
399 def ORi : LogicI<0x0d, "ori", or>;
400 def XORi : LogicI<0x0e, "xori", xor>;
401 def LUi : LoadUpper<0x0f, "lui">;
403 /// Arithmetic Instructions (3-Operand, R-Type)
404 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu, 1>;
405 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
406 def ADD : ArithOverflowR<0x00, 0x20, "add", 1>;
407 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
408 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
409 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
410 def AND : LogicR<0x24, "and", and>;
411 def OR : LogicR<0x25, "or", or>;
412 def XOR : LogicR<0x26, "xor", xor>;
413 def NOR : LogicNOR<0x00, 0x27, "nor">;
415 /// Shift Instructions
416 def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
417 def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
418 def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
419 def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
420 def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
421 def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
423 // Rotate Instructions
424 let Predicates = [IsMips32r2] in {
425 def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
426 def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
429 /// Load and Store Instructions
430 def LB : LoadM<0x20, "lb", sextloadi8>;
431 def LBu : LoadM<0x24, "lbu", zextloadi8>;
432 def LH : LoadM<0x21, "lh", sextloadi16>;
433 def LHu : LoadM<0x25, "lhu", zextloadi16>;
434 def LW : LoadM<0x23, "lw", load>;
435 def SB : StoreM<0x28, "sb", truncstorei8>;
436 def SH : StoreM<0x29, "sh", truncstorei16>;
437 def SW : StoreM<0x2b, "sw", store>;
439 /// Jump and Branch Instructions
440 def J : JumpFJ<0x02, "j">;
441 def JR : JumpFR<0x00, 0x08, "jr">;
442 def JAL : JumpLink<0x03, "jal">;
443 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
444 def BEQ : CBranch<0x04, "beq", seteq>;
445 def BNE : CBranch<0x05, "bne", setne>;
448 def BGEZ : CBranchZero<0x01, "bgez", setge>;
451 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
452 def BLEZ : CBranchZero<0x07, "blez", setle>;
453 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
456 def BGEZAL : BranchLink<"bgezal">;
457 def BLTZAL : BranchLink<"bltzal">;
459 let isReturn=1, isTerminator=1, hasDelaySlot=1,
460 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
461 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
462 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
464 /// Multiply and Divide Instructions.
465 def MULT : Mul<0x18, "mult", IIImul>;
466 def MULTu : Mul<0x19, "multu", IIImul>;
467 def SDIV : Div<MipsDivRem, 0x1a, "div", IIIdiv>;
468 def UDIV : Div<MipsDivRemU, 0x1b, "divu", IIIdiv>;
471 def MTHI : MoveToLOHI<0x11, "mthi">;
473 def MTLO : MoveToLOHI<0x13, "mtlo">;
476 def MFHI : MoveFromLOHI<0x10, "mfhi">;
478 def MFLO : MoveFromLOHI<0x12, "mflo">;
480 /// Sign Ext In Register Instructions.
481 let Predicates = [HasSEInReg] in {
482 let shamt = 0x10, rs = 0 in
483 def SEB : SignExtInReg<0x21, "seb", i8>;
485 let shamt = 0x18, rs = 0 in
486 def SEH : SignExtInReg<0x20, "seh", i16>;
490 def CLZ : CountLeading<0b100000, "clz",
491 [(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
492 def CLO : CountLeading<0b100001, "clo",
493 [(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
496 let Predicates = [HasSwap] in {
497 let shamt = 0x3, rs = 0 in
498 def WSBW : ByteSwap<0x20, "wsbw">;
502 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
503 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
505 // Conditional moves:
506 // These instructions are expanded in
507 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
508 // conditional move instructions.
509 // flag:int, data:int
510 let usesCustomInserter = 1, shamt = 0, Constraints = "$F = $dst" in
511 class CondMovIntInt<bits<6> funct, string instr_asm> :
512 FR<0, funct, (outs CPURegs:$dst),
513 (ins CPURegs:$T, CPURegs:$cond, CPURegs:$F),
514 !strconcat(instr_asm, "\t$dst, $T, $cond"), [], NoItinerary>;
516 def MOVZ_I : CondMovIntInt<0x0a, "movz">;
517 def MOVN_I : CondMovIntInt<0x0b, "movn">;
521 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
523 // FrameIndexes are legalized when they are operands from load/store
524 // instructions. The same not happens for stack address copies, so an
525 // add op with mem ComplexPattern is used and the stack address copy
526 // can be matched. It's similar to Sparc LEA_ADDRi
527 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
530 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
531 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
532 def MSUB : MArithR<4, "msub", MipsMSub>;
533 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
535 // MUL is a assembly macro in the current used ISAs. In recent ISA's
536 // it is a real instruction.
537 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>;
539 //===----------------------------------------------------------------------===//
540 // Arbitrary patterns that map to one or more instructions
541 //===----------------------------------------------------------------------===//
544 def : Pat<(i32 immSExt16:$in),
545 (ADDiu ZERO, imm:$in)>;
546 def : Pat<(i32 immZExt16:$in),
547 (ORi ZERO, imm:$in)>;
549 // Arbitrary immediates
550 def : Pat<(i32 imm:$imm),
551 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
554 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
555 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
556 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
557 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
558 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
559 (ADDiu CPURegs:$src, imm:$imm)>;
562 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
563 (JAL tglobaladdr:$dst)>;
564 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
565 (JAL texternalsym:$dst)>;
566 //def : Pat<(MipsJmpLink CPURegs:$dst),
567 // (JALR CPURegs:$dst)>;
570 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
571 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
572 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
573 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
574 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
575 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
577 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
578 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
579 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
581 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
582 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
583 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
586 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
587 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
588 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
589 (ADDiu CPURegs:$gp, tconstpool:$in)>;
591 // Mips does not have "not", so we expand our way
592 def : Pat<(not CPURegs:$in),
593 (NOR CPURegs:$in, ZERO)>;
595 // extended load and stores
596 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
597 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
598 def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
601 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
604 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
605 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
606 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
607 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
609 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
610 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
611 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
612 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
613 def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
614 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
615 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
616 (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
618 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
619 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
620 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
621 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
623 def : Pat<(brcond CPURegs:$cond, bb:$dst),
624 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
627 multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
628 def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
629 (MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
630 def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
631 (MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
632 def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), RC:$T, RC:$F),
633 (MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
634 def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), RC:$T, RC:$F),
635 (MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
636 def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
637 (MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
638 def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
639 (MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
640 def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
641 (MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
642 def : Pat<(select (seteq CPURegs:$lhs, 0), RC:$T, RC:$F),
643 (MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
646 multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
647 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
648 (MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
649 def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
650 (MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
651 def : Pat<(select (setne CPURegs:$lhs, 0), RC:$T, RC:$F),
652 (MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
655 defm : MovzPats<CPURegs, MOVZ_I>;
656 defm : MovnPats<CPURegs, MOVN_I>;
658 // select patterns with got access
659 let AddedComplexity = 10 in
660 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs),
661 (i32 tglobaladdr:$T), CPURegs:$F),
662 (MOVN_I CPURegs:$F, (ADDiu GP, tglobaladdr:$T),
663 (XOR CPURegs:$lhs, CPURegs:$rhs))>;
666 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
667 (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
668 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
669 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
671 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
672 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
673 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
674 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
676 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
677 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
678 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
679 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
681 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
682 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
683 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
684 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
686 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
687 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
688 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
689 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
691 //===----------------------------------------------------------------------===//
692 // Floating Point Support
693 //===----------------------------------------------------------------------===//
695 include "MipsInstrFPU.td"