1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
186 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
187 let Predicates = [HasStdEnc];
191 bit isCommutable = 1;
208 bit isTerminator = 1;
211 bit hasExtraSrcRegAllocReq = 1;
212 bit isCodeGenOnly = 1;
215 class IsAsCheapAsAMove {
216 bit isAsCheapAsAMove = 1;
219 class NeverHasSideEffects {
220 bit neverHasSideEffects = 1;
223 //===----------------------------------------------------------------------===//
224 // Instruction format superclass
225 //===----------------------------------------------------------------------===//
227 include "MipsInstrFormats.td"
229 //===----------------------------------------------------------------------===//
230 // Mips Operand, Complex Patterns and Transformations Definitions.
231 //===----------------------------------------------------------------------===//
233 // Instruction operand types
234 def jmptarget : Operand<OtherVT> {
235 let EncoderMethod = "getJumpTargetOpValue";
237 def brtarget : Operand<OtherVT> {
238 let EncoderMethod = "getBranchTargetOpValue";
239 let OperandType = "OPERAND_PCREL";
240 let DecoderMethod = "DecodeBranchTarget";
242 def calltarget : Operand<iPTR> {
243 let EncoderMethod = "getJumpTargetOpValue";
245 def calltarget64: Operand<i64>;
246 def simm16 : Operand<i32> {
247 let DecoderMethod= "DecodeSimm16";
250 def simm20 : Operand<i32> {
253 def uimm20 : Operand<i32> {
256 def uimm10 : Operand<i32> {
259 def simm16_64 : Operand<i64>;
260 def shamt : Operand<i32>;
263 def uimm16 : Operand<i32> {
264 let PrintMethod = "printUnsignedImm";
267 def MipsMemAsmOperand : AsmOperandClass {
269 let ParserMethod = "parseMemOperand";
273 def mem : Operand<i32> {
274 let PrintMethod = "printMemOperand";
275 let MIOperandInfo = (ops CPURegs, simm16);
276 let EncoderMethod = "getMemEncoding";
277 let ParserMatchClass = MipsMemAsmOperand;
278 let OperandType = "OPERAND_MEMORY";
281 def mem64 : Operand<i64> {
282 let PrintMethod = "printMemOperand";
283 let MIOperandInfo = (ops CPU64Regs, simm16_64);
284 let EncoderMethod = "getMemEncoding";
285 let ParserMatchClass = MipsMemAsmOperand;
286 let OperandType = "OPERAND_MEMORY";
289 def mem_ea : Operand<i32> {
290 let PrintMethod = "printMemOperandEA";
291 let MIOperandInfo = (ops CPURegs, simm16);
292 let EncoderMethod = "getMemEncoding";
293 let OperandType = "OPERAND_MEMORY";
296 def mem_ea_64 : Operand<i64> {
297 let PrintMethod = "printMemOperandEA";
298 let MIOperandInfo = (ops CPU64Regs, simm16_64);
299 let EncoderMethod = "getMemEncoding";
300 let OperandType = "OPERAND_MEMORY";
303 // size operand of ext instruction
304 def size_ext : Operand<i32> {
305 let EncoderMethod = "getSizeExtEncoding";
306 let DecoderMethod = "DecodeExtSize";
309 // size operand of ins instruction
310 def size_ins : Operand<i32> {
311 let EncoderMethod = "getSizeInsEncoding";
312 let DecoderMethod = "DecodeInsSize";
315 // Transformation Function - get the lower 16 bits.
316 def LO16 : SDNodeXForm<imm, [{
317 return getImm(N, N->getZExtValue() & 0xFFFF);
320 // Transformation Function - get the higher 16 bits.
321 def HI16 : SDNodeXForm<imm, [{
322 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
326 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
328 // Node immediate fits as 16-bit sign extended on target immediate.
330 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
332 // Node immediate fits as 16-bit sign extended on target immediate.
334 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
336 // Node immediate fits as 15-bit sign extended on target immediate.
338 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
340 // Node immediate fits as 16-bit zero extended on target immediate.
341 // The LO16 param means that only the lower 16 bits of the node
342 // immediate are caught.
344 def immZExt16 : PatLeaf<(imm), [{
345 if (N->getValueType(0) == MVT::i32)
346 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
348 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
351 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
352 def immLow16Zero : PatLeaf<(imm), [{
353 int64_t Val = N->getSExtValue();
354 return isInt<32>(Val) && !(Val & 0xffff);
357 // shamt field must fit in 5 bits.
358 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
360 // True if (N + 1) fits in 16-bit field.
361 def immSExt16Plus1 : PatLeaf<(imm), [{
362 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
365 // Mips Address Mode! SDNode frameindex could possibily be a match
366 // since load and store instructions from stack used it.
368 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
371 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
374 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
376 //===----------------------------------------------------------------------===//
377 // Instructions specific format
378 //===----------------------------------------------------------------------===//
380 // Arithmetic and logical instructions with 3 register operands.
381 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
382 InstrItinClass Itin = NoItinerary,
383 SDPatternOperator OpNode = null_frag>:
384 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
385 !strconcat(opstr, "\t$rd, $rs, $rt"),
386 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
387 let isCommutable = isComm;
388 let isReMaterializable = 1;
391 // Arithmetic and logical instructions with 2 register operands.
392 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
393 InstrItinClass Itin = NoItinerary,
394 SDPatternOperator imm_type = null_frag,
395 SDPatternOperator OpNode = null_frag> :
396 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
397 !strconcat(opstr, "\t$rt, $rs, $imm16"),
398 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
400 let isReMaterializable = 1;
401 let TwoOperandAliasConstraint = "$rs = $rt";
404 // Arithmetic Multiply ADD/SUB
405 class MArithR<string opstr, bit isComm = 0> :
406 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
407 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
410 let isCommutable = isComm;
414 class LogicNOR<string opstr, RegisterOperand RO>:
415 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
416 !strconcat(opstr, "\t$rd, $rs, $rt"),
417 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
418 let isCommutable = 1;
422 class shift_rotate_imm<string opstr, Operand ImmOpnd,
423 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
424 SDPatternOperator PF = null_frag> :
425 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
426 !strconcat(opstr, "\t$rd, $rt, $shamt"),
427 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
429 class shift_rotate_reg<string opstr, RegisterOperand RO,
430 SDPatternOperator OpNode = null_frag>:
431 InstSE<(outs RO:$rd), (ins RO:$rt, CPURegsOpnd:$rs),
432 !strconcat(opstr, "\t$rd, $rt, $rs"),
433 [(set RO:$rd, (OpNode RO:$rt, CPURegsOpnd:$rs))], IIArith, FrmR, opstr>;
435 // Load Upper Imediate
436 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
437 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
438 [], IIArith, FrmI>, IsAsCheapAsAMove {
439 let neverHasSideEffects = 1;
440 let isReMaterializable = 1;
443 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
444 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
446 let Inst{25-21} = addr{20-16};
447 let Inst{15-0} = addr{15-0};
448 let DecoderMethod = "DecodeMem";
452 class Load<string opstr, SDPatternOperator OpNode, DAGOperand RO,
453 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
455 InstSE<(outs RO:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
456 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
457 !strconcat(opstr, ofsuffix)> {
458 let DecoderMethod = "DecodeMem";
459 let canFoldAsLoad = 1;
463 class Store<string opstr, SDPatternOperator OpNode, DAGOperand RO,
464 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
466 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
467 [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI,
468 !strconcat(opstr, ofsuffix)> {
469 let DecoderMethod = "DecodeMem";
473 multiclass LoadM<string opstr, DAGOperand RO,
474 SDPatternOperator OpNode = null_frag,
475 InstrItinClass Itin = NoItinerary,
476 ComplexPattern Addr = addr> {
477 def NAME : Load<opstr, OpNode, RO, Itin, mem, Addr, "">,
478 Requires<[NotN64, HasStdEnc]>;
479 def _P8 : Load<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">,
480 Requires<[IsN64, HasStdEnc]> {
481 let DecoderNamespace = "Mips64";
482 let isCodeGenOnly = 1;
486 multiclass StoreM<string opstr, DAGOperand RO,
487 SDPatternOperator OpNode = null_frag,
488 InstrItinClass Itin = NoItinerary,
489 ComplexPattern Addr = addr> {
490 def NAME : Store<opstr, OpNode, RO, Itin, mem, Addr, "">,
491 Requires<[NotN64, HasStdEnc]>;
492 def _P8 : Store<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">,
493 Requires<[IsN64, HasStdEnc]> {
494 let DecoderNamespace = "Mips64";
495 let isCodeGenOnly = 1;
499 // Load/Store Left/Right
500 let canFoldAsLoad = 1 in
501 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
503 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
504 !strconcat(opstr, "\t$rt, $addr"),
505 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
506 let DecoderMethod = "DecodeMem";
507 string Constraints = "$src = $rt";
510 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
512 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
513 [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
514 let DecoderMethod = "DecodeMem";
517 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterOperand RO> {
518 def NAME : LoadLeftRight<opstr, OpNode, RO, mem>,
519 Requires<[NotN64, HasStdEnc]>;
520 def _P8 : LoadLeftRight<opstr, OpNode, RO, mem64>,
521 Requires<[IsN64, HasStdEnc]> {
522 let DecoderNamespace = "Mips64";
523 let isCodeGenOnly = 1;
527 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterOperand RO> {
528 def NAME : StoreLeftRight<opstr, OpNode, RO, mem>,
529 Requires<[NotN64, HasStdEnc]>;
530 def _P8 : StoreLeftRight<opstr, OpNode, RO, mem64>,
531 Requires<[IsN64, HasStdEnc]> {
532 let DecoderNamespace = "Mips64";
533 let isCodeGenOnly = 1;
537 // Conditional Branch
538 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
539 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
540 !strconcat(opstr, "\t$rs, $rt, $offset"),
541 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
544 let isTerminator = 1;
545 let hasDelaySlot = 1;
549 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
550 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
551 !strconcat(opstr, "\t$rs, $offset"),
552 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
554 let isTerminator = 1;
555 let hasDelaySlot = 1;
560 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
561 InstSE<(outs CPURegsOpnd:$rd), (ins RO:$rs, RO:$rt),
562 !strconcat(opstr, "\t$rd, $rs, $rt"),
563 [(set CPURegsOpnd:$rd, (cond_op RO:$rs, RO:$rt))],
566 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
568 InstSE<(outs CPURegsOpnd:$rt), (ins RO:$rs, Od:$imm16),
569 !strconcat(opstr, "\t$rt, $rs, $imm16"),
570 [(set CPURegsOpnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
574 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
575 SDPatternOperator targetoperator> :
576 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
577 [(operator targetoperator:$target)], IIBranch, FrmJ> {
580 let hasDelaySlot = 1;
581 let DecoderMethod = "DecodeJumpTarget";
585 // Unconditional branch
586 class UncondBranch<string opstr> :
587 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
588 [(br bb:$offset)], IIBranch, FrmI> {
590 let isTerminator = 1;
592 let hasDelaySlot = 1;
593 let Predicates = [RelocPIC, HasStdEnc];
597 // Base class for indirect branch and return instruction classes.
598 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
599 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
600 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
603 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
605 let isIndirectBranch = 1;
608 // Return instruction
609 class RetBase<RegisterOperand RO>: JumpFR<RO> {
611 let isCodeGenOnly = 1;
613 let hasExtraSrcRegAllocReq = 1;
616 // Jump and Link (Call)
617 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
618 class JumpLink<string opstr> :
619 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
620 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
621 let DecoderMethod = "DecodeJumpTarget";
624 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
625 Register RetReg, RegisterOperand ResRO = RO>:
626 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
627 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
629 class JumpLinkReg<string opstr, RegisterOperand RO>:
630 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
633 class BGEZAL_FT<string opstr, RegisterOperand RO> :
634 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
635 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
639 class BAL_BR_Pseudo<Instruction RealInst> :
640 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
641 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
643 let isTerminator = 1;
645 let hasDelaySlot = 1;
650 class SYS_FT<string opstr> :
651 InstSE<(outs), (ins uimm20:$code_),
652 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
654 class BRK_FT<string opstr> :
655 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
656 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
659 class ER_FT<string opstr> :
660 InstSE<(outs), (ins),
661 opstr, [], NoItinerary, FrmOther>;
664 let hasSideEffects = 1 in
666 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
667 NoItinerary, FrmOther>;
669 let hasSideEffects = 1 in
670 class TEQ_FT<string opstr, RegisterOperand RO> :
671 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
672 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
675 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
676 list<Register> DefRegs> :
677 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
679 let isCommutable = 1;
681 let neverHasSideEffects = 1;
684 // Pseudo multiply/divide instruction with explicit accumulator register
686 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
687 SDPatternOperator OpNode, InstrItinClass Itin,
688 bit IsComm = 1, bit HasSideEffects = 0,
689 bit UsesCustomInserter = 0> :
690 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
691 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
692 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
693 let isCommutable = IsComm;
694 let hasSideEffects = HasSideEffects;
695 let usesCustomInserter = UsesCustomInserter;
698 // Pseudo multiply add/sub instruction with explicit accumulator register
700 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
701 : PseudoSE<(outs ACRegs:$ac),
702 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin),
704 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))],
706 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> {
707 string Constraints = "$acin = $ac";
710 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
711 list<Register> DefRegs> :
712 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
718 class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
719 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
721 let neverHasSideEffects = 1;
724 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
725 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
727 let neverHasSideEffects = 1;
730 class EffectiveAddress<string opstr, RegisterOperand RO, Operand Mem> :
731 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
732 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
733 let isCodeGenOnly = 1;
734 let DecoderMethod = "DecodeMem";
737 // Count Leading Ones/Zeros in Word
738 class CountLeading0<string opstr, RegisterOperand RO>:
739 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
740 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
741 Requires<[HasBitCount, HasStdEnc]>;
743 class CountLeading1<string opstr, RegisterOperand RO>:
744 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
745 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
746 Requires<[HasBitCount, HasStdEnc]>;
749 // Sign Extend in Register.
750 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
751 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
752 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> {
753 let Predicates = [HasSEInReg, HasStdEnc];
757 class SubwordSwap<string opstr, RegisterOperand RO>:
758 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
760 let Predicates = [HasSwap, HasStdEnc];
761 let neverHasSideEffects = 1;
765 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
766 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
770 class ExtBase<string opstr, RegisterOperand RO>:
771 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
772 !strconcat(opstr, " $rt, $rs, $pos, $size"),
773 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
775 let Predicates = [HasMips32r2, HasStdEnc];
778 class InsBase<string opstr, RegisterOperand RO>:
779 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
780 !strconcat(opstr, " $rt, $rs, $pos, $size"),
781 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
783 let Predicates = [HasMips32r2, HasStdEnc];
784 let Constraints = "$src = $rt";
787 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
788 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
789 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
790 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
792 multiclass Atomic2Ops32<PatFrag Op> {
793 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
794 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, Requires<[IsN64, HasStdEnc]>;
797 // Atomic Compare & Swap.
798 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
799 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
800 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
802 multiclass AtomicCmpSwap32<PatFrag Op> {
803 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
804 Requires<[NotN64, HasStdEnc]>;
805 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
806 Requires<[IsN64, HasStdEnc]>;
809 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
810 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
811 [], NoItinerary, FrmI> {
812 let DecoderMethod = "DecodeMem";
816 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
817 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
818 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
819 let DecoderMethod = "DecodeMem";
821 let Constraints = "$rt = $dst";
824 class MFC3OP<dag outs, dag ins, string asmstr> :
825 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
827 let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in
828 def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> {
829 let Inst = 0x0000000d;
832 //===----------------------------------------------------------------------===//
833 // Pseudo instructions
834 //===----------------------------------------------------------------------===//
837 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
838 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
840 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
841 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
842 [(callseq_start timm:$amt)]>;
843 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
844 [(callseq_end timm:$amt1, timm:$amt2)]>;
847 let usesCustomInserter = 1 in {
848 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
849 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
850 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
851 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
852 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
853 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
854 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
855 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
856 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
857 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
858 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
859 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
860 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
861 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
862 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
863 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
864 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
865 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
867 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
868 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
869 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
871 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
872 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
873 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
876 /// Pseudo instructions for loading and storing accumulator registers.
877 let isPseudo = 1, isCodeGenOnly = 1 in {
878 defm LOAD_AC64 : LoadM<"", ACRegs>;
879 defm STORE_AC64 : StoreM<"", ACRegs>;
882 //===----------------------------------------------------------------------===//
883 // Instruction definition
884 //===----------------------------------------------------------------------===//
885 //===----------------------------------------------------------------------===//
886 // MipsI Instructions
887 //===----------------------------------------------------------------------===//
889 /// Arithmetic Instructions (ALU Immediate)
890 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, IIArith, immSExt16,
892 ADDI_FM<0x9>, IsAsCheapAsAMove;
893 def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
894 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegsOpnd>,
896 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegsOpnd>,
898 def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, IILogic, immZExt16,
901 def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, IILogic, immZExt16,
904 def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, IILogic, immZExt16,
907 def LUi : MMRel, LoadUpper<"lui", CPURegsOpnd, uimm16>, LUI_FM;
909 /// Arithmetic Instructions (3-Operand, R-Type)
910 def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIArith, add>,
912 def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIArith, sub>,
914 def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
916 def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
917 def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
918 def SLT : MMRel, SetCC_R<"slt", setlt, CPURegsOpnd>, ADD_FM<0, 0x2a>;
919 def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegsOpnd>, ADD_FM<0, 0x2b>;
920 def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IILogic, and>,
922 def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IILogic, or>,
924 def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IILogic, xor>,
926 def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
928 /// Shift Instructions
929 def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
931 def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
933 def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
935 def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
936 def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
937 def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
939 // Rotate Instructions
940 let Predicates = [HasMips32r2, HasStdEnc] in {
941 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr,
944 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>,
948 /// Load and Store Instructions
950 defm LB : LoadM<"lb", CPURegsOpnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
951 defm LBu : LoadM<"lbu", CPURegsOpnd, zextloadi8, IILoad, addrDefault>, MMRel,
953 defm LH : LoadM<"lh", CPURegsOpnd, sextloadi16, IILoad, addrDefault>, MMRel,
955 defm LHu : LoadM<"lhu", CPURegsOpnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
956 defm LW : LoadM<"lw", CPURegsOpnd, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>;
957 defm SB : StoreM<"sb", CPURegsOpnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
958 defm SH : StoreM<"sh", CPURegsOpnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
959 defm SW : StoreM<"sw", CPURegsOpnd, store, IIStore>, MMRel, LW_FM<0x2b>;
961 /// load/store left/right
962 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegsOpnd>, LW_FM<0x22>;
963 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegsOpnd>, LW_FM<0x26>;
964 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegsOpnd>, LW_FM<0x2a>;
965 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegsOpnd>, LW_FM<0x2e>;
967 def SYNC : SYNC_FT, SYNC_FM;
968 def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>;
970 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
971 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
973 def ERET : ER_FT<"eret">, ER_FM<0x18>;
974 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
976 /// Load-linked, Store-conditional
977 let Predicates = [NotN64, HasStdEnc] in {
978 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
979 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>;
982 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
983 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>;
984 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>;
987 /// Jump and Branch Instructions
988 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
989 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
990 def JR : IndirectBranch<CPURegsOpnd>, MTLO_FM<8>;
991 def B : UncondBranch<"b">, B_FM;
992 def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>;
993 def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>;
994 def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>;
995 def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>;
996 def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>;
997 def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>;
999 def JAL : JumpLink<"jal">, FJ<3>;
1000 def JALR : JumpLinkReg<"jalr", CPURegsOpnd>, JALR_FM;
1001 def JALRPseudo : JumpLinkRegPseudo<CPURegsOpnd, JALR, RA>;
1002 def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
1003 def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
1004 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1005 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
1006 def TAILCALL_R : JumpFR<CPURegsOpnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
1008 def RET : RetBase<CPURegsOpnd>, MTLO_FM<8>;
1010 // Exception handling related node and instructions.
1011 // The conversion sequence is:
1012 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1013 // MIPSeh_return -> (stack change + indirect branch)
1015 // MIPSeh_return takes the place of regular return instruction
1016 // but takes two arguments (V1, V0) which are used for storing
1017 // the offset and return address respectively.
1018 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1020 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1021 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1023 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1024 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst),
1025 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>;
1026 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff,
1028 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>;
1031 /// Multiply and Divide Instructions.
1032 def MULT : MMRel, Mult<"mult", IIImult, CPURegsOpnd, [HI, LO]>,
1034 def MULTu : MMRel, Mult<"multu", IIImult, CPURegsOpnd, [HI, LO]>,
1036 def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImult>;
1037 def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImult>;
1038 def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
1039 def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>;
1040 def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv,
1042 def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv,
1045 def MTHI : MoveToLOHI<"mthi", CPURegsOpnd, [HI]>, MTLO_FM<0x11>;
1046 def MTLO : MoveToLOHI<"mtlo", CPURegsOpnd, [LO]>, MTLO_FM<0x13>;
1047 def MFHI : MoveFromLOHI<"mfhi", CPURegsOpnd, [HI]>, MFLO_FM<0x10>;
1048 def MFLO : MoveFromLOHI<"mflo", CPURegsOpnd, [LO]>, MFLO_FM<0x12>;
1050 /// Sign Ext In Register Instructions.
1051 def SEB : SignExtInReg<"seb", i8, CPURegsOpnd>, SEB_FM<0x10, 0x20>;
1052 def SEH : SignExtInReg<"seh", i16, CPURegsOpnd>, SEB_FM<0x18, 0x20>;
1055 def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
1056 def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>;
1058 /// Word Swap Bytes Within Halfwords
1059 def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>;
1062 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1064 // FrameIndexes are legalized when they are operands from load/store
1065 // instructions. The same not happens for stack address copies, so an
1066 // add op with mem ComplexPattern is used and the stack address copy
1067 // can be matched. It's similar to Sparc LEA_ADDRi
1068 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegsOpnd, mem_ea>, LW_FM<9>;
1071 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1072 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1073 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1074 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1075 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1076 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1077 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1078 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1080 def RDHWR : ReadHardware<CPURegsOpnd, HWRegsOpnd>, RDHWR_FM;
1082 def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
1083 def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
1085 /// Move Control Registers From/To CPU Registers
1086 def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1087 (ins CPURegsOpnd:$rd, uimm16:$sel),
1088 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
1090 def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1091 (ins CPURegsOpnd:$rt),
1092 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
1094 def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1095 (ins CPURegsOpnd:$rd, uimm16:$sel),
1096 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
1098 def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1099 (ins CPURegsOpnd:$rt),
1100 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
1102 //===----------------------------------------------------------------------===//
1103 // Instruction aliases
1104 //===----------------------------------------------------------------------===//
1105 def : InstAlias<"move $dst, $src",
1106 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1107 Requires<[NotMips64]>;
1108 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 1>;
1109 def : InstAlias<"addu $rs, $rt, $imm",
1110 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1111 def : InstAlias<"add $rs, $rt, $imm",
1112 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1113 def : InstAlias<"and $rs, $rt, $imm",
1114 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1115 def : InstAlias<"j $rs", (JR CPURegsOpnd:$rs), 0>,
1116 Requires<[NotMips64]>;
1117 def : InstAlias<"jalr $rs", (JALR RA, CPURegsOpnd:$rs), 0>;
1118 def : InstAlias<"jal $rs", (JALR RA, CPURegsOpnd:$rs), 0>;
1119 def : InstAlias<"jal $rd,$rs", (JALR CPURegsOpnd:$rd, CPURegsOpnd:$rs), 0>;
1120 def : InstAlias<"not $rt, $rs",
1121 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
1122 def : InstAlias<"neg $rt, $rs",
1123 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1124 def : InstAlias<"negu $rt, $rs",
1125 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1126 def : InstAlias<"slt $rs, $rt, $imm",
1127 (SLTi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1128 def : InstAlias<"xor $rs, $rt, $imm",
1129 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1130 Requires<[NotMips64]>;
1131 def : InstAlias<"or $rs, $rt, $imm",
1132 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1133 Requires<[NotMips64]>;
1134 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1135 def : InstAlias<"mfc0 $rt, $rd",
1136 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1137 def : InstAlias<"mtc0 $rt, $rd",
1138 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1139 def : InstAlias<"mfc2 $rt, $rd",
1140 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1141 def : InstAlias<"mtc2 $rt, $rd",
1142 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1143 def : InstAlias<"bnez $rs,$offset",
1144 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1145 Requires<[NotMips64]>;
1146 def : InstAlias<"beqz $rs,$offset",
1147 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1148 Requires<[NotMips64]>;
1149 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1151 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1152 def : InstAlias<"break", (BREAK 0, 0), 1>;
1153 //===----------------------------------------------------------------------===//
1154 // Assembler Pseudo Instructions
1155 //===----------------------------------------------------------------------===//
1157 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1158 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1159 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1160 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>;
1162 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1163 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1164 !strconcat(instr_asm, "\t$rt, $addr")> ;
1165 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>;
1167 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1168 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1169 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1170 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>;
1174 //===----------------------------------------------------------------------===//
1175 // Arbitrary patterns that map to one or more instructions
1176 //===----------------------------------------------------------------------===//
1178 // Load/store pattern templates.
1179 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1180 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1182 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1183 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1186 def : MipsPat<(i32 immSExt16:$in),
1187 (ADDiu ZERO, imm:$in)>;
1188 def : MipsPat<(i32 immZExt16:$in),
1189 (ORi ZERO, imm:$in)>;
1190 def : MipsPat<(i32 immLow16Zero:$in),
1191 (LUi (HI16 imm:$in))>;
1193 // Arbitrary immediates
1194 def : MipsPat<(i32 imm:$imm),
1195 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1197 // Carry MipsPatterns
1198 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1199 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1200 let Predicates = [HasStdEnc, NotDSP] in {
1201 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1202 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1203 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1204 (ADDiu CPURegs:$src, imm:$imm)>;
1208 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1209 (JAL tglobaladdr:$dst)>;
1210 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1211 (JAL texternalsym:$dst)>;
1212 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1213 // (JALR CPURegs:$dst)>;
1216 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1217 (TAILCALL tglobaladdr:$dst)>;
1218 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1219 (TAILCALL texternalsym:$dst)>;
1221 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1222 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1223 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1224 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1225 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1226 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1228 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1229 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1230 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1231 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1232 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1233 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1235 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1236 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1237 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1238 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1239 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1240 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1241 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1242 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1243 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1244 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1247 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1248 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1249 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1250 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1253 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1254 MipsPat<(MipsWrapper RC:$gp, node:$in),
1255 (ADDiuOp RC:$gp, node:$in)>;
1257 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1258 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1259 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1260 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1261 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1262 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1264 // Mips does not have "not", so we expand our way
1265 def : MipsPat<(not CPURegs:$in),
1266 (NOR CPURegsOpnd:$in, ZERO)>;
1269 let Predicates = [NotN64, HasStdEnc] in {
1270 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1271 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1272 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1274 let Predicates = [IsN64, HasStdEnc] in {
1275 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1276 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1277 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1281 let Predicates = [NotN64, HasStdEnc] in {
1282 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1284 let Predicates = [IsN64, HasStdEnc] in {
1285 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1289 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1290 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1291 Instruction SLTiuOp, Register ZEROReg> {
1292 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1293 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1294 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1295 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1297 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1298 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1299 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1300 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1301 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1302 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1303 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1304 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1305 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1306 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1307 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1308 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1310 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1311 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1312 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1313 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1315 def : MipsPat<(brcond RC:$cond, bb:$dst),
1316 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1319 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1321 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1322 (BLEZ i32:$lhs, bb:$dst)>;
1323 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1324 (BGEZ i32:$lhs, bb:$dst)>;
1327 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1328 Instruction SLTuOp, Register ZEROReg> {
1329 def : MipsPat<(seteq RC:$lhs, 0),
1330 (SLTiuOp RC:$lhs, 1)>;
1331 def : MipsPat<(setne RC:$lhs, 0),
1332 (SLTuOp ZEROReg, RC:$lhs)>;
1333 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1334 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1335 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1336 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1339 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1340 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1341 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1342 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1343 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1346 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1347 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1348 (SLTOp RC:$rhs, RC:$lhs)>;
1349 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1350 (SLTuOp RC:$rhs, RC:$lhs)>;
1353 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1354 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1355 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1356 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1357 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1360 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1361 Instruction SLTiuOp> {
1362 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1363 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1364 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1365 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1368 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1369 defm : SetlePats<CPURegs, SLT, SLTu>;
1370 defm : SetgtPats<CPURegs, SLT, SLTu>;
1371 defm : SetgePats<CPURegs, SLT, SLTu>;
1372 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1375 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1377 // mflo/hi patterns.
1378 def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
1379 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
1381 // Load halfword/word patterns.
1382 let AddedComplexity = 40 in {
1383 let Predicates = [NotN64, HasStdEnc] in {
1384 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1385 def : LoadRegImmPat<LH, i32, sextloadi16>;
1386 def : LoadRegImmPat<LW, i32, load>;
1388 let Predicates = [IsN64, HasStdEnc] in {
1389 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>;
1390 def : LoadRegImmPat<LH_P8, i32, sextloadi16>;
1391 def : LoadRegImmPat<LW_P8, i32, load>;
1395 //===----------------------------------------------------------------------===//
1396 // Floating Point Support
1397 //===----------------------------------------------------------------------===//
1399 include "MipsInstrFPU.td"
1400 include "Mips64InstrInfo.td"
1401 include "MipsCondMov.td"
1406 include "Mips16InstrFormats.td"
1407 include "Mips16InstrInfo.td"
1410 include "MipsDSPInstrFormats.td"
1411 include "MipsDSPInstrInfo.td"
1414 include "MicroMipsInstrFormats.td"
1415 include "MicroMipsInstrInfo.td"