1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
185 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
186 AssemblerPredicate<"FeatureMicroMips">;
187 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
188 AssemblerPredicate<"!FeatureMicroMips">;
189 def IsLE : Predicate<"Subtarget.isLittle()">;
190 def IsBE : Predicate<"!Subtarget.isLittle()">;
192 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
193 let Predicates = [HasStdEnc];
197 bit isCommutable = 1;
214 bit isTerminator = 1;
217 bit hasExtraSrcRegAllocReq = 1;
218 bit isCodeGenOnly = 1;
221 class IsAsCheapAsAMove {
222 bit isAsCheapAsAMove = 1;
225 class NeverHasSideEffects {
226 bit neverHasSideEffects = 1;
229 //===----------------------------------------------------------------------===//
230 // Instruction format superclass
231 //===----------------------------------------------------------------------===//
233 include "MipsInstrFormats.td"
235 //===----------------------------------------------------------------------===//
236 // Mips Operand, Complex Patterns and Transformations Definitions.
237 //===----------------------------------------------------------------------===//
239 // Instruction operand types
240 def jmptarget : Operand<OtherVT> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def brtarget : Operand<OtherVT> {
244 let EncoderMethod = "getBranchTargetOpValue";
245 let OperandType = "OPERAND_PCREL";
246 let DecoderMethod = "DecodeBranchTarget";
248 def calltarget : Operand<iPTR> {
249 let EncoderMethod = "getJumpTargetOpValue";
251 def calltarget64: Operand<i64>;
252 def simm16 : Operand<i32> {
253 let DecoderMethod= "DecodeSimm16";
256 def simm20 : Operand<i32> {
259 def uimm20 : Operand<i32> {
262 def uimm10 : Operand<i32> {
265 def simm16_64 : Operand<i64>;
266 def shamt : Operand<i32>;
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm16 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def MipsMemAsmOperand : AsmOperandClass {
279 let ParserMethod = "parseMemOperand";
282 def PtrRegAsmOperand : AsmOperandClass {
284 let ParserMethod = "parsePtrReg";
288 def mem : Operand<iPTR> {
289 let PrintMethod = "printMemOperand";
290 let MIOperandInfo = (ops ptr_rc, simm16);
291 let EncoderMethod = "getMemEncoding";
292 let ParserMatchClass = MipsMemAsmOperand;
293 let OperandType = "OPERAND_MEMORY";
296 def mem_ea : Operand<iPTR> {
297 let PrintMethod = "printMemOperandEA";
298 let MIOperandInfo = (ops ptr_rc, simm16);
299 let EncoderMethod = "getMemEncoding";
300 let OperandType = "OPERAND_MEMORY";
303 def PtrRC : Operand<iPTR> {
304 let MIOperandInfo = (ops ptr_rc);
305 let DecoderMethod = "DecodePtrRegisterClass";
306 let ParserMatchClass = PtrRegAsmOperand;
309 // size operand of ext instruction
310 def size_ext : Operand<i32> {
311 let EncoderMethod = "getSizeExtEncoding";
312 let DecoderMethod = "DecodeExtSize";
315 // size operand of ins instruction
316 def size_ins : Operand<i32> {
317 let EncoderMethod = "getSizeInsEncoding";
318 let DecoderMethod = "DecodeInsSize";
321 // Transformation Function - get the lower 16 bits.
322 def LO16 : SDNodeXForm<imm, [{
323 return getImm(N, N->getZExtValue() & 0xFFFF);
326 // Transformation Function - get the higher 16 bits.
327 def HI16 : SDNodeXForm<imm, [{
328 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
332 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
334 // Node immediate fits as 16-bit sign extended on target immediate.
336 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
338 // Node immediate fits as 16-bit sign extended on target immediate.
340 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
342 // Node immediate fits as 15-bit sign extended on target immediate.
344 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
346 // Node immediate fits as 16-bit zero extended on target immediate.
347 // The LO16 param means that only the lower 16 bits of the node
348 // immediate are caught.
350 def immZExt16 : PatLeaf<(imm), [{
351 if (N->getValueType(0) == MVT::i32)
352 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
354 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
357 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
358 def immLow16Zero : PatLeaf<(imm), [{
359 int64_t Val = N->getSExtValue();
360 return isInt<32>(Val) && !(Val & 0xffff);
363 // shamt field must fit in 5 bits.
364 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
366 // True if (N + 1) fits in 16-bit field.
367 def immSExt16Plus1 : PatLeaf<(imm), [{
368 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
371 // Mips Address Mode! SDNode frameindex could possibily be a match
372 // since load and store instructions from stack used it.
374 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
377 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
380 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
383 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
385 //===----------------------------------------------------------------------===//
386 // Instructions specific format
387 //===----------------------------------------------------------------------===//
389 // Arithmetic and logical instructions with 3 register operands.
390 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
391 InstrItinClass Itin = NoItinerary,
392 SDPatternOperator OpNode = null_frag>:
393 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
394 !strconcat(opstr, "\t$rd, $rs, $rt"),
395 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
396 let isCommutable = isComm;
397 let isReMaterializable = 1;
400 // Arithmetic and logical instructions with 2 register operands.
401 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
402 InstrItinClass Itin = NoItinerary,
403 SDPatternOperator imm_type = null_frag,
404 SDPatternOperator OpNode = null_frag> :
405 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
406 !strconcat(opstr, "\t$rt, $rs, $imm16"),
407 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
409 let isReMaterializable = 1;
410 let TwoOperandAliasConstraint = "$rs = $rt";
413 // Arithmetic Multiply ADD/SUB
414 class MArithR<string opstr, bit isComm = 0> :
415 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
416 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
417 let Defs = [HI0, LO0];
418 let Uses = [HI0, LO0];
419 let isCommutable = isComm;
423 class LogicNOR<string opstr, RegisterOperand RO>:
424 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
425 !strconcat(opstr, "\t$rd, $rs, $rt"),
426 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
427 let isCommutable = 1;
431 class shift_rotate_imm<string opstr, Operand ImmOpnd,
432 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
433 SDPatternOperator PF = null_frag> :
434 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
435 !strconcat(opstr, "\t$rd, $rt, $shamt"),
436 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
438 class shift_rotate_reg<string opstr, RegisterOperand RO,
439 SDPatternOperator OpNode = null_frag>:
440 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
441 !strconcat(opstr, "\t$rd, $rt, $rs"),
442 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
444 // Load Upper Imediate
445 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
446 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
447 [], IIArith, FrmI>, IsAsCheapAsAMove {
448 let neverHasSideEffects = 1;
449 let isReMaterializable = 1;
452 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
453 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
455 let Inst{25-21} = addr{20-16};
456 let Inst{15-0} = addr{15-0};
457 let DecoderMethod = "DecodeMem";
461 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
462 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
463 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
464 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, opstr> {
465 let DecoderMethod = "DecodeMem";
466 let canFoldAsLoad = 1;
470 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
471 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
472 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
473 [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI, opstr> {
474 let DecoderMethod = "DecodeMem";
478 // Load/Store Left/Right
479 let canFoldAsLoad = 1 in
480 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
481 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
482 !strconcat(opstr, "\t$rt, $addr"),
483 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
484 let DecoderMethod = "DecodeMem";
485 string Constraints = "$src = $rt";
488 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
489 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
490 [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
491 let DecoderMethod = "DecodeMem";
494 // Conditional Branch
495 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
496 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
497 !strconcat(opstr, "\t$rs, $rt, $offset"),
498 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
501 let isTerminator = 1;
502 let hasDelaySlot = 1;
506 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
507 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
508 !strconcat(opstr, "\t$rs, $offset"),
509 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
511 let isTerminator = 1;
512 let hasDelaySlot = 1;
517 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
518 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
519 !strconcat(opstr, "\t$rd, $rs, $rt"),
520 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
523 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
525 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
526 !strconcat(opstr, "\t$rt, $rs, $imm16"),
527 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
531 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
532 SDPatternOperator targetoperator> :
533 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
534 [(operator targetoperator:$target)], IIBranch, FrmJ> {
537 let hasDelaySlot = 1;
538 let DecoderMethod = "DecodeJumpTarget";
542 // Unconditional branch
543 class UncondBranch<string opstr> :
544 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
545 [(br bb:$offset)], IIBranch, FrmI> {
547 let isTerminator = 1;
549 let hasDelaySlot = 1;
550 let Predicates = [RelocPIC, HasStdEnc];
554 // Base class for indirect branch and return instruction classes.
555 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
556 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
557 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
560 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
562 let isIndirectBranch = 1;
565 // Return instruction
566 class RetBase<RegisterOperand RO>: JumpFR<RO> {
568 let isCodeGenOnly = 1;
570 let hasExtraSrcRegAllocReq = 1;
573 // Jump and Link (Call)
574 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
575 class JumpLink<string opstr> :
576 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
577 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
578 let DecoderMethod = "DecodeJumpTarget";
581 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
582 Register RetReg, RegisterOperand ResRO = RO>:
583 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
584 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
586 class JumpLinkReg<string opstr, RegisterOperand RO>:
587 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
590 class BGEZAL_FT<string opstr, RegisterOperand RO> :
591 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
592 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
596 class BAL_BR_Pseudo<Instruction RealInst> :
597 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
598 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
600 let isTerminator = 1;
602 let hasDelaySlot = 1;
607 class SYS_FT<string opstr> :
608 InstSE<(outs), (ins uimm20:$code_),
609 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
611 class BRK_FT<string opstr> :
612 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
613 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
616 class ER_FT<string opstr> :
617 InstSE<(outs), (ins),
618 opstr, [], NoItinerary, FrmOther>;
621 class DEI_FT<string opstr, RegisterOperand RO> :
622 InstSE<(outs RO:$rt), (ins),
623 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
626 class WAIT_FT<string opstr> :
627 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
628 let Inst{31-26} = 0x10;
631 let Inst{5-0} = 0x20;
635 let hasSideEffects = 1 in
637 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
638 NoItinerary, FrmOther>;
640 let hasSideEffects = 1 in
641 class TEQ_FT<string opstr, RegisterOperand RO> :
642 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
643 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
645 class TEQI_FT<string opstr, RegisterOperand RO> :
646 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
647 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
649 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
650 list<Register> DefRegs> :
651 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
653 let isCommutable = 1;
655 let neverHasSideEffects = 1;
658 // Pseudo multiply/divide instruction with explicit accumulator register
660 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
661 SDPatternOperator OpNode, InstrItinClass Itin,
662 bit IsComm = 1, bit HasSideEffects = 0,
663 bit UsesCustomInserter = 0> :
664 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
665 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
666 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
667 let isCommutable = IsComm;
668 let hasSideEffects = HasSideEffects;
669 let usesCustomInserter = UsesCustomInserter;
672 // Pseudo multiply add/sub instruction with explicit accumulator register
674 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
675 : PseudoSE<(outs ACC64:$ac),
676 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
678 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
680 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
681 string Constraints = "$acin = $ac";
684 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
685 list<Register> DefRegs> :
686 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
692 class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
693 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo,
696 let neverHasSideEffects = 1;
699 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
700 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
703 let neverHasSideEffects = 1;
706 class EffectiveAddress<string opstr, RegisterOperand RO> :
707 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
708 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
709 let isCodeGenOnly = 1;
710 let DecoderMethod = "DecodeMem";
713 // Count Leading Ones/Zeros in Word
714 class CountLeading0<string opstr, RegisterOperand RO>:
715 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
716 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
717 Requires<[HasBitCount, HasStdEnc]>;
719 class CountLeading1<string opstr, RegisterOperand RO>:
720 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
721 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
722 Requires<[HasBitCount, HasStdEnc]>;
725 // Sign Extend in Register.
726 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
727 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
728 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> {
729 let Predicates = [HasSEInReg, HasStdEnc];
733 class SubwordSwap<string opstr, RegisterOperand RO>:
734 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
736 let Predicates = [HasSwap, HasStdEnc];
737 let neverHasSideEffects = 1;
741 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
742 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
746 class ExtBase<string opstr, RegisterOperand RO>:
747 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
748 !strconcat(opstr, " $rt, $rs, $pos, $size"),
749 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
751 let Predicates = [HasMips32r2, HasStdEnc];
754 class InsBase<string opstr, RegisterOperand RO>:
755 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
756 !strconcat(opstr, " $rt, $rs, $pos, $size"),
757 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
759 let Predicates = [HasMips32r2, HasStdEnc];
760 let Constraints = "$src = $rt";
763 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
764 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
765 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
766 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
768 // Atomic Compare & Swap.
769 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
770 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
771 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
773 class LLBase<string opstr, RegisterOperand RO> :
774 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
775 [], NoItinerary, FrmI> {
776 let DecoderMethod = "DecodeMem";
780 class SCBase<string opstr, RegisterOperand RO> :
781 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
782 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
783 let DecoderMethod = "DecodeMem";
785 let Constraints = "$rt = $dst";
788 class MFC3OP<string asmstr, RegisterOperand RO> :
789 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
790 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
792 let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in
793 def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> {
794 let Inst = 0x0000000d;
797 //===----------------------------------------------------------------------===//
798 // Pseudo instructions
799 //===----------------------------------------------------------------------===//
802 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
803 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
805 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
806 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
807 [(callseq_start timm:$amt)]>;
808 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
809 [(callseq_end timm:$amt1, timm:$amt2)]>;
812 let usesCustomInserter = 1 in {
813 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
814 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
815 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
816 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
817 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
818 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
819 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
820 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
821 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
822 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
823 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
824 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
825 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
826 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
827 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
828 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
829 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
830 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
832 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
833 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
834 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
836 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
837 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
838 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
841 /// Pseudo instructions for loading and storing accumulator registers.
842 let isPseudo = 1, isCodeGenOnly = 1 in {
843 def LOAD_ACC64 : Load<"", ACC64>;
844 def STORE_ACC64 : Store<"", ACC64>;
847 //===----------------------------------------------------------------------===//
848 // Instruction definition
849 //===----------------------------------------------------------------------===//
850 //===----------------------------------------------------------------------===//
851 // MipsI Instructions
852 //===----------------------------------------------------------------------===//
854 /// Arithmetic Instructions (ALU Immediate)
855 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
857 ADDI_FM<0x9>, IsAsCheapAsAMove;
858 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
859 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
861 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
863 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
866 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
869 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
872 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
874 /// Arithmetic Instructions (3-Operand, R-Type)
875 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
877 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
879 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
881 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
882 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
883 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
884 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
885 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
887 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
889 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
891 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
893 /// Shift Instructions
894 def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>,
896 def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>,
898 def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>,
900 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
901 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
902 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
904 // Rotate Instructions
905 let Predicates = [HasMips32r2, HasStdEnc] in {
906 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr,
909 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
913 /// Load and Store Instructions
915 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
916 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
918 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
920 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
921 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
923 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
924 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
925 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
927 /// load/store left/right
928 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>;
929 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>;
930 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>;
931 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
933 def SYNC : SYNC_FT, SYNC_FM;
934 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
935 def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
936 def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
937 def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
938 def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
939 def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
941 def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
942 def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
943 def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
944 def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
945 def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
946 def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
948 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
949 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
951 def ERET : ER_FT<"eret">, ER_FM<0x18>;
952 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
954 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
955 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
957 def WAIT : WAIT_FT<"wait">;
959 /// Load-linked, Store-conditional
960 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
961 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
963 /// Jump and Branch Instructions
964 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
965 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
966 def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>;
967 def B : UncondBranch<"b">, B_FM;
968 def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
969 def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
970 def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
971 def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
972 def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
973 def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
975 def JAL : JumpLink<"jal">, FJ<3>;
976 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
977 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
978 def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
979 def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
980 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
981 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
982 def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
984 def RET : RetBase<GPR32Opnd>, MTLO_FM<8>;
986 // Exception handling related node and instructions.
987 // The conversion sequence is:
988 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
989 // MIPSeh_return -> (stack change + indirect branch)
991 // MIPSeh_return takes the place of regular return instruction
992 // but takes two arguments (V1, V0) which are used for storing
993 // the offset and return address respectively.
994 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
996 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
997 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
999 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1000 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1001 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1002 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1004 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1007 /// Multiply and Divide Instructions.
1008 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1010 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1012 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1013 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1014 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
1015 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
1016 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1018 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1021 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1022 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1023 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>;
1024 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>;
1026 /// Sign Ext In Register Instructions.
1027 def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1028 def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1031 def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1032 def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1034 /// Word Swap Bytes Within Halfwords
1035 def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1038 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1040 // FrameIndexes are legalized when they are operands from load/store
1041 // instructions. The same not happens for stack address copies, so an
1042 // add op with mem ComplexPattern is used and the stack address copy
1043 // can be matched. It's similar to Sparc LEA_ADDRi
1044 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1047 def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1048 def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1049 def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1050 def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1051 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1052 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1053 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1054 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1056 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1058 def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>;
1059 def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>;
1061 /// Move Control Registers From/To CPU Registers
1062 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1063 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1064 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1065 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1067 //===----------------------------------------------------------------------===//
1068 // Instruction aliases
1069 //===----------------------------------------------------------------------===//
1070 def : InstAlias<"move $dst, $src",
1071 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1072 Requires<[NotMips64]>;
1073 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1074 def : InstAlias<"addu $rs, $rt, $imm",
1075 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1076 def : InstAlias<"add $rs, $rt, $imm",
1077 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1078 def : InstAlias<"and $rs, $rt, $imm",
1079 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1080 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1081 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1082 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1083 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1084 def : InstAlias<"not $rt, $rs",
1085 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1086 def : InstAlias<"neg $rt, $rs",
1087 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1088 def : InstAlias<"negu $rt, $rs",
1089 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1090 def : InstAlias<"slt $rs, $rt, $imm",
1091 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1092 def : InstAlias<"xor $rs, $rt, $imm",
1093 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1094 def : InstAlias<"or $rs, $rt, $imm",
1095 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1096 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1097 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1098 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1099 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1100 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1101 def : InstAlias<"bnez $rs,$offset",
1102 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1103 def : InstAlias<"beqz $rs,$offset",
1104 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1105 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1107 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1108 def : InstAlias<"break", (BREAK 0, 0), 1>;
1109 def : InstAlias<"ei", (EI ZERO), 1>;
1110 def : InstAlias<"di", (DI ZERO), 1>;
1112 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1113 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1114 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1115 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1116 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1117 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1118 //===----------------------------------------------------------------------===//
1119 // Assembler Pseudo Instructions
1120 //===----------------------------------------------------------------------===//
1122 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1123 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1124 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1125 def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>;
1127 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1128 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1129 !strconcat(instr_asm, "\t$rt, $addr")> ;
1130 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1132 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1133 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1134 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1135 def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>;
1139 //===----------------------------------------------------------------------===//
1140 // Arbitrary patterns that map to one or more instructions
1141 //===----------------------------------------------------------------------===//
1143 // Load/store pattern templates.
1144 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1145 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1147 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1148 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1151 def : MipsPat<(i32 immSExt16:$in),
1152 (ADDiu ZERO, imm:$in)>;
1153 def : MipsPat<(i32 immZExt16:$in),
1154 (ORi ZERO, imm:$in)>;
1155 def : MipsPat<(i32 immLow16Zero:$in),
1156 (LUi (HI16 imm:$in))>;
1158 // Arbitrary immediates
1159 def : MipsPat<(i32 imm:$imm),
1160 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1162 // Carry MipsPatterns
1163 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1164 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1165 let Predicates = [HasStdEnc, NotDSP] in {
1166 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1167 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1168 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1169 (ADDiu GPR32:$src, imm:$imm)>;
1173 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1174 (JAL tglobaladdr:$dst)>;
1175 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1176 (JAL texternalsym:$dst)>;
1177 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1178 // (JALR GPR32:$dst)>;
1181 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1182 (TAILCALL tglobaladdr:$dst)>;
1183 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1184 (TAILCALL texternalsym:$dst)>;
1186 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1187 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1188 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1189 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1190 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1191 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1193 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1194 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1195 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1196 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1197 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1198 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1200 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1201 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1202 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1203 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1204 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1205 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1206 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1207 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1208 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1209 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1212 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1213 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1214 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1215 (ADDiu GPR32:$gp, tconstpool:$in)>;
1218 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1219 MipsPat<(MipsWrapper RC:$gp, node:$in),
1220 (ADDiuOp RC:$gp, node:$in)>;
1222 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1223 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1224 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1225 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1226 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1227 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1229 // Mips does not have "not", so we expand our way
1230 def : MipsPat<(not GPR32:$in),
1231 (NOR GPR32Opnd:$in, ZERO)>;
1234 let Predicates = [HasStdEnc] in {
1235 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1236 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1237 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1241 let Predicates = [HasStdEnc] in
1242 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1245 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1246 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1247 Instruction SLTiuOp, Register ZEROReg> {
1248 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1249 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1250 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1251 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1253 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1254 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1255 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1256 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1257 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1258 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1259 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1260 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1261 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1262 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1263 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1264 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1266 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1267 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1268 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1269 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1271 def : MipsPat<(brcond RC:$cond, bb:$dst),
1272 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1275 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1277 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1278 (BLEZ i32:$lhs, bb:$dst)>;
1279 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1280 (BGEZ i32:$lhs, bb:$dst)>;
1283 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1284 Instruction SLTuOp, Register ZEROReg> {
1285 def : MipsPat<(seteq RC:$lhs, 0),
1286 (SLTiuOp RC:$lhs, 1)>;
1287 def : MipsPat<(setne RC:$lhs, 0),
1288 (SLTuOp ZEROReg, RC:$lhs)>;
1289 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1290 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1291 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1292 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1295 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1296 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1297 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1298 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1299 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1302 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1303 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1304 (SLTOp RC:$rhs, RC:$lhs)>;
1305 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1306 (SLTuOp RC:$rhs, RC:$lhs)>;
1309 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1310 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1311 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1312 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1313 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1316 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1317 Instruction SLTiuOp> {
1318 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1319 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1320 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1321 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1324 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1325 defm : SetlePats<GPR32, SLT, SLTu>;
1326 defm : SetgtPats<GPR32, SLT, SLTu>;
1327 defm : SetgePats<GPR32, SLT, SLTu>;
1328 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1331 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1333 // mflo/hi patterns.
1334 def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)),
1335 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>;
1337 // Load halfword/word patterns.
1338 let AddedComplexity = 40 in {
1339 let Predicates = [HasStdEnc] in {
1340 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1341 def : LoadRegImmPat<LH, i32, sextloadi16>;
1342 def : LoadRegImmPat<LW, i32, load>;
1346 //===----------------------------------------------------------------------===//
1347 // Floating Point Support
1348 //===----------------------------------------------------------------------===//
1350 include "MipsInstrFPU.td"
1351 include "Mips64InstrInfo.td"
1352 include "MipsCondMov.td"
1357 include "Mips16InstrFormats.td"
1358 include "Mips16InstrInfo.td"
1361 include "MipsDSPInstrFormats.td"
1362 include "MipsDSPInstrInfo.td"
1365 include "MipsMSAInstrFormats.td"
1366 include "MipsMSAInstrInfo.td"
1369 include "MicroMipsInstrFormats.td"
1370 include "MicroMipsInstrInfo.td"