1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
160 AssemblerPredicate<"!FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
164 AssemblerPredicate<"FeatureMips5_32r2">;
165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
166 AssemblerPredicate<"FeatureMips32">;
167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
168 AssemblerPredicate<"FeatureMips32r2">;
169 def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
170 AssemblerPredicate<"FeatureMips32r5">;
171 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
172 AssemblerPredicate<"FeatureMips32r6">;
173 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
174 AssemblerPredicate<"!FeatureMips32r6">;
175 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
176 AssemblerPredicate<"FeatureGP64Bit">;
177 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
178 AssemblerPredicate<"!FeatureGP64Bit">;
179 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
180 AssemblerPredicate<"FeatureMips64">;
181 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
182 AssemblerPredicate<"FeatureMips64r2">;
183 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
184 AssemblerPredicate<"FeatureMips64r6">;
185 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
186 AssemblerPredicate<"!FeatureMips64r6">;
187 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
188 AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
189 def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
190 AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
191 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
192 AssemblerPredicate<"FeatureMips16">;
193 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
194 AssemblerPredicate<"FeatureCnMips">;
195 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
196 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
197 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
198 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
199 AssemblerPredicate<"!FeatureMips16">;
200 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
201 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
202 AssemblerPredicate<"FeatureMicroMips">;
203 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
204 AssemblerPredicate<"!FeatureMicroMips">;
205 def IsLE : Predicate<"Subtarget->isLittle()">;
206 def IsBE : Predicate<"!Subtarget->isLittle()">;
207 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
208 def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
209 def HasEVA : Predicate<"Subtarget->hasEVA()">,
210 AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
211 def HasMSA : Predicate<"Subtarget->hasMSA()">,
212 AssemblerPredicate<"FeatureMSA">;
215 //===----------------------------------------------------------------------===//
216 // Mips GPR size adjectives.
217 // They are mutually exclusive.
218 //===----------------------------------------------------------------------===//
220 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
221 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
223 //===----------------------------------------------------------------------===//
224 // Mips ISA/ASE membership and instruction group membership adjectives.
225 // They are mutually exclusive.
226 //===----------------------------------------------------------------------===//
228 // FIXME: I'd prefer to use additive predicates to build the instruction sets
229 // but we are short on assembler feature bits at the moment. Using a
230 // subtractive predicate will hopefully keep us under the 32 predicate
231 // limit long enough to develop an alternative way to handle P1||P2
233 class ISA_MIPS1_NOT_4_32 {
234 list<Predicate> InsnPredicates = [NotMips4_32];
236 class ISA_MIPS1_NOT_32R6_64R6 {
237 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
239 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
240 class ISA_MIPS2_NOT_32R6_64R6 {
241 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
243 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
244 class ISA_MIPS3_NOT_32R6_64R6 {
245 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
247 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
248 class ISA_MIPS32_NOT_32R6_64R6 {
249 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
251 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
252 class ISA_MIPS32R2_NOT_32R6_64R6 {
253 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
255 class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
256 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
257 class ISA_MIPS64_NOT_64R6 {
258 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
260 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
261 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
262 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
263 class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
264 class ISA_MICROMIPS32R6 {
265 list<Predicate> InsnPredicates = [HasMicroMips32r6];
267 class ISA_MICROMIPS64R6 {
268 list<Predicate> InsnPredicates = [HasMicroMips64r6];
271 class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
272 class INSN_EVA_NOT_32R6_64R6 {
273 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
276 // The portions of MIPS-III that were also added to MIPS32
277 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
279 // The portions of MIPS-III that were also added to MIPS32 but were removed in
280 // MIPS32r6 and MIPS64r6.
281 class INSN_MIPS3_32_NOT_32R6_64R6 {
282 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
285 // The portions of MIPS-III that were also added to MIPS32
286 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
288 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
289 // MIPS32r6 and MIPS64r6.
290 class INSN_MIPS4_32_NOT_32R6_64R6 {
291 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
294 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
295 // MIPS32r6 and MIPS64r6.
296 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
297 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
300 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
301 // MIPS32r6 and MIPS64r6.
302 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
303 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
307 list<Predicate> InsnPredicates = [HasMSA];
311 list<Predicate> InsnPredicates = [HasMSA, HasMips64];
314 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
315 // It can be used only on instructions that doesn't inherit PredicateControl.
316 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
317 let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
320 //===----------------------------------------------------------------------===//
322 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
323 let EncodingPredicates = [HasStdEnc];
326 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
327 InstAlias<Asm, Result, Emit>, PredicateControl;
330 bit isCommutable = 1;
347 bit isTerminator = 1;
350 bit hasExtraSrcRegAllocReq = 1;
351 bit isCodeGenOnly = 1;
354 class IsAsCheapAsAMove {
355 bit isAsCheapAsAMove = 1;
358 class NeverHasSideEffects {
359 bit hasSideEffects = 0;
362 //===----------------------------------------------------------------------===//
363 // Instruction format superclass
364 //===----------------------------------------------------------------------===//
366 include "MipsInstrFormats.td"
368 //===----------------------------------------------------------------------===//
369 // Mips Operand, Complex Patterns and Transformations Definitions.
370 //===----------------------------------------------------------------------===//
372 def MipsJumpTargetAsmOperand : AsmOperandClass {
373 let Name = "JumpTarget";
374 let ParserMethod = "parseJumpTarget";
375 let PredicateMethod = "isImm";
376 let RenderMethod = "addImmOperands";
379 // Instruction operand types
380 def jmptarget : Operand<OtherVT> {
381 let EncoderMethod = "getJumpTargetOpValue";
382 let ParserMatchClass = MipsJumpTargetAsmOperand;
384 def brtarget : Operand<OtherVT> {
385 let EncoderMethod = "getBranchTargetOpValue";
386 let OperandType = "OPERAND_PCREL";
387 let DecoderMethod = "DecodeBranchTarget";
388 let ParserMatchClass = MipsJumpTargetAsmOperand;
390 def calltarget : Operand<iPTR> {
391 let EncoderMethod = "getJumpTargetOpValue";
392 let ParserMatchClass = MipsJumpTargetAsmOperand;
395 def imm64: Operand<i64>;
397 def simm9 : Operand<i32>;
398 def simm10 : Operand<i32>;
399 def simm11 : Operand<i32>;
401 def simm16 : Operand<i32> {
402 let DecoderMethod= "DecodeSimm16";
405 def simm19_lsl2 : Operand<i32> {
406 let EncoderMethod = "getSimm19Lsl2Encoding";
407 let DecoderMethod = "DecodeSimm19Lsl2";
408 let ParserMatchClass = MipsJumpTargetAsmOperand;
411 def simm18_lsl3 : Operand<i32> {
412 let EncoderMethod = "getSimm18Lsl3Encoding";
413 let DecoderMethod = "DecodeSimm18Lsl3";
414 let ParserMatchClass = MipsJumpTargetAsmOperand;
417 def simm20 : Operand<i32> {
420 def uimm20 : Operand<i32> {
423 def MipsUImm10AsmOperand : AsmOperandClass {
425 let RenderMethod = "addImmOperands";
426 let ParserMethod = "parseImm";
427 let PredicateMethod = "isUImm<10>";
430 def uimm10 : Operand<i32> {
431 let ParserMatchClass = MipsUImm10AsmOperand;
434 def simm16_64 : Operand<i64> {
435 let DecoderMethod = "DecodeSimm16";
439 def uimmz : Operand<i32> {
440 let PrintMethod = "printUnsignedImm";
444 def uimm2 : Operand<i32> {
445 let PrintMethod = "printUnsignedImm";
448 def uimm3 : Operand<i32> {
449 let PrintMethod = "printUnsignedImm";
452 def uimm5 : Operand<i32> {
453 let PrintMethod = "printUnsignedImm";
456 def uimm6 : Operand<i32> {
457 let PrintMethod = "printUnsignedImm";
460 def uimm16 : Operand<i32> {
461 let PrintMethod = "printUnsignedImm";
464 def pcrel16 : Operand<i32> {
467 def MipsMemAsmOperand : AsmOperandClass {
469 let ParserMethod = "parseMemOperand";
472 def MipsMemSimm9AsmOperand : AsmOperandClass {
473 let Name = "MemOffsetSimm9";
474 let SuperClasses = [MipsMemAsmOperand];
475 let RenderMethod = "addMemOperands";
476 let ParserMethod = "parseMemOperand";
477 let PredicateMethod = "isMemWithSimmOffset<9>";
480 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
481 let Name = "MemOffsetSimm9GPR";
482 let SuperClasses = [MipsMemAsmOperand];
483 let RenderMethod = "addMemOperands";
484 let ParserMethod = "parseMemOperand";
485 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
488 def MipsMemSimm11AsmOperand : AsmOperandClass {
489 let Name = "MemOffsetSimm11";
490 let SuperClasses = [MipsMemAsmOperand];
491 let RenderMethod = "addMemOperands";
492 let ParserMethod = "parseMemOperand";
493 let PredicateMethod = "isMemWithSimmOffset<11>";
496 def MipsMemSimm16AsmOperand : AsmOperandClass {
497 let Name = "MemOffsetSimm16";
498 let SuperClasses = [MipsMemAsmOperand];
499 let RenderMethod = "addMemOperands";
500 let ParserMethod = "parseMemOperand";
501 let PredicateMethod = "isMemWithSimmOffset<16>";
504 def MipsInvertedImmoperand : AsmOperandClass {
506 let RenderMethod = "addImmOperands";
507 let ParserMethod = "parseInvNum";
510 def InvertedImOperand : Operand<i32> {
511 let ParserMatchClass = MipsInvertedImmoperand;
514 def InvertedImOperand64 : Operand<i64> {
515 let ParserMatchClass = MipsInvertedImmoperand;
518 class mem_generic : Operand<iPTR> {
519 let PrintMethod = "printMemOperand";
520 let MIOperandInfo = (ops ptr_rc, simm16);
521 let EncoderMethod = "getMemEncoding";
522 let ParserMatchClass = MipsMemAsmOperand;
523 let OperandType = "OPERAND_MEMORY";
527 def mem : mem_generic;
529 // MSA specific address operand
530 def mem_msa : mem_generic {
531 let MIOperandInfo = (ops ptr_rc, simm10);
532 let EncoderMethod = "getMSAMemEncoding";
535 def mem_simm9 : mem_generic {
536 let MIOperandInfo = (ops ptr_rc, simm9);
537 let EncoderMethod = "getMemEncoding";
538 let ParserMatchClass = MipsMemSimm9AsmOperand;
541 def mem_simm9gpr : mem_generic {
542 let MIOperandInfo = (ops ptr_rc, simm9);
543 let EncoderMethod = "getMemEncoding";
544 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
547 def mem_simm11 : mem_generic {
548 let MIOperandInfo = (ops ptr_rc, simm11);
549 let EncoderMethod = "getMemEncoding";
550 let ParserMatchClass = MipsMemSimm11AsmOperand;
553 def mem_simm16 : mem_generic {
554 let MIOperandInfo = (ops ptr_rc, simm16);
555 let EncoderMethod = "getMemEncoding";
556 let ParserMatchClass = MipsMemSimm16AsmOperand;
559 def mem_ea : Operand<iPTR> {
560 let PrintMethod = "printMemOperandEA";
561 let MIOperandInfo = (ops ptr_rc, simm16);
562 let EncoderMethod = "getMemEncoding";
563 let OperandType = "OPERAND_MEMORY";
566 def PtrRC : Operand<iPTR> {
567 let MIOperandInfo = (ops ptr_rc);
568 let DecoderMethod = "DecodePtrRegisterClass";
569 let ParserMatchClass = GPR32AsmOperand;
572 // size operand of ext instruction
573 def size_ext : Operand<i32> {
574 let EncoderMethod = "getSizeExtEncoding";
575 let DecoderMethod = "DecodeExtSize";
578 // size operand of ins instruction
579 def size_ins : Operand<i32> {
580 let EncoderMethod = "getSizeInsEncoding";
581 let DecoderMethod = "DecodeInsSize";
584 // Transformation Function - get the lower 16 bits.
585 def LO16 : SDNodeXForm<imm, [{
586 return getImm(N, N->getZExtValue() & 0xFFFF);
589 // Transformation Function - get the higher 16 bits.
590 def HI16 : SDNodeXForm<imm, [{
591 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
595 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
597 // Node immediate is zero (e.g. insve.d)
598 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
600 // Node immediate fits as 16-bit sign extended on target immediate.
602 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
604 // Node immediate fits as 16-bit sign extended on target immediate.
606 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
608 // Node immediate fits as 15-bit sign extended on target immediate.
610 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
612 // Node immediate fits as 16-bit zero extended on target immediate.
613 // The LO16 param means that only the lower 16 bits of the node
614 // immediate are caught.
616 def immZExt16 : PatLeaf<(imm), [{
617 if (N->getValueType(0) == MVT::i32)
618 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
620 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
623 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
624 def immLow16Zero : PatLeaf<(imm), [{
625 int64_t Val = N->getSExtValue();
626 return isInt<32>(Val) && !(Val & 0xffff);
629 // shamt field must fit in 5 bits.
630 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
632 // True if (N + 1) fits in 16-bit field.
633 def immSExt16Plus1 : PatLeaf<(imm), [{
634 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
637 // Mips Address Mode! SDNode frameindex could possibily be a match
638 // since load and store instructions from stack used it.
640 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
643 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
646 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
649 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
651 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
653 //===----------------------------------------------------------------------===//
654 // Instructions specific format
655 //===----------------------------------------------------------------------===//
657 // Arithmetic and logical instructions with 3 register operands.
658 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
659 InstrItinClass Itin = NoItinerary,
660 SDPatternOperator OpNode = null_frag>:
661 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
662 !strconcat(opstr, "\t$rd, $rs, $rt"),
663 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
664 let isCommutable = isComm;
665 let isReMaterializable = 1;
666 let TwoOperandAliasConstraint = "$rd = $rs";
669 // Arithmetic and logical instructions with 2 register operands.
670 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
671 InstrItinClass Itin = NoItinerary,
672 SDPatternOperator imm_type = null_frag,
673 SDPatternOperator OpNode = null_frag> :
674 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
675 !strconcat(opstr, "\t$rt, $rs, $imm16"),
676 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
678 let isReMaterializable = 1;
679 let TwoOperandAliasConstraint = "$rs = $rt";
682 // Arithmetic Multiply ADD/SUB
683 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
684 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
685 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
686 let Defs = [HI0, LO0];
687 let Uses = [HI0, LO0];
688 let isCommutable = isComm;
692 class LogicNOR<string opstr, RegisterOperand RO>:
693 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
694 !strconcat(opstr, "\t$rd, $rs, $rt"),
695 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
696 let isCommutable = 1;
700 class shift_rotate_imm<string opstr, Operand ImmOpnd,
701 RegisterOperand RO, InstrItinClass itin,
702 SDPatternOperator OpNode = null_frag,
703 SDPatternOperator PF = null_frag> :
704 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
705 !strconcat(opstr, "\t$rd, $rt, $shamt"),
706 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
707 let TwoOperandAliasConstraint = "$rt = $rd";
710 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
711 SDPatternOperator OpNode = null_frag>:
712 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
713 !strconcat(opstr, "\t$rd, $rt, $rs"),
714 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
717 // Load Upper Immediate
718 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
719 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
720 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
721 let hasSideEffects = 0;
722 let isReMaterializable = 1;
726 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
727 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
728 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
729 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
730 let DecoderMethod = "DecodeMem";
731 let canFoldAsLoad = 1;
735 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
736 SDPatternOperator OpNode = null_frag,
737 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
738 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
739 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
740 let DecoderMethod = "DecodeMem";
744 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
745 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
746 StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
748 // Load/Store Left/Right
749 let canFoldAsLoad = 1 in
750 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
751 InstrItinClass Itin> :
752 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
753 !strconcat(opstr, "\t$rt, $addr"),
754 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
755 let DecoderMethod = "DecodeMem";
756 string Constraints = "$src = $rt";
759 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
760 InstrItinClass Itin> :
761 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
762 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
763 let DecoderMethod = "DecodeMem";
767 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
768 SDPatternOperator OpNode= null_frag> :
769 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
770 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
771 let DecoderMethod = "DecodeFMem2";
775 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
776 SDPatternOperator OpNode= null_frag> :
777 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
778 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
779 let DecoderMethod = "DecodeFMem2";
784 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
785 SDPatternOperator OpNode= null_frag> :
786 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
787 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
788 let DecoderMethod = "DecodeFMem3";
792 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
793 SDPatternOperator OpNode= null_frag> :
794 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
795 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
796 let DecoderMethod = "DecodeFMem3";
800 // Conditional Branch
801 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
802 RegisterOperand RO, bit DelaySlot = 1> :
803 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
804 !strconcat(opstr, "\t$rs, $rt, $offset"),
805 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
808 let isTerminator = 1;
809 let hasDelaySlot = DelaySlot;
813 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
814 RegisterOperand RO, bit DelaySlot = 1> :
815 InstSE<(outs), (ins RO:$rs, opnd:$offset),
816 !strconcat(opstr, "\t$rs, $offset"),
817 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
820 let isTerminator = 1;
821 let hasDelaySlot = DelaySlot;
826 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
827 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
828 !strconcat(opstr, "\t$rd, $rs, $rt"),
829 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
830 II_SLT_SLTU, FrmR, opstr>;
832 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
834 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
835 !strconcat(opstr, "\t$rt, $rs, $imm16"),
836 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
837 II_SLTI_SLTIU, FrmI, opstr>;
840 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
841 SDPatternOperator targetoperator, string bopstr> :
842 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
843 [(operator targetoperator:$target)], II_J, FrmJ, bopstr> {
846 let hasDelaySlot = 1;
847 let DecoderMethod = "DecodeJumpTarget";
851 // Unconditional branch
852 class UncondBranch<Instruction BEQInst> :
853 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
854 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
856 let isTerminator = 1;
858 let hasDelaySlot = 1;
859 let AdditionalPredicates = [RelocPIC];
863 // Base class for indirect branch and return instruction classes.
864 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
865 class JumpFR<string opstr, RegisterOperand RO,
866 SDPatternOperator operator = null_frag>:
867 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
871 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
873 let isIndirectBranch = 1;
876 // Jump and Link (Call)
877 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
878 class JumpLink<string opstr, DAGOperand opnd> :
879 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
880 [(MipsJmpLink imm:$target)], II_JAL, FrmJ, opstr> {
881 let DecoderMethod = "DecodeJumpTarget";
884 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
885 Register RetReg, RegisterOperand ResRO = RO>:
886 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
887 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
889 class JumpLinkReg<string opstr, RegisterOperand RO>:
890 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
891 [], II_JALR, FrmR, opstr>;
893 class BGEZAL_FT<string opstr, DAGOperand opnd,
894 RegisterOperand RO, bit DelaySlot = 1> :
895 InstSE<(outs), (ins RO:$rs, opnd:$offset),
896 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
897 let hasDelaySlot = DelaySlot;
902 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
903 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
904 class TailCall<Instruction JumpInst> :
905 PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
906 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
908 class TailCallReg<RegisterOperand RO, Instruction JRInst,
909 RegisterOperand ResRO = RO> :
910 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
911 PseudoInstExpansion<(JRInst ResRO:$rs)>;
914 class BAL_BR_Pseudo<Instruction RealInst> :
915 PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
916 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
918 let isTerminator = 1;
920 let hasDelaySlot = 1;
925 class SYS_FT<string opstr> :
926 InstSE<(outs), (ins uimm20:$code_),
927 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
929 class BRK_FT<string opstr> :
930 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
931 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
935 class ER_FT<string opstr> :
936 InstSE<(outs), (ins),
937 opstr, [], NoItinerary, FrmOther, opstr>;
940 class DEI_FT<string opstr, RegisterOperand RO> :
941 InstSE<(outs RO:$rt), (ins),
942 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
945 class WAIT_FT<string opstr> :
946 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
949 let hasSideEffects = 1 in
950 class SYNC_FT<string opstr> :
951 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
952 NoItinerary, FrmOther, opstr>;
954 class SYNCI_FT<string opstr> :
955 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
956 NoItinerary, FrmOther, opstr> {
957 let hasSideEffects = 1;
958 let DecoderMethod = "DecodeSyncI";
961 let hasSideEffects = 1 in
962 class TEQ_FT<string opstr, RegisterOperand RO> :
963 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
964 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
967 class TEQI_FT<string opstr, RegisterOperand RO> :
968 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
969 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
971 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
972 list<Register> DefRegs> :
973 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
975 let isCommutable = 1;
977 let hasSideEffects = 0;
980 // Pseudo multiply/divide instruction with explicit accumulator register
982 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
983 SDPatternOperator OpNode, InstrItinClass Itin,
984 bit IsComm = 1, bit HasSideEffects = 0,
985 bit UsesCustomInserter = 0> :
986 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
987 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
988 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
989 let isCommutable = IsComm;
990 let hasSideEffects = HasSideEffects;
991 let usesCustomInserter = UsesCustomInserter;
994 // Pseudo multiply add/sub instruction with explicit accumulator register
996 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
998 : PseudoSE<(outs ACC64:$ac),
999 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
1001 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
1003 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
1004 string Constraints = "$acin = $ac";
1007 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1008 list<Register> DefRegs> :
1009 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1010 [], itin, FrmR, opstr> {
1015 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
1016 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
1017 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
1019 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1020 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1022 let Uses = [UseReg];
1023 let hasSideEffects = 0;
1026 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
1027 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
1028 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
1031 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1032 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1035 let hasSideEffects = 0;
1038 class EffectiveAddress<string opstr, RegisterOperand RO> :
1039 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1040 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
1041 !strconcat(opstr, "_lea")> {
1042 let isCodeGenOnly = 1;
1043 let DecoderMethod = "DecodeMem";
1046 // Count Leading Ones/Zeros in Word
1047 class CountLeading0<string opstr, RegisterOperand RO>:
1048 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1049 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
1051 class CountLeading1<string opstr, RegisterOperand RO>:
1052 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1053 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
1055 // Sign Extend in Register.
1056 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1057 InstrItinClass itin> :
1058 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1059 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1062 class SubwordSwap<string opstr, RegisterOperand RO,
1063 InstrItinClass itin = NoItinerary>:
1064 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1066 let hasSideEffects = 0;
1070 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1071 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
1072 II_RDHWR, FrmR, "rdhwr">;
1075 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1076 SDPatternOperator Op = null_frag>:
1077 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1078 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1079 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
1080 FrmR, opstr>, ISA_MIPS32R2;
1082 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1083 SDPatternOperator Op = null_frag>:
1084 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1085 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1086 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1087 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
1088 let Constraints = "$src = $rt";
1091 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1092 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1093 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1094 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1096 // Atomic Compare & Swap.
1097 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1098 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1099 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1101 class LLBase<string opstr, RegisterOperand RO> :
1102 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1103 [], NoItinerary, FrmI> {
1104 let DecoderMethod = "DecodeMem";
1108 class SCBase<string opstr, RegisterOperand RO> :
1109 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1110 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1111 let DecoderMethod = "DecodeMem";
1113 let Constraints = "$rt = $dst";
1116 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1117 InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
1118 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1120 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1121 InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
1122 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1124 class TrapBase<Instruction RealInst>
1125 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1126 PseudoInstExpansion<(RealInst 0, 0)> {
1128 let isTerminator = 1;
1129 let isCodeGenOnly = 1;
1132 //===----------------------------------------------------------------------===//
1133 // Pseudo instructions
1134 //===----------------------------------------------------------------------===//
1137 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1138 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1140 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1141 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1142 [(callseq_start timm:$amt)]>;
1143 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1144 [(callseq_end timm:$amt1, timm:$amt2)]>;
1147 let usesCustomInserter = 1 in {
1148 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1149 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1150 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1151 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1152 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1153 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1154 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1155 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1156 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1157 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1158 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1159 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1160 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1161 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1162 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1163 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1164 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1165 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1167 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1168 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1169 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1171 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1172 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1173 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1176 /// Pseudo instructions for loading and storing accumulator registers.
1177 let isPseudo = 1, isCodeGenOnly = 1 in {
1178 def LOAD_ACC64 : Load<"", ACC64>;
1179 def STORE_ACC64 : Store<"", ACC64>;
1182 // We need these two pseudo instructions to avoid offset calculation for long
1183 // branches. See the comment in file MipsLongBranch.cpp for detailed
1186 // Expands to: lui $dst, %hi($tgt - $baltgt)
1187 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1188 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1190 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1191 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1192 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1194 //===----------------------------------------------------------------------===//
1195 // Instruction definition
1196 //===----------------------------------------------------------------------===//
1197 //===----------------------------------------------------------------------===//
1198 // MipsI Instructions
1199 //===----------------------------------------------------------------------===//
1201 /// Arithmetic Instructions (ALU Immediate)
1202 let AdditionalPredicates = [NotInMicroMips] in {
1203 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1204 II_ADDIU, immSExt16, add>,
1205 ADDI_FM<0x9>, IsAsCheapAsAMove;
1207 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1208 ISA_MIPS1_NOT_32R6_64R6;
1209 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1211 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1213 let AdditionalPredicates = [NotInMicroMips] in {
1214 def ANDi : MMRel, StdMMR6Rel,
1215 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
1218 def ORi : MMRel, StdMMR6Rel,
1219 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
1221 def XORi : MMRel, StdMMR6Rel,
1222 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
1224 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1225 let AdditionalPredicates = [NotInMicroMips] in {
1226 /// Arithmetic Instructions (3-Operand, R-Type)
1227 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1229 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1232 let Defs = [HI0, LO0] in
1233 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1234 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1235 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1236 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1237 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1238 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1239 let AdditionalPredicates = [NotInMicroMips] in {
1240 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1242 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1244 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1247 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1249 /// Shift Instructions
1250 let AdditionalPredicates = [NotInMicroMips] in {
1251 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1252 immZExt5>, SRA_FM<0, 0>;
1253 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1254 immZExt5>, SRA_FM<2, 0>;
1256 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1257 immZExt5>, SRA_FM<3, 0>;
1258 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1260 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1262 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1265 // Rotate Instructions
1266 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1268 SRA_FM<2, 1>, ISA_MIPS32R2;
1269 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1270 SRLV_FM<6, 1>, ISA_MIPS32R2;
1272 /// Load and Store Instructions
1274 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1275 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1277 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1279 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1280 let AdditionalPredicates = [NotInMicroMips] in {
1281 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1284 def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
1286 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1287 let AdditionalPredicates = [NotInMicroMips] in {
1288 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1291 /// load/store left/right
1292 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1293 AdditionalPredicates = [NotInMicroMips] in {
1294 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1295 ISA_MIPS1_NOT_32R6_64R6;
1296 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1297 ISA_MIPS1_NOT_32R6_64R6;
1298 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1299 ISA_MIPS1_NOT_32R6_64R6;
1300 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1301 ISA_MIPS1_NOT_32R6_64R6;
1304 let AdditionalPredicates = [NotInMicroMips] in {
1305 // COP2 Memory Instructions
1306 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1307 ISA_MIPS1_NOT_32R6_64R6;
1308 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1309 ISA_MIPS1_NOT_32R6_64R6;
1310 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1311 ISA_MIPS2_NOT_32R6_64R6;
1312 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1313 ISA_MIPS2_NOT_32R6_64R6;
1315 // COP3 Memory Instructions
1316 let DecoderNamespace = "COP3_" in {
1317 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1318 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1319 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1321 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1326 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1327 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1329 let AdditionalPredicates = [NotInMicroMips] in {
1330 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1331 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1332 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1333 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1334 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1335 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1338 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1339 ISA_MIPS2_NOT_32R6_64R6;
1340 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1341 ISA_MIPS2_NOT_32R6_64R6;
1342 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1343 ISA_MIPS2_NOT_32R6_64R6;
1344 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1345 ISA_MIPS2_NOT_32R6_64R6;
1346 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1347 ISA_MIPS2_NOT_32R6_64R6;
1348 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1349 ISA_MIPS2_NOT_32R6_64R6;
1351 let AdditionalPredicates = [NotInMicroMips] in {
1352 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
1354 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1355 def TRAP : TrapBase<BREAK>;
1356 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1358 let AdditionalPredicates = [NotInMicroMips] in {
1359 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
1360 def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
1362 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
1364 let AdditionalPredicates = [NotInMicroMips] in {
1365 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1367 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1369 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1370 AdditionalPredicates = [NotInMicroMips] in {
1371 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1373 /// Load-linked, Store-conditional
1374 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1375 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1378 /// Jump and Branch Instructions
1379 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1380 AdditionalRequires<[RelocStatic]>, IsBranch;
1381 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1382 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1383 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1384 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1385 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1386 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1387 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1388 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1390 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1391 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1392 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1394 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1395 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1396 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1398 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1399 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1400 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1402 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1403 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1404 def B : UncondBranch<BEQ>;
1406 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1407 let AdditionalPredicates = [NotInMicroMips] in {
1408 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1409 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1412 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1413 ISA_MIPS32_NOT_32R6_64R6;
1414 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1415 ISA_MIPS1_NOT_32R6_64R6;
1416 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1417 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1418 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1419 ISA_MIPS1_NOT_32R6_64R6;
1420 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1421 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1422 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1423 def TAILCALL : TailCall<J>;
1424 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1426 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1427 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1428 class PseudoIndirectBranchBase<RegisterOperand RO> :
1429 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1430 II_IndirectBranchPseudo> {
1433 let hasDelaySlot = 1;
1435 let isIndirectBranch = 1;
1438 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1440 // Return instructions are matched as a RetRA instruction, then are expanded
1441 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1442 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1444 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1445 [], II_ReturnPseudo> {
1446 let isTerminator = 1;
1448 let hasDelaySlot = 1;
1450 let isCodeGenOnly = 1;
1452 let hasExtraSrcRegAllocReq = 1;
1455 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1457 // Exception handling related node and instructions.
1458 // The conversion sequence is:
1459 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1460 // MIPSeh_return -> (stack change + indirect branch)
1462 // MIPSeh_return takes the place of regular return instruction
1463 // but takes two arguments (V1, V0) which are used for storing
1464 // the offset and return address respectively.
1465 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1467 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1468 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1470 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1471 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1472 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1473 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1475 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1478 /// Multiply and Divide Instructions.
1479 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1480 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1481 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1482 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1483 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1484 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1485 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1486 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1488 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1489 ISA_MIPS1_NOT_32R6_64R6;
1490 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1491 ISA_MIPS1_NOT_32R6_64R6;
1492 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1493 AdditionalPredicates = [NotInMicroMips] in {
1494 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1495 ISA_MIPS1_NOT_32R6_64R6;
1496 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1497 ISA_MIPS1_NOT_32R6_64R6;
1500 /// Sign Ext In Register Instructions.
1501 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1502 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1503 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1504 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1507 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1508 ISA_MIPS32_NOT_32R6_64R6;
1509 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1510 ISA_MIPS32_NOT_32R6_64R6;
1512 /// Word Swap Bytes Within Halfwords
1513 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
1517 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1519 // FrameIndexes are legalized when they are operands from load/store
1520 // instructions. The same not happens for stack address copies, so an
1521 // add op with mem ComplexPattern is used and the stack address copy
1522 // can be matched. It's similar to Sparc LEA_ADDRi
1523 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1526 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1527 ISA_MIPS32_NOT_32R6_64R6;
1528 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1529 ISA_MIPS32_NOT_32R6_64R6;
1530 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1531 ISA_MIPS32_NOT_32R6_64R6;
1532 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1533 ISA_MIPS32_NOT_32R6_64R6;
1535 let AdditionalPredicates = [NotDSP] in {
1536 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1537 ISA_MIPS1_NOT_32R6_64R6;
1538 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1539 ISA_MIPS1_NOT_32R6_64R6;
1540 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1541 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1542 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1543 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1544 ISA_MIPS32_NOT_32R6_64R6;
1545 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1546 ISA_MIPS32_NOT_32R6_64R6;
1547 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1548 ISA_MIPS32_NOT_32R6_64R6;
1549 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1550 ISA_MIPS32_NOT_32R6_64R6;
1553 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1554 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1555 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1556 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1558 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1560 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1561 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1563 /// Move Control Registers From/To CPU Registers
1564 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1565 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1566 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
1567 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1569 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1571 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
1572 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1573 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1575 // JR_HB and JALR_HB are defined here using the new style naming
1576 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1577 // and because of that it doesn't follow the naming convention of the
1578 // rest of the file. To avoid a mixture of old vs new style, the new
1579 // style was chosen.
1580 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1581 dag OutOperandList = (outs);
1582 dag InOperandList = (ins GPROpnd:$rs);
1583 string AsmString = !strconcat(instr_asm, "\t$rs");
1584 list<dag> Pattern = [];
1587 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1588 dag OutOperandList = (outs GPROpnd:$rd);
1589 dag InOperandList = (ins GPROpnd:$rs);
1590 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1591 list<dag> Pattern = [];
1594 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1595 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1597 let isIndirectBranch=1;
1603 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1604 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1605 let isIndirectBranch=1;
1609 class JR_HB_ENC : JR_HB_FM<8>;
1610 class JALR_HB_ENC : JALR_HB_FM<9>;
1612 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1613 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1615 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1617 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1618 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1619 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1620 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1622 class CacheOp<string instr_asm, Operand MemOpnd> :
1623 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1624 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1626 let DecoderMethod = "DecodeCacheOp";
1629 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1630 INSN_MIPS3_32_NOT_32R6_64R6;
1631 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1632 INSN_MIPS3_32_NOT_32R6_64R6;
1634 //===----------------------------------------------------------------------===//
1635 // Instruction aliases
1636 //===----------------------------------------------------------------------===//
1637 def : MipsInstAlias<"move $dst, $src",
1638 (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1640 let AdditionalPredicates = [NotInMicroMips];
1642 def : MipsInstAlias<"move $dst, $src",
1643 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1645 let AdditionalPredicates = [NotInMicroMips];
1647 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1648 ISA_MIPS1_NOT_32R6_64R6;
1649 def : MipsInstAlias<"addu $rs, $rt, $imm",
1650 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1651 def : MipsInstAlias<"addu $rs, $imm",
1652 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1653 def : MipsInstAlias<"add $rs, $rt, $imm",
1654 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1655 ISA_MIPS1_NOT_32R6_64R6;
1656 def : MipsInstAlias<"add $rs, $imm",
1657 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1658 ISA_MIPS1_NOT_32R6_64R6;
1659 def : MipsInstAlias<"and $rs, $rt, $imm",
1660 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1661 def : MipsInstAlias<"and $rs, $imm",
1662 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1663 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1664 let Predicates = [NotInMicroMips] in {
1665 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1667 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1668 def : MipsInstAlias<"not $rt, $rs",
1669 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1670 def : MipsInstAlias<"neg $rt, $rs",
1671 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1672 def : MipsInstAlias<"negu $rt",
1673 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1674 def : MipsInstAlias<"negu $rt, $rs",
1675 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1676 def : MipsInstAlias<"slt $rs, $rt, $imm",
1677 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1678 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1679 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1680 def : MipsInstAlias<"xor $rs, $rt, $imm",
1681 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1682 def : MipsInstAlias<"xor $rs, $imm",
1683 (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1684 def : MipsInstAlias<"or $rs, $rt, $imm",
1685 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1686 def : MipsInstAlias<"or $rs, $imm",
1687 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1688 let AdditionalPredicates = [NotInMicroMips] in {
1689 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1691 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
1692 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1693 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
1694 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1695 let AdditionalPredicates = [NotInMicroMips] in {
1696 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1698 def : MipsInstAlias<"bnez $rs,$offset",
1699 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1700 def : MipsInstAlias<"bnezl $rs,$offset",
1701 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1702 def : MipsInstAlias<"beqz $rs,$offset",
1703 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1704 def : MipsInstAlias<"beqzl $rs,$offset",
1705 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1706 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1708 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1709 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1710 let AdditionalPredicates = [NotInMicroMips] in {
1711 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1713 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1714 let AdditionalPredicates = [NotInMicroMips] in {
1715 def : MipsInstAlias<"teq $rs, $rt",
1716 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1717 def : MipsInstAlias<"tge $rs, $rt",
1718 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1719 def : MipsInstAlias<"tgeu $rs, $rt",
1720 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1721 def : MipsInstAlias<"tlt $rs, $rt",
1722 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1723 def : MipsInstAlias<"tltu $rs, $rt",
1724 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1725 def : MipsInstAlias<"tne $rs, $rt",
1726 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1728 def : MipsInstAlias<"sll $rd, $rt, $rs",
1729 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1730 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1731 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1732 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1733 def : MipsInstAlias<"sub $rs, $imm",
1734 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1735 0>, ISA_MIPS1_NOT_32R6_64R6;
1736 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1737 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1738 InvertedImOperand:$imm), 0>;
1739 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1740 InvertedImOperand:$imm), 0>;
1741 def : MipsInstAlias<"sra $rd, $rt, $rs",
1742 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1743 def : MipsInstAlias<"srl $rd, $rt, $rs",
1744 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1745 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1746 def : MipsInstAlias<"sync",
1747 (SYNC 0), 1>, ISA_MIPS2;
1748 //===----------------------------------------------------------------------===//
1749 // Assembler Pseudo Instructions
1750 //===----------------------------------------------------------------------===//
1752 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
1753 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1754 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1755 def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
1757 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
1758 RegisterOperand RO> :
1759 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1760 !strconcat(instr_asm, "\t$rt, $addr")> ;
1761 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
1763 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
1764 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1765 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1766 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
1768 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1770 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1773 let hasDelaySlot = 1 in {
1774 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1775 (ins imm64:$imm64, brtarget:$offset),
1776 "bne\t$rt, $imm64, $offset">;
1777 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1778 (ins imm64:$imm64, brtarget:$offset),
1779 "beq\t$rt, $imm64, $offset">;
1781 class CondBranchPseudo<string instr_asm> :
1782 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
1784 !strconcat(instr_asm, "\t$rs, $rt, $offset")>;
1787 def BLT : CondBranchPseudo<"blt">;
1788 def BLE : CondBranchPseudo<"ble">;
1789 def BGE : CondBranchPseudo<"bge">;
1790 def BGT : CondBranchPseudo<"bgt">;
1791 def BLTU : CondBranchPseudo<"bltu">;
1792 def BLEU : CondBranchPseudo<"bleu">;
1793 def BGEU : CondBranchPseudo<"bgeu">;
1794 def BGTU : CondBranchPseudo<"bgtu">;
1795 def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
1796 def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
1797 def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
1798 def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
1799 def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
1800 def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
1801 def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
1802 def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
1804 // FIXME: Predicates are removed because instructions are matched regardless of
1805 // predicates, because PredicateControl was not in the hierarchy. This was
1806 // done to emit more precise error message from expansion function.
1807 // Once the tablegen-erated errors are made better, this needs to be fixed and
1808 // predicates needs to be restored.
1810 def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1811 "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
1813 def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1814 "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
1816 def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1817 "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
1819 def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1820 "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
1822 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1823 "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
1825 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1826 "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
1828 //===----------------------------------------------------------------------===//
1829 // Arbitrary patterns that map to one or more instructions
1830 //===----------------------------------------------------------------------===//
1832 // Load/store pattern templates.
1833 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1834 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1836 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1837 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1840 let AdditionalPredicates = [NotInMicroMips] in {
1841 def : MipsPat<(i32 immSExt16:$in),
1842 (ADDiu ZERO, imm:$in)>;
1843 def : MipsPat<(i32 immZExt16:$in),
1844 (ORi ZERO, imm:$in)>;
1846 def : MipsPat<(i32 immLow16Zero:$in),
1847 (LUi (HI16 imm:$in))>;
1849 // Arbitrary immediates
1850 def : MipsPat<(i32 imm:$imm),
1851 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1853 // Carry MipsPatterns
1854 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1855 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1856 let AdditionalPredicates = [NotDSP] in {
1857 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1858 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1859 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1860 (ADDiu GPR32:$src, imm:$imm)>;
1863 // Support multiplication for pre-Mips32 targets that don't have
1864 // the MUL instruction.
1865 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1866 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1867 ISA_MIPS1_NOT_32R6_64R6;
1870 def : MipsPat<(MipsSync (i32 immz)),
1871 (SYNC 0)>, ISA_MIPS2;
1874 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1875 (JAL tglobaladdr:$dst)>;
1876 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1877 (JAL texternalsym:$dst)>;
1878 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1879 // (JALR GPR32:$dst)>;
1882 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1883 (TAILCALL tglobaladdr:$dst)>;
1884 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1885 (TAILCALL texternalsym:$dst)>;
1887 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1888 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1889 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1890 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1891 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1892 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1894 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1895 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1896 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1897 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1898 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1899 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1901 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1902 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1903 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1904 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1905 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1906 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1907 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1908 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1909 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1910 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1913 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1914 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1915 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1916 (ADDiu GPR32:$gp, tconstpool:$in)>;
1919 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1920 MipsPat<(MipsWrapper RC:$gp, node:$in),
1921 (ADDiuOp RC:$gp, node:$in)>;
1923 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1924 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1925 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1926 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1927 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1928 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1930 let AdditionalPredicates = [NotInMicroMips] in {
1931 // Mips does not have "not", so we expand our way
1932 def : MipsPat<(not GPR32:$in),
1933 (NOR GPR32Opnd:$in, ZERO)>;
1937 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1938 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1939 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1942 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1945 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1946 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1947 Instruction SLTiuOp, Register ZEROReg> {
1948 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1949 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1950 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1951 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1953 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1954 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1955 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1956 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1957 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1958 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1959 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1960 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1961 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1962 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1963 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1964 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1966 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1967 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1968 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1969 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1971 def : MipsPat<(brcond RC:$cond, bb:$dst),
1972 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1975 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1977 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1978 (BLEZ i32:$lhs, bb:$dst)>;
1979 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1980 (BGEZ i32:$lhs, bb:$dst)>;
1983 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1984 Instruction SLTuOp, Register ZEROReg> {
1985 def : MipsPat<(seteq RC:$lhs, 0),
1986 (SLTiuOp RC:$lhs, 1)>;
1987 def : MipsPat<(setne RC:$lhs, 0),
1988 (SLTuOp ZEROReg, RC:$lhs)>;
1989 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1990 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1991 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1992 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1995 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1996 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1997 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1998 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1999 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
2002 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2003 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
2004 (SLTOp RC:$rhs, RC:$lhs)>;
2005 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
2006 (SLTuOp RC:$rhs, RC:$lhs)>;
2009 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2010 def : MipsPat<(setge RC:$lhs, RC:$rhs),
2011 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
2012 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
2013 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
2016 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
2017 Instruction SLTiuOp> {
2018 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
2019 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
2020 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
2021 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
2024 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
2025 defm : SetlePats<GPR32, SLT, SLTu>;
2026 defm : SetgtPats<GPR32, SLT, SLTu>;
2027 defm : SetgePats<GPR32, SLT, SLTu>;
2028 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
2031 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
2033 // Load halfword/word patterns.
2034 let AddedComplexity = 40 in {
2035 def : LoadRegImmPat<LBu, i32, zextloadi8>;
2036 def : LoadRegImmPat<LH, i32, sextloadi16>;
2037 let AdditionalPredicates = [NotInMicroMips] in {
2038 def : LoadRegImmPat<LW, i32, load>;
2042 //===----------------------------------------------------------------------===//
2043 // Floating Point Support
2044 //===----------------------------------------------------------------------===//
2046 include "MipsInstrFPU.td"
2047 include "Mips64InstrInfo.td"
2048 include "MipsCondMov.td"
2050 include "Mips32r6InstrInfo.td"
2051 include "Mips64r6InstrInfo.td"
2056 include "Mips16InstrFormats.td"
2057 include "Mips16InstrInfo.td"
2060 include "MipsDSPInstrFormats.td"
2061 include "MipsDSPInstrInfo.td"
2064 include "MipsMSAInstrFormats.td"
2065 include "MipsMSAInstrInfo.td"
2068 include "MipsEVAInstrFormats.td"
2069 include "MipsEVAInstrInfo.td"
2072 include "MicroMipsInstrFormats.td"
2073 include "MicroMipsInstrInfo.td"
2074 include "MicroMipsInstrFPU.td"
2077 include "MicroMips32r6InstrFormats.td"
2078 include "MicroMips32r6InstrInfo.td"
2081 include "MicroMips64r6InstrFormats.td"
2082 include "MicroMips64r6InstrInfo.td"