1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
186 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
187 let Predicates = [HasStdEnc];
191 bit isCommutable = 1;
208 bit isTerminator = 1;
211 bit hasExtraSrcRegAllocReq = 1;
212 bit isCodeGenOnly = 1;
215 class IsAsCheapAsAMove {
216 bit isAsCheapAsAMove = 1;
219 class NeverHasSideEffects {
220 bit neverHasSideEffects = 1;
223 //===----------------------------------------------------------------------===//
224 // Instruction format superclass
225 //===----------------------------------------------------------------------===//
227 include "MipsInstrFormats.td"
229 //===----------------------------------------------------------------------===//
230 // Mips Operand, Complex Patterns and Transformations Definitions.
231 //===----------------------------------------------------------------------===//
233 // Instruction operand types
234 def jmptarget : Operand<OtherVT> {
235 let EncoderMethod = "getJumpTargetOpValue";
237 def brtarget : Operand<OtherVT> {
238 let EncoderMethod = "getBranchTargetOpValue";
239 let OperandType = "OPERAND_PCREL";
240 let DecoderMethod = "DecodeBranchTarget";
242 def calltarget : Operand<iPTR> {
243 let EncoderMethod = "getJumpTargetOpValue";
245 def calltarget64: Operand<i64>;
246 def simm16 : Operand<i32> {
247 let DecoderMethod= "DecodeSimm16";
250 def simm20 : Operand<i32> {
253 def simm16_64 : Operand<i64>;
254 def shamt : Operand<i32>;
257 def uimm16 : Operand<i32> {
258 let PrintMethod = "printUnsignedImm";
261 def MipsMemAsmOperand : AsmOperandClass {
263 let ParserMethod = "parseMemOperand";
267 def mem : Operand<i32> {
268 let PrintMethod = "printMemOperand";
269 let MIOperandInfo = (ops CPURegs, simm16);
270 let EncoderMethod = "getMemEncoding";
271 let ParserMatchClass = MipsMemAsmOperand;
272 let OperandType = "OPERAND_MEMORY";
275 def mem64 : Operand<i64> {
276 let PrintMethod = "printMemOperand";
277 let MIOperandInfo = (ops CPU64Regs, simm16_64);
278 let EncoderMethod = "getMemEncoding";
279 let ParserMatchClass = MipsMemAsmOperand;
280 let OperandType = "OPERAND_MEMORY";
283 def mem_ea : Operand<i32> {
284 let PrintMethod = "printMemOperandEA";
285 let MIOperandInfo = (ops CPURegs, simm16);
286 let EncoderMethod = "getMemEncoding";
287 let OperandType = "OPERAND_MEMORY";
290 def mem_ea_64 : Operand<i64> {
291 let PrintMethod = "printMemOperandEA";
292 let MIOperandInfo = (ops CPU64Regs, simm16_64);
293 let EncoderMethod = "getMemEncoding";
294 let OperandType = "OPERAND_MEMORY";
297 // size operand of ext instruction
298 def size_ext : Operand<i32> {
299 let EncoderMethod = "getSizeExtEncoding";
300 let DecoderMethod = "DecodeExtSize";
303 // size operand of ins instruction
304 def size_ins : Operand<i32> {
305 let EncoderMethod = "getSizeInsEncoding";
306 let DecoderMethod = "DecodeInsSize";
309 // Transformation Function - get the lower 16 bits.
310 def LO16 : SDNodeXForm<imm, [{
311 return getImm(N, N->getZExtValue() & 0xFFFF);
314 // Transformation Function - get the higher 16 bits.
315 def HI16 : SDNodeXForm<imm, [{
316 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
320 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
322 // Node immediate fits as 16-bit sign extended on target immediate.
324 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
326 // Node immediate fits as 16-bit sign extended on target immediate.
328 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
330 // Node immediate fits as 15-bit sign extended on target immediate.
332 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
334 // Node immediate fits as 16-bit zero extended on target immediate.
335 // The LO16 param means that only the lower 16 bits of the node
336 // immediate are caught.
338 def immZExt16 : PatLeaf<(imm), [{
339 if (N->getValueType(0) == MVT::i32)
340 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
342 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
345 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
346 def immLow16Zero : PatLeaf<(imm), [{
347 int64_t Val = N->getSExtValue();
348 return isInt<32>(Val) && !(Val & 0xffff);
351 // shamt field must fit in 5 bits.
352 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
354 // True if (N + 1) fits in 16-bit field.
355 def immSExt16Plus1 : PatLeaf<(imm), [{
356 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
359 // Mips Address Mode! SDNode frameindex could possibily be a match
360 // since load and store instructions from stack used it.
362 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
365 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
368 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
370 //===----------------------------------------------------------------------===//
371 // Instructions specific format
372 //===----------------------------------------------------------------------===//
374 // Arithmetic and logical instructions with 3 register operands.
375 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
376 InstrItinClass Itin = NoItinerary,
377 SDPatternOperator OpNode = null_frag>:
378 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
379 !strconcat(opstr, "\t$rd, $rs, $rt"),
380 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
381 let isCommutable = isComm;
382 let isReMaterializable = 1;
385 // Arithmetic and logical instructions with 2 register operands.
386 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
387 SDPatternOperator imm_type = null_frag,
388 SDPatternOperator OpNode = null_frag> :
389 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
390 !strconcat(opstr, "\t$rt, $rs, $imm16"),
391 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
392 IIAlu, FrmI, opstr> {
393 let isReMaterializable = 1;
396 // Arithmetic Multiply ADD/SUB
397 class MArithR<string opstr, bit isComm = 0> :
398 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
399 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> {
402 let isCommutable = isComm;
406 class LogicNOR<string opstr, RegisterOperand RC>:
407 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
408 !strconcat(opstr, "\t$rd, $rs, $rt"),
409 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> {
410 let isCommutable = 1;
414 class shift_rotate_imm<string opstr, Operand ImmOpnd,
415 RegisterOperand RC, SDPatternOperator OpNode = null_frag,
416 SDPatternOperator PF = null_frag> :
417 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
418 !strconcat(opstr, "\t$rd, $rt, $shamt"),
419 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>;
421 class shift_rotate_reg<string opstr, RegisterOperand RC,
422 SDPatternOperator OpNode = null_frag>:
423 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt),
424 !strconcat(opstr, "\t$rd, $rt, $rs"),
425 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>;
427 // Load Upper Imediate
428 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
429 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
430 [], IIAlu, FrmI>, IsAsCheapAsAMove {
431 let neverHasSideEffects = 1;
432 let isReMaterializable = 1;
435 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
436 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
438 let Inst{25-21} = addr{20-16};
439 let Inst{15-0} = addr{15-0};
440 let DecoderMethod = "DecodeMem";
444 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
445 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
446 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
447 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
448 !strconcat(opstr, ofsuffix)> {
449 let DecoderMethod = "DecodeMem";
450 let canFoldAsLoad = 1;
454 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
455 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
456 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
457 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI,
458 !strconcat(opstr, ofsuffix)> {
459 let DecoderMethod = "DecodeMem";
463 multiclass LoadM<string opstr, RegisterClass RC,
464 SDPatternOperator OpNode = null_frag,
465 ComplexPattern Addr = addr> {
466 def NAME : Load<opstr, OpNode, RC, mem, Addr, "">,
467 Requires<[NotN64, HasStdEnc]>;
468 def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">,
469 Requires<[IsN64, HasStdEnc]> {
470 let DecoderNamespace = "Mips64";
471 let isCodeGenOnly = 1;
475 multiclass StoreM<string opstr, RegisterClass RC,
476 SDPatternOperator OpNode = null_frag,
477 ComplexPattern Addr = addr> {
478 def NAME : Store<opstr, OpNode, RC, mem, Addr, "">,
479 Requires<[NotN64, HasStdEnc]>;
480 def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">,
481 Requires<[IsN64, HasStdEnc]> {
482 let DecoderNamespace = "Mips64";
483 let isCodeGenOnly = 1;
487 // Load/Store Left/Right
488 let canFoldAsLoad = 1 in
489 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
491 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
492 !strconcat(opstr, "\t$rt, $addr"),
493 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
494 let DecoderMethod = "DecodeMem";
495 string Constraints = "$src = $rt";
498 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
500 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
501 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
502 let DecoderMethod = "DecodeMem";
505 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
506 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
507 Requires<[NotN64, HasStdEnc]>;
508 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
509 Requires<[IsN64, HasStdEnc]> {
510 let DecoderNamespace = "Mips64";
511 let isCodeGenOnly = 1;
515 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
516 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
517 Requires<[NotN64, HasStdEnc]>;
518 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
519 Requires<[IsN64, HasStdEnc]> {
520 let DecoderNamespace = "Mips64";
521 let isCodeGenOnly = 1;
525 // Conditional Branch
526 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> :
527 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
528 !strconcat(opstr, "\t$rs, $rt, $offset"),
529 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
532 let isTerminator = 1;
533 let hasDelaySlot = 1;
537 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> :
538 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
539 !strconcat(opstr, "\t$rs, $offset"),
540 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
542 let isTerminator = 1;
543 let hasDelaySlot = 1;
548 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
549 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
550 !strconcat(opstr, "\t$rd, $rs, $rt"),
551 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))],
554 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
556 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
557 !strconcat(opstr, "\t$rt, $rs, $imm16"),
558 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
562 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
563 SDPatternOperator targetoperator> :
564 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
565 [(operator targetoperator:$target)], IIBranch, FrmJ> {
568 let hasDelaySlot = 1;
569 let DecoderMethod = "DecodeJumpTarget";
573 // Unconditional branch
574 class UncondBranch<string opstr> :
575 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
576 [(br bb:$offset)], IIBranch, FrmI> {
578 let isTerminator = 1;
580 let hasDelaySlot = 1;
581 let Predicates = [RelocPIC, HasStdEnc];
585 // Base class for indirect branch and return instruction classes.
586 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
587 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
588 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
591 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
593 let isIndirectBranch = 1;
596 // Return instruction
597 class RetBase<RegisterClass RC>: JumpFR<RC> {
599 let isCodeGenOnly = 1;
601 let hasExtraSrcRegAllocReq = 1;
604 // Jump and Link (Call)
605 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
606 class JumpLink<string opstr> :
607 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
608 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
609 let DecoderMethod = "DecodeJumpTarget";
612 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst,
614 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>,
615 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>;
617 class JumpLinkReg<string opstr, RegisterClass RC>:
618 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
621 class BGEZAL_FT<string opstr, RegisterOperand RO> :
622 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
623 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
628 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> {
630 let isTerminator = 1;
632 let hasDelaySlot = 1;
637 let hasSideEffects = 1 in
639 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
640 NoItinerary, FrmOther>;
643 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
644 list<Register> DefRegs> :
645 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
647 let isCommutable = 1;
649 let neverHasSideEffects = 1;
652 // Pseudo multiply/divide instruction with explicit accumulator register
654 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
655 SDPatternOperator OpNode, InstrItinClass Itin,
656 bit IsComm = 1, bit HasSideEffects = 0> :
657 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
658 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
659 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
660 let isCommutable = IsComm;
661 let hasSideEffects = HasSideEffects;
664 // Pseudo multiply add/sub instruction with explicit accumulator register
666 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
667 : PseudoSE<(outs ACRegs:$ac),
668 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin),
670 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))],
672 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> {
673 string Constraints = "$acin = $ac";
676 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
677 list<Register> DefRegs> :
678 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
684 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
685 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
687 let neverHasSideEffects = 1;
690 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
691 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
693 let neverHasSideEffects = 1;
696 class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
697 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
698 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
699 let isCodeGenOnly = 1;
700 let DecoderMethod = "DecodeMem";
703 // Count Leading Ones/Zeros in Word
704 class CountLeading0<string opstr, RegisterOperand RO>:
705 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
706 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>,
707 Requires<[HasBitCount, HasStdEnc]>;
709 class CountLeading1<string opstr, RegisterOperand RO>:
710 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
711 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>,
712 Requires<[HasBitCount, HasStdEnc]>;
715 // Sign Extend in Register.
716 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
717 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
718 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
719 let Predicates = [HasSEInReg, HasStdEnc];
723 class SubwordSwap<string opstr, RegisterOperand RO>:
724 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
726 let Predicates = [HasSwap, HasStdEnc];
727 let neverHasSideEffects = 1;
731 class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
732 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
736 class ExtBase<string opstr, RegisterOperand RO>:
737 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
738 !strconcat(opstr, " $rt, $rs, $pos, $size"),
739 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
741 let Predicates = [HasMips32r2, HasStdEnc];
744 class InsBase<string opstr, RegisterOperand RO>:
745 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
746 !strconcat(opstr, " $rt, $rs, $pos, $size"),
747 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
749 let Predicates = [HasMips32r2, HasStdEnc];
750 let Constraints = "$src = $rt";
753 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
754 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
755 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
756 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
758 multiclass Atomic2Ops32<PatFrag Op> {
759 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
760 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
761 Requires<[IsN64, HasStdEnc]> {
762 let DecoderNamespace = "Mips64";
766 // Atomic Compare & Swap.
767 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
768 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
769 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
771 multiclass AtomicCmpSwap32<PatFrag Op> {
772 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
773 Requires<[NotN64, HasStdEnc]>;
774 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
775 Requires<[IsN64, HasStdEnc]> {
776 let DecoderNamespace = "Mips64";
780 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
781 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
782 [], NoItinerary, FrmI> {
783 let DecoderMethod = "DecodeMem";
787 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
788 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
789 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
790 let DecoderMethod = "DecodeMem";
792 let Constraints = "$rt = $dst";
795 class MFC3OP<dag outs, dag ins, string asmstr> :
796 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
798 //===----------------------------------------------------------------------===//
799 // Pseudo instructions
800 //===----------------------------------------------------------------------===//
803 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
804 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
806 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
807 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
808 [(callseq_start timm:$amt)]>;
809 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
810 [(callseq_end timm:$amt1, timm:$amt2)]>;
813 let usesCustomInserter = 1 in {
814 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
815 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
816 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
817 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
818 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
819 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
820 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
821 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
822 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
823 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
824 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
825 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
826 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
827 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
828 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
829 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
830 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
831 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
833 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
834 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
835 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
837 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
838 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
839 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
842 /// Pseudo instructions for loading and storing accumulator registers.
843 let isPseudo = 1 in {
844 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>;
845 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>;
848 //===----------------------------------------------------------------------===//
849 // Instruction definition
850 //===----------------------------------------------------------------------===//
851 //===----------------------------------------------------------------------===//
852 // MipsI Instructions
853 //===----------------------------------------------------------------------===//
855 /// Arithmetic Instructions (ALU Immediate)
856 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
857 ADDI_FM<0x9>, IsAsCheapAsAMove;
858 def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
859 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
861 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
863 def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
865 def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
867 def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
869 def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
871 /// Arithmetic Instructions (3-Operand, R-Type)
872 def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>,
874 def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>,
876 def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
878 def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
879 def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
880 def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
881 def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
882 def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
884 def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>,
886 def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>,
888 def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
890 /// Shift Instructions
891 def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
893 def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
895 def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
897 def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
898 def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
899 def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
901 // Rotate Instructions
902 let Predicates = [HasMips32r2, HasStdEnc] in {
903 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr,
906 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>,
910 /// Load and Store Instructions
912 defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>;
913 defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>;
914 defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>;
915 defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>;
916 defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>;
917 defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>;
918 defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>;
919 defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>;
921 /// load/store left/right
922 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
923 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
924 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
925 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
927 def SYNC : SYNC_FT, SYNC_FM;
929 /// Load-linked, Store-conditional
930 let Predicates = [NotN64, HasStdEnc] in {
931 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
932 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>;
935 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
936 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>;
937 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>;
940 /// Jump and Branch Instructions
941 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
942 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
943 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
944 def B : UncondBranch<"b">, B_FM;
945 def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>;
946 def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>;
947 def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>;
948 def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>;
949 def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>;
950 def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>;
952 def BAL_BR: BAL_FT, BAL_FM;
954 def JAL : JumpLink<"jal">, FJ<3>;
955 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
956 def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>;
957 def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
958 def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
959 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
960 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
962 def RET : RetBase<CPURegs>, MTLO_FM<8>;
964 // Exception handling related node and instructions.
965 // The conversion sequence is:
966 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
967 // MIPSeh_return -> (stack change + indirect branch)
969 // MIPSeh_return takes the place of regular return instruction
970 // but takes two arguments (V1, V0) which are used for storing
971 // the offset and return address respectively.
972 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
974 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
975 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
977 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
978 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst),
979 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>;
980 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff,
982 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>;
985 /// Multiply and Divide Instructions.
986 def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>,
988 def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>,
990 def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>;
991 def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>;
992 def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
993 def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>;
994 def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv,
996 def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv,
999 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
1000 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
1001 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
1002 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
1004 /// Sign Ext In Register Instructions.
1005 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
1006 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
1009 def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
1010 def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>;
1012 /// Word Swap Bytes Within Halfwords
1013 def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>;
1016 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1018 // FrameIndexes are legalized when they are operands from load/store
1019 // instructions. The same not happens for stack address copies, so an
1020 // add op with mem ComplexPattern is used and the stack address copy
1021 // can be matched. It's similar to Sparc LEA_ADDRi
1022 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
1025 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1026 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1027 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1028 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1029 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1030 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1031 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1032 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1034 def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
1036 def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
1037 def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
1039 /// Move Control Registers From/To CPU Registers
1040 def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1041 (ins CPURegsOpnd:$rd, uimm16:$sel),
1042 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
1044 def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1045 (ins CPURegsOpnd:$rt),
1046 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
1048 def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1049 (ins CPURegsOpnd:$rd, uimm16:$sel),
1050 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
1052 def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1053 (ins CPURegsOpnd:$rt),
1054 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
1056 //===----------------------------------------------------------------------===//
1057 // Instruction aliases
1058 //===----------------------------------------------------------------------===//
1059 def : InstAlias<"move $dst, $src",
1060 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1061 Requires<[NotMips64]>;
1062 def : InstAlias<"move $dst, $src",
1063 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1064 Requires<[NotMips64]>;
1065 def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
1066 def : InstAlias<"addu $rs, $rt, $imm",
1067 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1068 def : InstAlias<"add $rs, $rt, $imm",
1069 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1070 def : InstAlias<"and $rs, $rt, $imm",
1071 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1072 def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
1073 Requires<[NotMips64]>;
1074 def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>;
1075 def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>;
1076 def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>,
1077 Requires<[NotMips64]>;
1078 def : InstAlias<"not $rt, $rs",
1079 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
1080 def : InstAlias<"neg $rt, $rs",
1081 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1082 def : InstAlias<"negu $rt, $rs",
1083 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1084 def : InstAlias<"slt $rs, $rt, $imm",
1085 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
1086 def : InstAlias<"xor $rs, $rt, $imm",
1087 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1088 Requires<[NotMips64]>;
1089 def : InstAlias<"or $rs, $rt, $imm",
1090 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1091 Requires<[NotMips64]>;
1092 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1093 def : InstAlias<"mfc0 $rt, $rd",
1094 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1095 def : InstAlias<"mtc0 $rt, $rd",
1096 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1097 def : InstAlias<"mfc2 $rt, $rd",
1098 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1099 def : InstAlias<"mtc2 $rt, $rd",
1100 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1101 def : InstAlias<"addiu $rs, $imm",
1102 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rs, simm16:$imm), 0>;
1103 def : InstAlias<"bnez $rs,$offset",
1104 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1105 Requires<[NotMips64]>;
1106 def : InstAlias<"beqz $rs,$offset",
1107 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1108 Requires<[NotMips64]>;
1109 //===----------------------------------------------------------------------===//
1110 // Assembler Pseudo Instructions
1111 //===----------------------------------------------------------------------===//
1113 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1114 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1115 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1116 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>;
1118 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1119 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1120 !strconcat(instr_asm, "\t$rt, $addr")> ;
1121 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>;
1123 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1124 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1125 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1126 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>;
1130 //===----------------------------------------------------------------------===//
1131 // Arbitrary patterns that map to one or more instructions
1132 //===----------------------------------------------------------------------===//
1134 // Load/store pattern templates.
1135 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1136 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1138 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1139 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1142 def : MipsPat<(i32 immSExt16:$in),
1143 (ADDiu ZERO, imm:$in)>;
1144 def : MipsPat<(i32 immZExt16:$in),
1145 (ORi ZERO, imm:$in)>;
1146 def : MipsPat<(i32 immLow16Zero:$in),
1147 (LUi (HI16 imm:$in))>;
1149 // Arbitrary immediates
1150 def : MipsPat<(i32 imm:$imm),
1151 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1153 // Carry MipsPatterns
1154 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1155 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1156 let Predicates = [HasStdEnc, NotDSP] in {
1157 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1158 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1159 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1160 (ADDiu CPURegs:$src, imm:$imm)>;
1164 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1165 (JAL tglobaladdr:$dst)>;
1166 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1167 (JAL texternalsym:$dst)>;
1168 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1169 // (JALR CPURegs:$dst)>;
1172 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1173 (TAILCALL tglobaladdr:$dst)>;
1174 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1175 (TAILCALL texternalsym:$dst)>;
1177 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1178 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1179 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1180 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1181 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1182 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1184 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1185 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1186 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1187 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1188 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1189 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1191 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1192 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1193 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1194 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1195 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1196 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1197 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1198 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1199 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1200 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1203 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1204 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1205 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1206 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1209 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1210 MipsPat<(MipsWrapper RC:$gp, node:$in),
1211 (ADDiuOp RC:$gp, node:$in)>;
1213 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1214 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1215 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1216 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1217 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1218 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1220 // Mips does not have "not", so we expand our way
1221 def : MipsPat<(not CPURegs:$in),
1222 (NOR CPURegsOpnd:$in, ZERO)>;
1225 let Predicates = [NotN64, HasStdEnc] in {
1226 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1227 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1228 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1230 let Predicates = [IsN64, HasStdEnc] in {
1231 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1232 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1233 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1237 let Predicates = [NotN64, HasStdEnc] in {
1238 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1240 let Predicates = [IsN64, HasStdEnc] in {
1241 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1245 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1246 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1247 Instruction SLTiuOp, Register ZEROReg> {
1248 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1249 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1250 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1251 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1253 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1254 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1255 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1256 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1257 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1258 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1259 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1260 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1262 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1263 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1264 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1265 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1267 def : MipsPat<(brcond RC:$cond, bb:$dst),
1268 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1271 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1274 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1275 Instruction SLTuOp, Register ZEROReg> {
1276 def : MipsPat<(seteq RC:$lhs, 0),
1277 (SLTiuOp RC:$lhs, 1)>;
1278 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1279 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1280 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1281 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1284 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1285 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1286 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1287 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1288 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1291 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1292 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1293 (SLTOp RC:$rhs, RC:$lhs)>;
1294 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1295 (SLTuOp RC:$rhs, RC:$lhs)>;
1298 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1299 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1300 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1301 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1302 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1305 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1306 Instruction SLTiuOp> {
1307 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1308 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1309 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1310 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1313 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1314 defm : SetlePats<CPURegs, SLT, SLTu>;
1315 defm : SetgtPats<CPURegs, SLT, SLTu>;
1316 defm : SetgePats<CPURegs, SLT, SLTu>;
1317 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1320 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1322 // mflo/hi patterns.
1323 def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
1324 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
1326 // Load halfword/word patterns.
1327 let AddedComplexity = 40 in {
1328 let Predicates = [NotN64, HasStdEnc] in {
1329 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1330 def : LoadRegImmPat<LH, i32, sextloadi16>;
1331 def : LoadRegImmPat<LW, i32, load>;
1333 let Predicates = [IsN64, HasStdEnc] in {
1334 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>;
1335 def : LoadRegImmPat<LH_P8, i32, sextloadi16>;
1336 def : LoadRegImmPat<LW_P8, i32, load>;
1340 //===----------------------------------------------------------------------===//
1341 // Floating Point Support
1342 //===----------------------------------------------------------------------===//
1344 include "MipsInstrFPU.td"
1345 include "Mips64InstrInfo.td"
1346 include "MipsCondMov.td"
1351 include "Mips16InstrFormats.td"
1352 include "Mips16InstrInfo.td"
1355 include "MipsDSPInstrFormats.td"
1356 include "MipsDSPInstrInfo.td"
1359 include "MicroMipsInstrFormats.td"
1360 include "MicroMipsInstrInfo.td"