1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "MipsInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Mips profiles and nodes
22 //===----------------------------------------------------------------------===//
24 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
25 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
30 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
31 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
32 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
33 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def SDT_MipsDivRem : SDTypeProfile<0, 2,
40 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
42 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
44 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
46 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
47 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
48 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
49 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
112 // Pointer to dynamically allocated stack area.
113 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
114 [SDNPHasChain, SDNPInGlue]>;
116 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
118 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
119 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
121 //===----------------------------------------------------------------------===//
122 // Mips Instruction Predicate Definitions.
123 //===----------------------------------------------------------------------===//
124 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
125 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
126 def HasSwap : Predicate<"Subtarget.hasSwap()">;
127 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
128 def HasMips32 : Predicate<"Subtarget.hasMips32()">;
129 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
130 def HasMips64 : Predicate<"Subtarget.hasMips64()">;
131 def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
132 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
133 def IsN64 : Predicate<"Subtarget.isABI_N64()">;
134 def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
135 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
136 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
138 //===----------------------------------------------------------------------===//
139 // Mips Operand, Complex Patterns and Transformations Definitions.
140 //===----------------------------------------------------------------------===//
142 // Instruction operand types
143 def jmptarget : Operand<OtherVT> {
144 let EncoderMethod = "getJumpTargetOpValue";
146 def brtarget : Operand<OtherVT> {
147 let EncoderMethod = "getBranchTargetOpValue";
148 let OperandType = "OPERAND_PCREL";
150 def calltarget : Operand<iPTR> {
151 let EncoderMethod = "getJumpTargetOpValue";
153 def calltarget64: Operand<i64>;
154 def simm16 : Operand<i32>;
155 def simm16_64 : Operand<i64>;
156 def shamt : Operand<i32>;
159 def uimm16 : Operand<i32> {
160 let PrintMethod = "printUnsignedImm";
164 def mem : Operand<i32> {
165 let PrintMethod = "printMemOperand";
166 let MIOperandInfo = (ops CPURegs, simm16);
167 let EncoderMethod = "getMemEncoding";
170 def mem64 : Operand<i64> {
171 let PrintMethod = "printMemOperand";
172 let MIOperandInfo = (ops CPU64Regs, simm16_64);
175 def mem_ea : Operand<i32> {
176 let PrintMethod = "printMemOperandEA";
177 let MIOperandInfo = (ops CPURegs, simm16);
178 let EncoderMethod = "getMemEncoding";
181 def mem_ea_64 : Operand<i64> {
182 let PrintMethod = "printMemOperandEA";
183 let MIOperandInfo = (ops CPU64Regs, simm16_64);
184 let EncoderMethod = "getMemEncoding";
187 // size operand of ext instruction
188 def size_ext : Operand<i32> {
189 let EncoderMethod = "getSizeExtEncoding";
192 // size operand of ins instruction
193 def size_ins : Operand<i32> {
194 let EncoderMethod = "getSizeInsEncoding";
197 // Transformation Function - get the lower 16 bits.
198 def LO16 : SDNodeXForm<imm, [{
199 return getImm(N, N->getZExtValue() & 0xFFFF);
202 // Transformation Function - get the higher 16 bits.
203 def HI16 : SDNodeXForm<imm, [{
204 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
207 // Node immediate fits as 16-bit sign extended on target immediate.
209 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
211 // Node immediate fits as 16-bit zero extended on target immediate.
212 // The LO16 param means that only the lower 16 bits of the node
213 // immediate are caught.
215 def immZExt16 : PatLeaf<(imm), [{
216 if (N->getValueType(0) == MVT::i32)
217 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
219 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
222 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
223 def immLow16Zero : PatLeaf<(imm), [{
224 int64_t Val = N->getSExtValue();
225 return isInt<32>(Val) && !(Val & 0xffff);
228 // shamt field must fit in 5 bits.
229 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
231 // Mips Address Mode! SDNode frameindex could possibily be a match
232 // since load and store instructions from stack used it.
233 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
235 //===----------------------------------------------------------------------===//
236 // Pattern fragment for load/store
237 //===----------------------------------------------------------------------===//
238 class UnalignedLoad<PatFrag Node> :
239 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
240 LoadSDNode *LD = cast<LoadSDNode>(N);
241 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
244 class AlignedLoad<PatFrag Node> :
245 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
246 LoadSDNode *LD = cast<LoadSDNode>(N);
247 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
250 class UnalignedStore<PatFrag Node> :
251 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
252 StoreSDNode *SD = cast<StoreSDNode>(N);
253 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
256 class AlignedStore<PatFrag Node> :
257 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
258 StoreSDNode *SD = cast<StoreSDNode>(N);
259 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
262 // Load/Store PatFrags.
263 def sextloadi16_a : AlignedLoad<sextloadi16>;
264 def zextloadi16_a : AlignedLoad<zextloadi16>;
265 def extloadi16_a : AlignedLoad<extloadi16>;
266 def load_a : AlignedLoad<load>;
267 def sextloadi32_a : AlignedLoad<sextloadi32>;
268 def zextloadi32_a : AlignedLoad<zextloadi32>;
269 def extloadi32_a : AlignedLoad<extloadi32>;
270 def truncstorei16_a : AlignedStore<truncstorei16>;
271 def store_a : AlignedStore<store>;
272 def truncstorei32_a : AlignedStore<truncstorei32>;
273 def sextloadi16_u : UnalignedLoad<sextloadi16>;
274 def zextloadi16_u : UnalignedLoad<zextloadi16>;
275 def extloadi16_u : UnalignedLoad<extloadi16>;
276 def load_u : UnalignedLoad<load>;
277 def sextloadi32_u : UnalignedLoad<sextloadi32>;
278 def zextloadi32_u : UnalignedLoad<zextloadi32>;
279 def extloadi32_u : UnalignedLoad<extloadi32>;
280 def truncstorei16_u : UnalignedStore<truncstorei16>;
281 def store_u : UnalignedStore<store>;
282 def truncstorei32_u : UnalignedStore<truncstorei32>;
284 //===----------------------------------------------------------------------===//
285 // Instructions specific format
286 //===----------------------------------------------------------------------===//
288 // Arithmetic and logical instructions with 3 register operands.
289 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
290 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
291 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
292 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
293 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
295 let isCommutable = isComm;
298 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
299 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
300 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
301 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
303 let isCommutable = isComm;
306 // Arithmetic and logical instructions with 2 register operands.
307 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
308 Operand Od, PatLeaf imm_type, RegisterClass RC> :
309 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
310 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
311 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
313 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
314 Operand Od, PatLeaf imm_type, RegisterClass RC> :
315 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
316 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
318 // Arithmetic Multiply ADD/SUB
319 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
320 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
321 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
322 !strconcat(instr_asm, "\t$rs, $rt"),
323 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
326 let isCommutable = isComm;
330 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
331 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
332 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
333 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
335 let isCommutable = 1;
339 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
340 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
342 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
343 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
344 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
348 // 32-bit shift instructions.
349 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
351 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
353 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
354 SDNode OpNode, RegisterClass RC>:
355 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
356 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
357 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
358 let shamt = isRotate;
361 // Load Upper Imediate
362 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
363 FI<op, (outs RC:$rt), (ins Imm:$imm16),
364 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
368 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
369 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
371 let Inst{25-21} = addr{20-16};
372 let Inst{15-0} = addr{15-0};
376 let canFoldAsLoad = 1 in
377 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
378 Operand MemOpnd, bit Pseudo>:
379 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
380 !strconcat(instr_asm, "\t$rt, $addr"),
381 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
382 let isPseudo = Pseudo;
385 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
386 Operand MemOpnd, bit Pseudo>:
387 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
388 !strconcat(instr_asm, "\t$rt, $addr"),
389 [(OpNode RC:$rt, addr:$addr)], IIStore> {
390 let isPseudo = Pseudo;
393 // Unaligned Memory Load/Store
394 let canFoldAsLoad = 1 in
395 class LoadUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
396 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), "", [], IILoad> {}
398 class StoreUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
399 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), "", [], IIStore> {}
402 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
404 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
406 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
411 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
413 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
415 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
420 multiclass LoadUnAlign32<bits<6> op> {
421 def #NAME# : LoadUnAlign<op, CPURegs, mem>,
423 def _P8 : LoadUnAlign<op, CPURegs, mem64>,
427 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
429 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
431 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
436 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
438 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
440 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
445 multiclass StoreUnAlign32<bits<6> op> {
446 def #NAME# : StoreUnAlign<op, CPURegs, mem>,
448 def _P8 : StoreUnAlign<op, CPURegs, mem64>,
452 // Conditional Branch
453 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
454 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
455 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
456 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
458 let isTerminator = 1;
459 let hasDelaySlot = 1;
462 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
464 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
465 !strconcat(instr_asm, "\t$rs, $imm16"),
466 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
469 let isTerminator = 1;
470 let hasDelaySlot = 1;
474 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
476 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
477 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
478 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
483 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
484 PatLeaf imm_type, RegisterClass RC>:
485 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
486 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
487 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
491 class JumpFJ<bits<6> op, string instr_asm>:
492 FJ<op, (outs), (ins jmptarget:$target),
493 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> {
497 let hasDelaySlot = 1;
498 let Predicates = [RelocStatic];
501 // Unconditional branch
502 class UncondBranch<bits<6> op, string instr_asm>:
503 BranchBase<op, (outs), (ins brtarget:$imm16),
504 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
508 let isTerminator = 1;
510 let hasDelaySlot = 1;
511 let Predicates = [RelocPIC];
514 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
515 isIndirectBranch = 1 in
516 class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
517 FR<op, func, (outs), (ins RC:$rs),
518 !strconcat(instr_asm, "\t$rs"), [(brind RC:$rs)], IIBranch> {
524 // Jump and Link (Call)
525 let isCall=1, hasDelaySlot=1 in {
526 class JumpLink<bits<6> op, string instr_asm>:
527 FJ<op, (outs), (ins calltarget:$target, variable_ops),
528 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
531 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
533 FR<op, func, (outs), (ins RC:$rs, variable_ops),
534 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
540 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
541 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops),
542 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
548 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
549 RegisterClass RC, list<Register> DefRegs>:
550 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
551 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
554 let isCommutable = 1;
558 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
559 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
561 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
562 RegisterClass RC, list<Register> DefRegs>:
563 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
564 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
565 [(op RC:$rs, RC:$rt)], itin> {
571 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
572 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
575 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
576 list<Register> UseRegs>:
577 FR<0x00, func, (outs RC:$rd), (ins),
578 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
585 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
586 list<Register> DefRegs>:
587 FR<0x00, func, (outs), (ins RC:$rs),
588 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
595 class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
596 FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
597 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
599 // Count Leading Ones/Zeros in Word
600 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
601 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
602 !strconcat(instr_asm, "\t$rd, $rs"),
603 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
604 Requires<[HasBitCount]> {
609 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
610 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
611 !strconcat(instr_asm, "\t$rd, $rs"),
612 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
613 Requires<[HasBitCount]> {
618 // Sign Extend in Register.
619 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
621 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
622 !strconcat(instr_asm, "\t$rd, $rt"),
623 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
626 let Predicates = [HasSEInReg];
630 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
631 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
632 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
635 let Predicates = [HasSwap];
639 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
640 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
641 "rdhwr\t$rt, $rd", [], IIAlu> {
647 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
648 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
649 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
650 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
655 let Predicates = [HasMips32r2];
658 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
659 FR<0x1f, _funct, (outs RC:$rt),
660 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
661 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
662 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
668 let Predicates = [HasMips32r2];
669 let Constraints = "$src = $rt";
672 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
673 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
675 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
676 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
677 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
679 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
680 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, Requires<[NotN64]>;
681 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, Requires<[IsN64]>;
684 // Atomic Compare & Swap.
685 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
687 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
688 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
689 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
691 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
692 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, Requires<[NotN64]>;
693 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, Requires<[IsN64]>;
696 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
697 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
698 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
702 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
703 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
704 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
706 let Constraints = "$rt = $dst";
709 //===----------------------------------------------------------------------===//
710 // Pseudo instructions
711 //===----------------------------------------------------------------------===//
713 // As stack alignment is always done with addiu, we need a 16-bit immediate
714 let Defs = [SP], Uses = [SP] in {
715 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
716 "!ADJCALLSTACKDOWN $amt",
717 [(callseq_start timm:$amt)]>;
718 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
719 "!ADJCALLSTACKUP $amt1",
720 [(callseq_end timm:$amt1, timm:$amt2)]>;
723 // Some assembly macros need to avoid pseudoinstructions and assembler
724 // automatic reodering, we should reorder ourselves.
725 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
726 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
727 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
728 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
730 // These macros are inserted to prevent GAS from complaining
731 // when using the AT register.
732 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
733 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
735 // When handling PIC code the assembler needs .cpload and .cprestore
736 // directives. If the real instructions corresponding these directives
737 // are used, we have the same behavior, but get also a bunch of warnings
738 // from the assembler.
739 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
740 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
742 // For O32 ABI & PIC & non-fixed global base register, the following instruction
743 // seqeunce is emitted to set the global base register:
745 // 0. lui $2, %hi(_gp_disp)
746 // 1. addiu $2, $2, %lo(_gp_disp)
747 // 2. addu $globalbasereg, $2, $t9
749 // SETGP01 is emitted during Prologue/Epilogue insertion and then converted to
750 // instructions 0 and 1 in the sequence above during MC lowering.
751 // SETGP2 is emitted just before register allocation and converted to
752 // instruction 2 just prior to post-RA scheduling.
754 def SETGP01 : MipsPseudo<(outs CPURegs:$dst), (ins), "", []>;
755 def SETGP2 : MipsPseudo<(outs CPURegs:$globalreg), (ins CPURegs:$picreg), "",
758 let usesCustomInserter = 1 in {
759 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
760 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
761 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
762 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
763 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
764 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
765 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
766 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
767 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
768 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
769 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
770 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
771 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
772 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
773 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
774 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
775 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
776 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
778 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
779 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
780 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
782 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
783 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
784 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
787 //===----------------------------------------------------------------------===//
788 // Instruction definition
789 //===----------------------------------------------------------------------===//
791 //===----------------------------------------------------------------------===//
792 // MipsI Instructions
793 //===----------------------------------------------------------------------===//
795 /// Arithmetic Instructions (ALU Immediate)
796 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
797 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
798 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
799 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
800 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
801 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
802 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
803 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
805 /// Arithmetic Instructions (3-Operand, R-Type)
806 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
807 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
808 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
809 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
810 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
811 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
812 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
813 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
814 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
815 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
817 /// Shift Instructions
818 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
819 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
820 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
821 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
822 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
823 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
825 // Rotate Instructions
826 let Predicates = [HasMips32r2] in {
827 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
828 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
831 /// Load and Store Instructions
833 defm LB : LoadM32<0x20, "lb", sextloadi8>;
834 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
835 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
836 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
837 defm LW : LoadM32<0x23, "lw", load_a>;
838 defm SB : StoreM32<0x28, "sb", truncstorei8>;
839 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
840 defm SW : StoreM32<0x2b, "sw", store_a>;
843 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
844 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
845 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
846 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
847 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
849 /// Primitives for unaligned
850 defm LWL : LoadUnAlign32<0x22>;
851 defm LWR : LoadUnAlign32<0x26>;
852 defm SWL : StoreUnAlign32<0x2A>;
853 defm SWR : StoreUnAlign32<0x2E>;
855 let hasSideEffects = 1 in
856 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
857 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
862 let Inst{10-6} = stype;
866 /// Load-linked, Store-conditional
867 def LL : LLBase<0x30, "ll", CPURegs, mem>, Requires<[NotN64]>;
868 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]>;
869 def SC : SCBase<0x38, "sc", CPURegs, mem>, Requires<[NotN64]>;
870 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>;
872 /// Jump and Branch Instructions
873 def J : JumpFJ<0x02, "j">;
874 def JR : JumpFR<0x00, 0x08, "jr", CPURegs>;
875 def B : UncondBranch<0x04, "b">;
876 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
877 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
878 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
879 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
880 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
881 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
883 // All calls clobber the non-callee saved registers...
884 let Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
885 K0, K1, GP, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9] in {
886 def JAL : JumpLink<0x03, "jal">;
887 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
888 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
889 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
892 let isReturn=1, isTerminator=1, hasDelaySlot=1,
893 isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
894 def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
895 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
897 /// Multiply and Divide Instructions.
898 def MULT : Mult32<0x18, "mult", IIImul>;
899 def MULTu : Mult32<0x19, "multu", IIImul>;
900 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
901 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
903 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
904 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
905 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
906 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
908 /// Sign Ext In Register Instructions.
909 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
910 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
913 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
914 def CLO : CountLeading1<0x21, "clo", CPURegs>;
916 /// Word Swap Bytes Within Halfwords
917 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
921 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
923 // FrameIndexes are legalized when they are operands from load/store
924 // instructions. The same not happens for stack address copies, so an
925 // add op with mem ComplexPattern is used and the stack address copy
926 // can be matched. It's similar to Sparc LEA_ADDRi
927 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
929 // DynAlloc node points to dynamically allocated stack space.
930 // $sp is added to the list of implicitly used registers to prevent dead code
931 // elimination from removing instructions that modify $sp.
933 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
936 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
937 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
938 def MSUB : MArithR<4, "msub", MipsMSub>;
939 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
941 // MUL is a assembly macro in the current used ISAs. In recent ISA's
942 // it is a real instruction.
943 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
944 Requires<[HasMips32]>;
946 def RDHWR : ReadHardware<CPURegs, HWRegs>;
948 def EXT : ExtBase<0, "ext", CPURegs>;
949 def INS : InsBase<4, "ins", CPURegs>;
951 //===----------------------------------------------------------------------===//
952 // Arbitrary patterns that map to one or more instructions
953 //===----------------------------------------------------------------------===//
956 def : Pat<(i32 immSExt16:$in),
957 (ADDiu ZERO, imm:$in)>;
958 def : Pat<(i32 immZExt16:$in),
959 (ORi ZERO, imm:$in)>;
960 def : Pat<(i32 immLow16Zero:$in),
961 (LUi (HI16 imm:$in))>;
963 // Arbitrary immediates
964 def : Pat<(i32 imm:$imm),
965 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
968 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
969 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
970 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
971 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
972 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
973 (ADDiu CPURegs:$src, imm:$imm)>;
976 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
977 (JAL tglobaladdr:$dst)>;
978 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
979 (JAL texternalsym:$dst)>;
980 //def : Pat<(MipsJmpLink CPURegs:$dst),
981 // (JALR CPURegs:$dst)>;
984 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
985 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
986 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
987 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
988 def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
990 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
991 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
992 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
993 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
994 def : Pat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
996 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
997 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
998 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
999 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1000 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1001 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1002 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1003 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1004 def : Pat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1005 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1008 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1009 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1010 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1011 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1014 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1015 Pat<(MipsWrapper RC:$gp, node:$in),
1016 (ADDiuOp RC:$gp, node:$in)>;
1018 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1019 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1020 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1021 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1022 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1023 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1025 // Mips does not have "not", so we expand our way
1026 def : Pat<(not CPURegs:$in),
1027 (NOR CPURegs:$in, ZERO)>;
1030 let Predicates = [NotN64] in {
1031 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1032 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1033 def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
1034 def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
1036 let Predicates = [IsN64] in {
1037 def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1038 def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1039 def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
1040 def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
1044 let Predicates = [NotN64] in {
1045 def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1046 def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
1048 let Predicates = [IsN64] in {
1049 def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1050 def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
1054 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1055 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1056 Instruction SLTiuOp, Register ZEROReg> {
1057 def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1058 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1059 def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1060 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1062 def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1063 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1064 def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1065 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1066 def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1067 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1068 def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1069 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1071 def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1072 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1073 def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1074 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1076 def : Pat<(brcond RC:$cond, bb:$dst),
1077 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1080 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1083 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1084 Instruction SLTuOp, Register ZEROReg> {
1085 def : Pat<(seteq RC:$lhs, RC:$rhs),
1086 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1087 def : Pat<(setne RC:$lhs, RC:$rhs),
1088 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1091 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1092 def : Pat<(setle RC:$lhs, RC:$rhs),
1093 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1094 def : Pat<(setule RC:$lhs, RC:$rhs),
1095 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1098 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1099 def : Pat<(setgt RC:$lhs, RC:$rhs),
1100 (SLTOp RC:$rhs, RC:$lhs)>;
1101 def : Pat<(setugt RC:$lhs, RC:$rhs),
1102 (SLTuOp RC:$rhs, RC:$lhs)>;
1105 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1106 def : Pat<(setge RC:$lhs, RC:$rhs),
1107 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1108 def : Pat<(setuge RC:$lhs, RC:$rhs),
1109 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1112 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1113 Instruction SLTiuOp> {
1114 def : Pat<(setge RC:$lhs, immSExt16:$rhs),
1115 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1116 def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
1117 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1120 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1121 defm : SetlePats<CPURegs, SLT, SLTu>;
1122 defm : SetgtPats<CPURegs, SLT, SLTu>;
1123 defm : SetgePats<CPURegs, SLT, SLTu>;
1124 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1126 // select MipsDynAlloc
1127 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1130 def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1132 //===----------------------------------------------------------------------===//
1133 // Floating Point Support
1134 //===----------------------------------------------------------------------===//
1136 include "MipsInstrFPU.td"
1137 include "Mips64InstrInfo.td"
1138 include "MipsCondMov.td"