1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
185 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
186 AssemblerPredicate<"FeatureMicroMips">;
187 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
188 AssemblerPredicate<"!FeatureMicroMips">;
189 def IsLE : Predicate<"Subtarget.isLittle()">;
190 def IsBE : Predicate<"!Subtarget.isLittle()">;
192 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
193 let Predicates = [HasStdEnc];
197 bit isCommutable = 1;
214 bit isTerminator = 1;
217 bit hasExtraSrcRegAllocReq = 1;
218 bit isCodeGenOnly = 1;
221 class IsAsCheapAsAMove {
222 bit isAsCheapAsAMove = 1;
225 class NeverHasSideEffects {
226 bit neverHasSideEffects = 1;
229 //===----------------------------------------------------------------------===//
230 // Instruction format superclass
231 //===----------------------------------------------------------------------===//
233 include "MipsInstrFormats.td"
235 //===----------------------------------------------------------------------===//
236 // Mips Operand, Complex Patterns and Transformations Definitions.
237 //===----------------------------------------------------------------------===//
239 // Instruction operand types
240 def jmptarget : Operand<OtherVT> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def brtarget : Operand<OtherVT> {
244 let EncoderMethod = "getBranchTargetOpValue";
245 let OperandType = "OPERAND_PCREL";
246 let DecoderMethod = "DecodeBranchTarget";
248 def calltarget : Operand<iPTR> {
249 let EncoderMethod = "getJumpTargetOpValue";
251 def calltarget64: Operand<i64>;
252 def simm16 : Operand<i32> {
253 let DecoderMethod= "DecodeSimm16";
256 def simm20 : Operand<i32> {
259 def uimm20 : Operand<i32> {
262 def uimm10 : Operand<i32> {
265 def simm16_64 : Operand<i64>;
266 def shamt : Operand<i32>;
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm16 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def MipsMemAsmOperand : AsmOperandClass {
279 let ParserMethod = "parseMemOperand";
283 def mem : Operand<iPTR> {
284 let PrintMethod = "printMemOperand";
285 let MIOperandInfo = (ops ptr_rc, simm16);
286 let EncoderMethod = "getMemEncoding";
287 let ParserMatchClass = MipsMemAsmOperand;
288 let OperandType = "OPERAND_MEMORY";
291 def mem_ea : Operand<iPTR> {
292 let PrintMethod = "printMemOperandEA";
293 let MIOperandInfo = (ops ptr_rc, simm16);
294 let EncoderMethod = "getMemEncoding";
295 let OperandType = "OPERAND_MEMORY";
298 def PtrRC : Operand<iPTR> {
299 let MIOperandInfo = (ops ptr_rc);
302 // size operand of ext instruction
303 def size_ext : Operand<i32> {
304 let EncoderMethod = "getSizeExtEncoding";
305 let DecoderMethod = "DecodeExtSize";
308 // size operand of ins instruction
309 def size_ins : Operand<i32> {
310 let EncoderMethod = "getSizeInsEncoding";
311 let DecoderMethod = "DecodeInsSize";
314 // Transformation Function - get the lower 16 bits.
315 def LO16 : SDNodeXForm<imm, [{
316 return getImm(N, N->getZExtValue() & 0xFFFF);
319 // Transformation Function - get the higher 16 bits.
320 def HI16 : SDNodeXForm<imm, [{
321 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
325 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
327 // Node immediate fits as 16-bit sign extended on target immediate.
329 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
331 // Node immediate fits as 16-bit sign extended on target immediate.
333 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
335 // Node immediate fits as 15-bit sign extended on target immediate.
337 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
339 // Node immediate fits as 16-bit zero extended on target immediate.
340 // The LO16 param means that only the lower 16 bits of the node
341 // immediate are caught.
343 def immZExt16 : PatLeaf<(imm), [{
344 if (N->getValueType(0) == MVT::i32)
345 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
347 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
350 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
351 def immLow16Zero : PatLeaf<(imm), [{
352 int64_t Val = N->getSExtValue();
353 return isInt<32>(Val) && !(Val & 0xffff);
356 // shamt field must fit in 5 bits.
357 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
359 // True if (N + 1) fits in 16-bit field.
360 def immSExt16Plus1 : PatLeaf<(imm), [{
361 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
364 // Mips Address Mode! SDNode frameindex could possibily be a match
365 // since load and store instructions from stack used it.
367 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
370 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
373 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
375 //===----------------------------------------------------------------------===//
376 // Instructions specific format
377 //===----------------------------------------------------------------------===//
379 // Arithmetic and logical instructions with 3 register operands.
380 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
381 InstrItinClass Itin = NoItinerary,
382 SDPatternOperator OpNode = null_frag>:
383 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
384 !strconcat(opstr, "\t$rd, $rs, $rt"),
385 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
386 let isCommutable = isComm;
387 let isReMaterializable = 1;
390 // Arithmetic and logical instructions with 2 register operands.
391 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
392 InstrItinClass Itin = NoItinerary,
393 SDPatternOperator imm_type = null_frag,
394 SDPatternOperator OpNode = null_frag> :
395 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
396 !strconcat(opstr, "\t$rt, $rs, $imm16"),
397 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
399 let isReMaterializable = 1;
400 let TwoOperandAliasConstraint = "$rs = $rt";
403 // Arithmetic Multiply ADD/SUB
404 class MArithR<string opstr, bit isComm = 0> :
405 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
406 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
407 let Defs = [HI0, LO0];
408 let Uses = [HI0, LO0];
409 let isCommutable = isComm;
413 class LogicNOR<string opstr, RegisterOperand RO>:
414 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
415 !strconcat(opstr, "\t$rd, $rs, $rt"),
416 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
417 let isCommutable = 1;
421 class shift_rotate_imm<string opstr, Operand ImmOpnd,
422 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
423 SDPatternOperator PF = null_frag> :
424 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
425 !strconcat(opstr, "\t$rd, $rt, $shamt"),
426 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
428 class shift_rotate_reg<string opstr, RegisterOperand RO,
429 SDPatternOperator OpNode = null_frag>:
430 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
431 !strconcat(opstr, "\t$rd, $rt, $rs"),
432 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
434 // Load Upper Imediate
435 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
436 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
437 [], IIArith, FrmI>, IsAsCheapAsAMove {
438 let neverHasSideEffects = 1;
439 let isReMaterializable = 1;
442 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
443 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
445 let Inst{25-21} = addr{20-16};
446 let Inst{15-0} = addr{15-0};
447 let DecoderMethod = "DecodeMem";
451 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
452 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
453 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
454 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, opstr> {
455 let DecoderMethod = "DecodeMem";
456 let canFoldAsLoad = 1;
460 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
461 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
462 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
463 [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI, opstr> {
464 let DecoderMethod = "DecodeMem";
468 // Load/Store Left/Right
469 let canFoldAsLoad = 1 in
470 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
471 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
472 !strconcat(opstr, "\t$rt, $addr"),
473 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
474 let DecoderMethod = "DecodeMem";
475 string Constraints = "$src = $rt";
478 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
479 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
480 [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
481 let DecoderMethod = "DecodeMem";
484 // Conditional Branch
485 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
486 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
487 !strconcat(opstr, "\t$rs, $rt, $offset"),
488 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
491 let isTerminator = 1;
492 let hasDelaySlot = 1;
496 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
497 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
498 !strconcat(opstr, "\t$rs, $offset"),
499 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
501 let isTerminator = 1;
502 let hasDelaySlot = 1;
507 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
508 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
509 !strconcat(opstr, "\t$rd, $rs, $rt"),
510 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
513 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
515 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
516 !strconcat(opstr, "\t$rt, $rs, $imm16"),
517 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
521 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
522 SDPatternOperator targetoperator> :
523 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
524 [(operator targetoperator:$target)], IIBranch, FrmJ> {
527 let hasDelaySlot = 1;
528 let DecoderMethod = "DecodeJumpTarget";
532 // Unconditional branch
533 class UncondBranch<string opstr> :
534 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
535 [(br bb:$offset)], IIBranch, FrmI> {
537 let isTerminator = 1;
539 let hasDelaySlot = 1;
540 let Predicates = [RelocPIC, HasStdEnc];
544 // Base class for indirect branch and return instruction classes.
545 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
546 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
547 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
550 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
552 let isIndirectBranch = 1;
555 // Return instruction
556 class RetBase<RegisterOperand RO>: JumpFR<RO> {
558 let isCodeGenOnly = 1;
560 let hasExtraSrcRegAllocReq = 1;
563 // Jump and Link (Call)
564 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
565 class JumpLink<string opstr> :
566 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
567 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
568 let DecoderMethod = "DecodeJumpTarget";
571 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
572 Register RetReg, RegisterOperand ResRO = RO>:
573 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
574 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
576 class JumpLinkReg<string opstr, RegisterOperand RO>:
577 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
580 class BGEZAL_FT<string opstr, RegisterOperand RO> :
581 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
582 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
586 class BAL_BR_Pseudo<Instruction RealInst> :
587 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
588 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
590 let isTerminator = 1;
592 let hasDelaySlot = 1;
597 class SYS_FT<string opstr> :
598 InstSE<(outs), (ins uimm20:$code_),
599 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
601 class BRK_FT<string opstr> :
602 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
603 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
606 class ER_FT<string opstr> :
607 InstSE<(outs), (ins),
608 opstr, [], NoItinerary, FrmOther>;
611 class DEI_FT<string opstr, RegisterOperand RO> :
612 InstSE<(outs RO:$rt), (ins),
613 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
616 class WAIT_FT<string opstr> :
617 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
618 let Inst{31-26} = 0x10;
621 let Inst{5-0} = 0x20;
625 let hasSideEffects = 1 in
627 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
628 NoItinerary, FrmOther>;
630 let hasSideEffects = 1 in
631 class TEQ_FT<string opstr, RegisterOperand RO> :
632 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
633 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
635 class TEQI_FT<string opstr, RegisterOperand RO> :
636 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
637 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
639 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
640 list<Register> DefRegs> :
641 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
643 let isCommutable = 1;
645 let neverHasSideEffects = 1;
648 // Pseudo multiply/divide instruction with explicit accumulator register
650 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
651 SDPatternOperator OpNode, InstrItinClass Itin,
652 bit IsComm = 1, bit HasSideEffects = 0,
653 bit UsesCustomInserter = 0> :
654 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
655 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
656 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
657 let isCommutable = IsComm;
658 let hasSideEffects = HasSideEffects;
659 let usesCustomInserter = UsesCustomInserter;
662 // Pseudo multiply add/sub instruction with explicit accumulator register
664 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
665 : PseudoSE<(outs ACC64:$ac),
666 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
668 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
670 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
671 string Constraints = "$acin = $ac";
674 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
675 list<Register> DefRegs> :
676 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
682 class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
683 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
685 let neverHasSideEffects = 1;
688 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
689 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
691 let neverHasSideEffects = 1;
694 class EffectiveAddress<string opstr, RegisterOperand RO> :
695 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
696 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
697 let isCodeGenOnly = 1;
698 let DecoderMethod = "DecodeMem";
701 // Count Leading Ones/Zeros in Word
702 class CountLeading0<string opstr, RegisterOperand RO>:
703 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
704 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
705 Requires<[HasBitCount, HasStdEnc]>;
707 class CountLeading1<string opstr, RegisterOperand RO>:
708 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
709 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
710 Requires<[HasBitCount, HasStdEnc]>;
713 // Sign Extend in Register.
714 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
715 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
716 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> {
717 let Predicates = [HasSEInReg, HasStdEnc];
721 class SubwordSwap<string opstr, RegisterOperand RO>:
722 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
724 let Predicates = [HasSwap, HasStdEnc];
725 let neverHasSideEffects = 1;
729 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
730 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
734 class ExtBase<string opstr, RegisterOperand RO>:
735 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
736 !strconcat(opstr, " $rt, $rs, $pos, $size"),
737 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
739 let Predicates = [HasMips32r2, HasStdEnc];
742 class InsBase<string opstr, RegisterOperand RO>:
743 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
744 !strconcat(opstr, " $rt, $rs, $pos, $size"),
745 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
747 let Predicates = [HasMips32r2, HasStdEnc];
748 let Constraints = "$src = $rt";
751 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
752 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
753 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
754 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
756 // Atomic Compare & Swap.
757 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
758 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
759 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
761 class LLBase<string opstr, RegisterOperand RO> :
762 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
763 [], NoItinerary, FrmI> {
764 let DecoderMethod = "DecodeMem";
768 class SCBase<string opstr, RegisterOperand RO> :
769 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
770 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
771 let DecoderMethod = "DecodeMem";
773 let Constraints = "$rt = $dst";
776 class MFC3OP<dag outs, dag ins, string asmstr> :
777 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
779 let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in
780 def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> {
781 let Inst = 0x0000000d;
784 //===----------------------------------------------------------------------===//
785 // Pseudo instructions
786 //===----------------------------------------------------------------------===//
789 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
790 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
792 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
793 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
794 [(callseq_start timm:$amt)]>;
795 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
796 [(callseq_end timm:$amt1, timm:$amt2)]>;
799 let usesCustomInserter = 1 in {
800 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
801 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
802 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
803 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
804 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
805 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
806 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
807 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
808 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
809 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
810 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
811 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
812 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
813 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
814 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
815 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
816 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
817 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
819 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
820 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
821 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
823 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
824 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
825 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
828 /// Pseudo instructions for loading and storing accumulator registers.
829 let isPseudo = 1, isCodeGenOnly = 1 in {
830 def LOAD_ACC64 : Load<"", ACC64>;
831 def STORE_ACC64 : Store<"", ACC64>;
834 //===----------------------------------------------------------------------===//
835 // Instruction definition
836 //===----------------------------------------------------------------------===//
837 //===----------------------------------------------------------------------===//
838 // MipsI Instructions
839 //===----------------------------------------------------------------------===//
841 /// Arithmetic Instructions (ALU Immediate)
842 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
844 ADDI_FM<0x9>, IsAsCheapAsAMove;
845 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
846 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
848 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
850 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
853 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
856 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
859 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
861 /// Arithmetic Instructions (3-Operand, R-Type)
862 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
864 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
866 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
868 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
869 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
870 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
871 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
872 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
874 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
876 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
878 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
880 /// Shift Instructions
881 def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>,
883 def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>,
885 def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>,
887 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
888 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
889 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
891 // Rotate Instructions
892 let Predicates = [HasMips32r2, HasStdEnc] in {
893 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr,
896 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
900 /// Load and Store Instructions
902 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
903 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
905 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
907 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
908 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
910 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
911 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
912 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
914 /// load/store left/right
915 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>;
916 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>;
917 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>;
918 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
920 def SYNC : SYNC_FT, SYNC_FM;
921 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
922 def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
923 def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
924 def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
925 def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
926 def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
928 def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
929 def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
930 def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
931 def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
932 def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
933 def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
935 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
936 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
938 def ERET : ER_FT<"eret">, ER_FM<0x18>;
939 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
941 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
942 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
944 def WAIT : WAIT_FT<"wait">;
946 /// Load-linked, Store-conditional
947 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
948 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
950 /// Jump and Branch Instructions
951 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
952 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
953 def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>;
954 def B : UncondBranch<"b">, B_FM;
955 def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
956 def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
957 def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
958 def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
959 def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
960 def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
962 def JAL : JumpLink<"jal">, FJ<3>;
963 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
964 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
965 def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
966 def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
967 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
968 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
969 def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
971 def RET : RetBase<GPR32Opnd>, MTLO_FM<8>;
973 // Exception handling related node and instructions.
974 // The conversion sequence is:
975 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
976 // MIPSeh_return -> (stack change + indirect branch)
978 // MIPSeh_return takes the place of regular return instruction
979 // but takes two arguments (V1, V0) which are used for storing
980 // the offset and return address respectively.
981 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
983 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
984 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
986 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
987 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
988 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
989 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
991 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
994 /// Multiply and Divide Instructions.
995 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
997 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
999 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1000 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1001 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
1002 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
1003 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1005 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1008 def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1009 def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1010 def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>;
1011 def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>;
1013 /// Sign Ext In Register Instructions.
1014 def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1015 def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1018 def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1019 def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1021 /// Word Swap Bytes Within Halfwords
1022 def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1025 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1027 // FrameIndexes are legalized when they are operands from load/store
1028 // instructions. The same not happens for stack address copies, so an
1029 // add op with mem ComplexPattern is used and the stack address copy
1030 // can be matched. It's similar to Sparc LEA_ADDRi
1031 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1034 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1035 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1036 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1037 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1038 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1039 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1040 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1041 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1043 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1045 def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>;
1046 def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>;
1048 /// Move Control Registers From/To CPU Registers
1049 def MFC0_3OP : MFC3OP<(outs GPR32Opnd:$rt),
1050 (ins GPR32Opnd:$rd, uimm16:$sel),
1051 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
1053 def MTC0_3OP : MFC3OP<(outs GPR32Opnd:$rd, uimm16:$sel),
1054 (ins GPR32Opnd:$rt),
1055 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
1057 def MFC2_3OP : MFC3OP<(outs GPR32Opnd:$rt),
1058 (ins GPR32Opnd:$rd, uimm16:$sel),
1059 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
1061 def MTC2_3OP : MFC3OP<(outs GPR32Opnd:$rd, uimm16:$sel),
1062 (ins GPR32Opnd:$rt),
1063 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
1065 //===----------------------------------------------------------------------===//
1066 // Instruction aliases
1067 //===----------------------------------------------------------------------===//
1068 def : InstAlias<"move $dst, $src",
1069 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1070 Requires<[NotMips64]>;
1071 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1072 def : InstAlias<"addu $rs, $rt, $imm",
1073 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1074 def : InstAlias<"add $rs, $rt, $imm",
1075 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1076 def : InstAlias<"and $rs, $rt, $imm",
1077 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1078 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1079 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1080 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1081 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1082 def : InstAlias<"not $rt, $rs",
1083 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1084 def : InstAlias<"neg $rt, $rs",
1085 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1086 def : InstAlias<"negu $rt, $rs",
1087 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1088 def : InstAlias<"slt $rs, $rt, $imm",
1089 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1090 def : InstAlias<"xor $rs, $rt, $imm",
1091 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1092 def : InstAlias<"or $rs, $rt, $imm",
1093 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1094 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1095 def : InstAlias<"mfc0 $rt, $rd",
1096 (MFC0_3OP GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1097 def : InstAlias<"mtc0 $rt, $rd",
1098 (MTC0_3OP GPR32Opnd:$rd, 0, GPR32Opnd:$rt), 0>;
1099 def : InstAlias<"mfc2 $rt, $rd",
1100 (MFC2_3OP GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1101 def : InstAlias<"mtc2 $rt, $rd",
1102 (MTC2_3OP GPR32Opnd:$rd, 0, GPR32Opnd:$rt), 0>;
1103 def : InstAlias<"bnez $rs,$offset",
1104 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1105 def : InstAlias<"beqz $rs,$offset",
1106 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1107 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1109 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1110 def : InstAlias<"break", (BREAK 0, 0), 1>;
1111 def : InstAlias<"ei", (EI ZERO), 1>;
1112 def : InstAlias<"di", (DI ZERO), 1>;
1114 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1115 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1116 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1117 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1118 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1119 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1120 //===----------------------------------------------------------------------===//
1121 // Assembler Pseudo Instructions
1122 //===----------------------------------------------------------------------===//
1124 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1125 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1126 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1127 def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>;
1129 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1130 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1131 !strconcat(instr_asm, "\t$rt, $addr")> ;
1132 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1134 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1135 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1136 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1137 def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>;
1141 //===----------------------------------------------------------------------===//
1142 // Arbitrary patterns that map to one or more instructions
1143 //===----------------------------------------------------------------------===//
1145 // Load/store pattern templates.
1146 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1147 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1149 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1150 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1153 def : MipsPat<(i32 immSExt16:$in),
1154 (ADDiu ZERO, imm:$in)>;
1155 def : MipsPat<(i32 immZExt16:$in),
1156 (ORi ZERO, imm:$in)>;
1157 def : MipsPat<(i32 immLow16Zero:$in),
1158 (LUi (HI16 imm:$in))>;
1160 // Arbitrary immediates
1161 def : MipsPat<(i32 imm:$imm),
1162 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1164 // Carry MipsPatterns
1165 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1166 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1167 let Predicates = [HasStdEnc, NotDSP] in {
1168 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1169 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1170 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1171 (ADDiu GPR32:$src, imm:$imm)>;
1175 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1176 (JAL tglobaladdr:$dst)>;
1177 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1178 (JAL texternalsym:$dst)>;
1179 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1180 // (JALR GPR32:$dst)>;
1183 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1184 (TAILCALL tglobaladdr:$dst)>;
1185 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1186 (TAILCALL texternalsym:$dst)>;
1188 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1189 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1190 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1191 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1192 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1193 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1195 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1196 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1197 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1198 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1199 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1200 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1202 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1203 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1204 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1205 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1206 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1207 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1208 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1209 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1210 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1211 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1214 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1215 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1216 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1217 (ADDiu GPR32:$gp, tconstpool:$in)>;
1220 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1221 MipsPat<(MipsWrapper RC:$gp, node:$in),
1222 (ADDiuOp RC:$gp, node:$in)>;
1224 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1225 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1226 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1227 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1228 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1229 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1231 // Mips does not have "not", so we expand our way
1232 def : MipsPat<(not GPR32:$in),
1233 (NOR GPR32Opnd:$in, ZERO)>;
1236 let Predicates = [HasStdEnc] in {
1237 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1238 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1239 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1243 let Predicates = [HasStdEnc] in
1244 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1247 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1248 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1249 Instruction SLTiuOp, Register ZEROReg> {
1250 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1251 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1252 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1253 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1255 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1256 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1257 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1258 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1259 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1260 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1261 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1262 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1263 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1264 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1265 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1266 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1268 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1269 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1270 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1271 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1273 def : MipsPat<(brcond RC:$cond, bb:$dst),
1274 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1277 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1279 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1280 (BLEZ i32:$lhs, bb:$dst)>;
1281 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1282 (BGEZ i32:$lhs, bb:$dst)>;
1285 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1286 Instruction SLTuOp, Register ZEROReg> {
1287 def : MipsPat<(seteq RC:$lhs, 0),
1288 (SLTiuOp RC:$lhs, 1)>;
1289 def : MipsPat<(setne RC:$lhs, 0),
1290 (SLTuOp ZEROReg, RC:$lhs)>;
1291 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1292 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1293 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1294 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1297 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1298 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1299 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1300 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1301 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1304 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1305 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1306 (SLTOp RC:$rhs, RC:$lhs)>;
1307 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1308 (SLTuOp RC:$rhs, RC:$lhs)>;
1311 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1312 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1313 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1314 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1315 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1318 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1319 Instruction SLTiuOp> {
1320 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1321 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1322 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1323 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1326 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1327 defm : SetlePats<GPR32, SLT, SLTu>;
1328 defm : SetgtPats<GPR32, SLT, SLTu>;
1329 defm : SetgePats<GPR32, SLT, SLTu>;
1330 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1333 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1335 // mflo/hi patterns.
1336 def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)),
1337 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>;
1339 // Load halfword/word patterns.
1340 let AddedComplexity = 40 in {
1341 let Predicates = [HasStdEnc] in {
1342 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1343 def : LoadRegImmPat<LH, i32, sextloadi16>;
1344 def : LoadRegImmPat<LW, i32, load>;
1348 //===----------------------------------------------------------------------===//
1349 // Floating Point Support
1350 //===----------------------------------------------------------------------===//
1352 include "MipsInstrFPU.td"
1353 include "Mips64InstrInfo.td"
1354 include "MipsCondMov.td"
1359 include "Mips16InstrFormats.td"
1360 include "Mips16InstrInfo.td"
1363 include "MipsDSPInstrFormats.td"
1364 include "MipsDSPInstrInfo.td"
1367 include "MipsMSAInstrFormats.td"
1368 include "MipsMSAInstrInfo.td"
1371 include "MicroMipsInstrFormats.td"
1372 include "MicroMipsInstrInfo.td"