1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
25 // Hi and Lo nodes are used to handle global addresses. Used on
26 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
27 // static model. (nothing to do with Mips Registers Hi and Lo)
28 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
29 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
32 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
33 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
36 // These are target-independent nodes, but have target-specific formats.
37 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
38 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
41 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
42 [SDNPHasChain, SDNPOutFlag]>;
43 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
44 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
46 //===----------------------------------------------------------------------===//
47 // Mips Instruction Predicate Definitions.
48 //===----------------------------------------------------------------------===//
49 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
51 //===----------------------------------------------------------------------===//
52 // Mips Operand, Complex Patterns and Transformations Definitions.
53 //===----------------------------------------------------------------------===//
55 // Instruction operand types
56 def brtarget : Operand<OtherVT>;
57 def calltarget : Operand<i32>;
58 def uimm16 : Operand<i32>;
59 def simm16 : Operand<i32>;
60 def shamt : Operand<i32>;
61 def addrlabel : Operand<i32>;
64 def mem : Operand<i32> {
65 let PrintMethod = "printMemOperand";
66 let MIOperandInfo = (ops simm16, CPURegs);
69 // Transformation Function - get the lower 16 bits.
70 def LO16 : SDNodeXForm<imm, [{
71 return getI32Imm((unsigned)N->getValue() & 0xFFFF);
74 // Transformation Function - get the higher 16 bits.
75 def HI16 : SDNodeXForm<imm, [{
76 return getI32Imm((unsigned)N->getValue() >> 16);
79 // Node immediate fits as 16-bit sign extended on target immediate.
81 def immSExt16 : PatLeaf<(imm), [{
82 if (N->getValueType(0) == MVT::i32)
83 return (int32_t)N->getValue() == (short)N->getValue();
85 return (int64_t)N->getValue() == (short)N->getValue();
88 // Node immediate fits as 16-bit zero extended on target immediate.
89 // The LO16 param means that only the lower 16 bits of the node
90 // immediate are caught.
92 def immZExt16 : PatLeaf<(imm), [{
93 if (N->getValueType(0) == MVT::i32)
94 return (uint32_t)N->getValue() == (unsigned short)N->getValue();
96 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
99 // Node immediate fits as 32-bit zero extended on target immediate.
100 //def immZExt32 : PatLeaf<(imm), [{
101 // return (uint64_t)N->getValue() == (uint32_t)N->getValue();
104 // shamt field must fit in 5 bits.
105 def immZExt5 : PatLeaf<(imm), [{
106 return N->getValue() == ((N->getValue()) & 0x1f) ;
109 // Mips Address Mode! SDNode frameindex could possibily be a match
110 // since load and store instructions from stack used it.
111 def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
113 //===----------------------------------------------------------------------===//
114 // Instructions specific format
115 //===----------------------------------------------------------------------===//
117 // Arithmetic 3 register operands
118 let isCommutable = 1 in
119 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
120 InstrItinClass itin>:
124 (ins CPURegs:$b, CPURegs:$c),
125 !strconcat(instr_asm, " $dst, $b, $c"),
126 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
128 let isCommutable = 1 in
129 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
133 (ins CPURegs:$b, CPURegs:$c),
134 !strconcat(instr_asm, " $dst, $b, $c"),
137 // Arithmetic 2 register operands
138 let isCommutable = 1 in
139 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
140 Operand Od, PatLeaf imm_type> :
143 (ins CPURegs:$b, Od:$c),
144 !strconcat(instr_asm, " $dst, $b, $c"),
145 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
147 // Arithmetic Multiply ADD/SUB
149 class MArithR<bits<6> func, string instr_asm> :
154 !strconcat(instr_asm, " $rs, $rt"),
158 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
162 (ins CPURegs:$b, CPURegs:$c),
163 !strconcat(instr_asm, " $dst, $b, $c"),
164 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
166 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
169 (ins CPURegs:$b, uimm16:$c),
170 !strconcat(instr_asm, " $dst, $b, $c"),
171 [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))], IIAlu>;
173 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
177 (ins CPURegs:$b, CPURegs:$c),
178 !strconcat(instr_asm, " $dst, $b, $c"),
179 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
183 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
187 (ins CPURegs:$b, shamt:$c),
188 !strconcat(instr_asm, " $dst, $b, $c"),
189 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
191 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
195 (ins CPURegs:$b, CPURegs:$c),
196 !strconcat(instr_asm, " $dst, $b, $c"),
197 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
199 // Load Upper Imediate
200 class LoadUpper<bits<6> op, string instr_asm>:
204 !strconcat(instr_asm, " $dst, $imm"),
208 let isSimpleLoad = 1, hasDelaySlot = 1 in
209 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
213 !strconcat(instr_asm, " $dst, $addr"),
214 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
216 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
219 (ins CPURegs:$dst, mem:$addr),
220 !strconcat(instr_asm, " $dst, $addr"),
221 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
223 // Conditional Branch
224 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
225 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
228 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
229 !strconcat(instr_asm, " $a, $b, $offset"),
230 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
234 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
237 (ins CPURegs:$src, brtarget:$offset),
238 !strconcat(instr_asm, " $src, $offset"),
239 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
244 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
249 (ins CPURegs:$b, CPURegs:$c),
250 !strconcat(instr_asm, " $dst, $b, $c"),
251 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
254 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
255 Operand Od, PatLeaf imm_type>:
258 (ins CPURegs:$b, Od:$c),
259 !strconcat(instr_asm, " $dst, $b, $c"),
260 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
263 // Unconditional branch
264 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
265 class JumpFJ<bits<6> op, string instr_asm>:
268 (ins brtarget:$target),
269 !strconcat(instr_asm, " $target"),
270 [(br bb:$target)], IIBranch>;
272 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
273 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
277 (ins CPURegs:$target),
278 !strconcat(instr_asm, " $target"),
279 [(brind CPURegs:$target)], IIBranch>;
281 // Jump and Link (Call)
282 let isCall=1, hasDelaySlot=1,
283 // All calls clobber the non-callee saved registers...
284 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
285 T3, T4, T5, T6, T7, T8, T9, K0, K1], Uses = [GP] in {
286 class JumpLink<bits<6> op, string instr_asm>:
289 (ins calltarget:$target),
290 !strconcat(instr_asm, " $target"),
291 [(MipsJmpLink imm:$target)], IIBranch>;
294 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
299 !strconcat(instr_asm, " $rs"),
300 [(MipsJmpLink CPURegs:$rs)], IIBranch>;
302 class BranchLink<string instr_asm>:
305 (ins CPURegs:$rs, brtarget:$target),
306 !strconcat(instr_asm, " $rs, $target"),
311 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
315 (ins CPURegs:$a, CPURegs:$b),
316 !strconcat(instr_asm, " $a, $b"),
320 class MoveFromTo<bits<6> func, string instr_asm>:
325 !strconcat(instr_asm, " $dst"),
328 // Count Leading Ones/Zeros in Word
329 class CountLeading<bits<6> func, string instr_asm>:
334 !strconcat(instr_asm, " $dst, $src"),
337 class EffectiveAddress<string instr_asm> :
342 [(set CPURegs:$dst, addr:$addr)], IIAlu>;
344 //===----------------------------------------------------------------------===//
345 // Pseudo instructions
346 //===----------------------------------------------------------------------===//
348 // As stack alignment is always done with addiu, we need a 16-bit immediate
349 let Defs = [SP], Uses = [SP] in {
350 def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt),
351 "!ADJCALLSTACKDOWN $amt",
352 [(callseq_start imm:$amt)]>;
353 def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2),
354 "!ADJCALLSTACKUP $amt1",
355 [(callseq_end imm:$amt1, imm:$amt2)]>;
358 let isImplicitDef = 1 in
359 def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
360 "!IMPLICIT_DEF $dst",
361 [(set CPURegs:$dst, (undef))]>;
363 // When handling PIC code the assembler needs .cpload and .cprestore
364 // directives. If the real instructions corresponding these directives
365 // are used, we have the same behavior, but get also a bunch of warnings
366 // from the assembler.
367 def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg),
368 ".set noreorder\n\t.cpload $reg\n\t.set reorder\n", []>;
369 def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc),
370 ".cprestore $loc\n", []>;
372 //===----------------------------------------------------------------------===//
373 // Instruction definition
374 //===----------------------------------------------------------------------===//
376 //===----------------------------------------------------------------------===//
377 // MipsI Instructions
378 //===----------------------------------------------------------------------===//
382 // ADDiu just accept 16-bit immediates but we handle this on Pat's.
383 // immZExt32 is used here so it can match GlobalAddress immediates.
384 def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
385 def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
386 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
387 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
388 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
389 def ADD : ArithOverflowR<0x00, 0x20, "add">;
390 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
393 def AND : LogicR<0x24, "and", and>;
394 def OR : LogicR<0x25, "or", or>;
395 def XOR : LogicR<0x26, "xor", xor>;
396 def ANDi : LogicI<0x0c, "andi", and>;
397 def ORi : LogicI<0x0d, "ori", or>;
398 def XORi : LogicI<0x0e, "xori", xor>;
399 def NOR : LogicNOR<0x00, 0x27, "nor">;
402 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
403 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
404 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
405 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
406 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
407 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
409 // Load Upper Immediate
410 def LUi : LoadUpper<0x0f, "lui">;
413 def LB : LoadM<0x20, "lb", sextloadi8>;
414 def LBu : LoadM<0x24, "lbu", zextloadi8>;
415 def LH : LoadM<0x21, "lh", sextloadi16>;
416 def LHu : LoadM<0x25, "lhu", zextloadi16>;
417 def LW : LoadM<0x23, "lw", load>;
418 def SB : StoreM<0x28, "sb", truncstorei8>;
419 def SH : StoreM<0x29, "sh", truncstorei16>;
420 def SW : StoreM<0x2b, "sw", store>;
422 // Conditional Branch
423 def BEQ : CBranch<0x04, "beq", seteq>;
424 def BNE : CBranch<0x05, "bne", setne>;
427 def BGEZ : CBranchZero<0x01, "bgez", setge>;
430 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
431 def BLEZ : CBranchZero<0x07, "blez", setle>;
432 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
435 // Set Condition Code
436 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
437 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
438 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
439 def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
441 // Unconditional jump
442 def J : JumpFJ<0x02, "j">;
443 def JR : JumpFR<0x00, 0x08, "jr">;
445 // Jump and Link (Call)
446 def JAL : JumpLink<0x03, "jal">;
447 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
448 def BGEZAL : BranchLink<"bgezal">;
449 def BLTZAL : BranchLink<"bltzal">;
451 // MulDiv and Move From Hi/Lo operations, have
452 // their correpondent SDNodes created on ISelDAG.
453 // Special Mul, Div operations
454 def MULT : MulDiv<0x18, "mult", IIImul>;
455 def MULTu : MulDiv<0x19, "multu", IIImul>;
456 def DIV : MulDiv<0x1a, "div", IIIdiv>;
457 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
460 def MFHI : MoveFromTo<0x10, "mfhi">;
461 def MFLO : MoveFromTo<0x12, "mflo">;
462 def MTHI : MoveFromTo<0x11, "mthi">;
463 def MTLO : MoveFromTo<0x13, "mtlo">;
466 // CLO/CLZ are part of the newer MIPS32(tm) instruction
467 // set and not older Mips I keep this for future use
469 //def CLO : CountLeading<0x21, "clo">;
470 //def CLZ : CountLeading<0x20, "clz">;
472 // MADD*/MSUB* are not part of MipsI either.
473 //def MADD : MArithR<0x00, "madd">;
474 //def MADDU : MArithR<0x01, "maddu">;
475 //def MSUB : MArithR<0x04, "msub">;
476 //def MSUBU : MArithR<0x05, "msubu">;
480 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
482 // Ret instruction - as mips does not have "ret" a
483 // jr $ra must be generated.
484 let isReturn=1, isTerminator=1, hasDelaySlot=1,
485 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
487 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
488 "jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
491 // FrameIndexes are legalized when they are operands from load/store
492 // instructions. The same not happens for stack address copies, so an
493 // add op with mem ComplexPattern is used and the stack address copy
494 // can be matched. It's similar to Sparc LEA_ADDRi
495 def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
497 //===----------------------------------------------------------------------===//
498 // Arbitrary patterns that map to one or more instructions
499 //===----------------------------------------------------------------------===//
502 def : Pat<(i32 immSExt16:$in),
503 (ADDiu ZERO, imm:$in)>;
504 def : Pat<(i32 immZExt16:$in),
505 (ORi ZERO, imm:$in)>;
507 // Arbitrary immediates
508 def : Pat<(i32 imm:$imm),
509 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
512 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
513 (JAL tglobaladdr:$dst)>;
514 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
515 (JAL texternalsym:$dst)>;
516 def : Pat<(MipsJmpLink CPURegs:$dst),
517 (JALR CPURegs:$dst)>;
519 // GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
520 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
521 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
522 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
523 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
524 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
525 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
526 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
527 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
529 // Mips does not have not, so we increase the operation
530 def : Pat<(not CPURegs:$in),
531 (NOR CPURegs:$in, ZERO)>;
533 // extended load and stores
534 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
535 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
536 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
539 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
545 // direct match equal/notequal zero branches
546 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
547 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
548 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
549 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
551 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
552 (BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
553 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
554 (BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
556 def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
557 (BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
558 def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
559 (BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
561 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
562 (BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
563 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
564 (BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
566 def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
567 (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
568 def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
569 (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
570 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
571 (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
572 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
573 (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
575 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
576 (BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
577 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
578 (BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
580 // generic brcond pattern
581 def : Pat<(brcond CPURegs:$cond, bb:$dst),
582 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
585 /// setcc patterns, only matched when there
586 /// is no brcond following a setcc operation
589 // setcc 2 register operands
590 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
591 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
592 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
593 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
595 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
596 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
597 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
598 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
600 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
601 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
602 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
603 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
605 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
606 (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
607 (SLT CPURegs:$rhs, CPURegs:$lhs))>;
609 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
610 (XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
611 (SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
613 // setcc reg/imm operands
614 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
615 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
616 def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
617 (XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;