1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
160 AssemblerPredicate<"FeatureMips2">;
161 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
162 AssemblerPredicate<"FeatureMips32">;
163 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
164 AssemblerPredicate<"FeatureMips32r2">;
165 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
166 AssemblerPredicate<"FeatureGP64Bit">;
167 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
168 AssemblerPredicate<"!FeatureGP64Bit">;
169 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
170 AssemblerPredicate<"FeatureMips64">;
171 def IsGP32 : Predicate<"!Subtarget.isGP64()">,
172 AssemblerPredicate<"!FeatureGP64Bit">;
173 def IsGP64 : Predicate<"Subtarget.isGP64()">,
174 AssemblerPredicate<"FeatureGP64Bit">;
175 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
176 AssemblerPredicate<"FeatureMips64r2">;
177 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
178 AssemblerPredicate<"FeatureN64">;
179 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
180 AssemblerPredicate<"FeatureMips16">;
181 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
182 AssemblerPredicate<"FeatureCnMips">;
183 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
184 AssemblerPredicate<"FeatureMips32">;
185 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
186 AssemblerPredicate<"FeatureMips32">;
187 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
188 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
189 AssemblerPredicate<"!FeatureMips16">;
190 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
191 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
192 AssemblerPredicate<"FeatureMicroMips">;
193 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
194 AssemblerPredicate<"!FeatureMicroMips">;
195 def IsLE : Predicate<"Subtarget.isLittle()">;
196 def IsBE : Predicate<"!Subtarget.isLittle()">;
197 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
199 //===----------------------------------------------------------------------===//
200 // Mips GPR size adjectives.
201 // They are mutually exclusive.
202 //===----------------------------------------------------------------------===//
204 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
206 //===----------------------------------------------------------------------===//
207 // Mips ISA/ASE membership and instruction group membership adjectives.
208 // They are mutually exclusive.
209 //===----------------------------------------------------------------------===//
211 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
212 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
213 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
215 class INSN_SWAP { list<Predicate> InsnPredicates = [HasSwap]; }
216 class INSN_SEINREG { list<Predicate> InsnPredicates = [HasSEInReg]; }
218 //===----------------------------------------------------------------------===//
220 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
221 let EncodingPredicates = [HasStdEnc];
224 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
225 InstAlias<Asm, Result, Emit>, PredicateControl;
228 bit isCommutable = 1;
245 bit isTerminator = 1;
248 bit hasExtraSrcRegAllocReq = 1;
249 bit isCodeGenOnly = 1;
252 class IsAsCheapAsAMove {
253 bit isAsCheapAsAMove = 1;
256 class NeverHasSideEffects {
257 bit neverHasSideEffects = 1;
260 //===----------------------------------------------------------------------===//
261 // Instruction format superclass
262 //===----------------------------------------------------------------------===//
264 include "MipsInstrFormats.td"
266 //===----------------------------------------------------------------------===//
267 // Mips Operand, Complex Patterns and Transformations Definitions.
268 //===----------------------------------------------------------------------===//
270 def MipsJumpTargetAsmOperand : AsmOperandClass {
271 let Name = "JumpTarget";
272 let ParserMethod = "ParseJumpTarget";
273 let PredicateMethod = "isImm";
274 let RenderMethod = "addImmOperands";
277 // Instruction operand types
278 def jmptarget : Operand<OtherVT> {
279 let EncoderMethod = "getJumpTargetOpValue";
280 let ParserMatchClass = MipsJumpTargetAsmOperand;
282 def brtarget : Operand<OtherVT> {
283 let EncoderMethod = "getBranchTargetOpValue";
284 let OperandType = "OPERAND_PCREL";
285 let DecoderMethod = "DecodeBranchTarget";
286 let ParserMatchClass = MipsJumpTargetAsmOperand;
288 def calltarget : Operand<iPTR> {
289 let EncoderMethod = "getJumpTargetOpValue";
290 let ParserMatchClass = MipsJumpTargetAsmOperand;
293 def simm10 : Operand<i32>;
295 def simm16 : Operand<i32> {
296 let DecoderMethod= "DecodeSimm16";
299 def simm20 : Operand<i32> {
302 def uimm20 : Operand<i32> {
305 def uimm10 : Operand<i32> {
308 def simm16_64 : Operand<i64> {
309 let DecoderMethod = "DecodeSimm16";
313 def uimmz : Operand<i32> {
314 let PrintMethod = "printUnsignedImm";
318 def uimm5 : Operand<i32> {
319 let PrintMethod = "printUnsignedImm";
322 def uimm6 : Operand<i32> {
323 let PrintMethod = "printUnsignedImm";
326 def uimm16 : Operand<i32> {
327 let PrintMethod = "printUnsignedImm";
330 def pcrel16 : Operand<i32> {
333 def MipsMemAsmOperand : AsmOperandClass {
335 let ParserMethod = "parseMemOperand";
338 def MipsInvertedImmoperand : AsmOperandClass {
340 let RenderMethod = "addImmOperands";
341 let ParserMethod = "parseInvNum";
344 def InvertedImOperand : Operand<i32> {
345 let ParserMatchClass = MipsInvertedImmoperand;
348 def InvertedImOperand64 : Operand<i64> {
349 let ParserMatchClass = MipsInvertedImmoperand;
352 class mem_generic : Operand<iPTR> {
353 let PrintMethod = "printMemOperand";
354 let MIOperandInfo = (ops ptr_rc, simm16);
355 let EncoderMethod = "getMemEncoding";
356 let ParserMatchClass = MipsMemAsmOperand;
357 let OperandType = "OPERAND_MEMORY";
361 def mem : mem_generic;
363 // MSA specific address operand
364 def mem_msa : mem_generic {
365 let MIOperandInfo = (ops ptr_rc, simm10);
366 let EncoderMethod = "getMSAMemEncoding";
369 def mem_ea : Operand<iPTR> {
370 let PrintMethod = "printMemOperandEA";
371 let MIOperandInfo = (ops ptr_rc, simm16);
372 let EncoderMethod = "getMemEncoding";
373 let OperandType = "OPERAND_MEMORY";
376 def PtrRC : Operand<iPTR> {
377 let MIOperandInfo = (ops ptr_rc);
378 let DecoderMethod = "DecodePtrRegisterClass";
379 let ParserMatchClass = GPR32AsmOperand;
382 // size operand of ext instruction
383 def size_ext : Operand<i32> {
384 let EncoderMethod = "getSizeExtEncoding";
385 let DecoderMethod = "DecodeExtSize";
388 // size operand of ins instruction
389 def size_ins : Operand<i32> {
390 let EncoderMethod = "getSizeInsEncoding";
391 let DecoderMethod = "DecodeInsSize";
394 // Transformation Function - get the lower 16 bits.
395 def LO16 : SDNodeXForm<imm, [{
396 return getImm(N, N->getZExtValue() & 0xFFFF);
399 // Transformation Function - get the higher 16 bits.
400 def HI16 : SDNodeXForm<imm, [{
401 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
405 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
407 // Node immediate is zero (e.g. insve.d)
408 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
410 // Node immediate fits as 16-bit sign extended on target immediate.
412 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
414 // Node immediate fits as 16-bit sign extended on target immediate.
416 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
418 // Node immediate fits as 15-bit sign extended on target immediate.
420 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
422 // Node immediate fits as 16-bit zero extended on target immediate.
423 // The LO16 param means that only the lower 16 bits of the node
424 // immediate are caught.
426 def immZExt16 : PatLeaf<(imm), [{
427 if (N->getValueType(0) == MVT::i32)
428 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
430 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
433 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
434 def immLow16Zero : PatLeaf<(imm), [{
435 int64_t Val = N->getSExtValue();
436 return isInt<32>(Val) && !(Val & 0xffff);
439 // shamt field must fit in 5 bits.
440 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
442 // True if (N + 1) fits in 16-bit field.
443 def immSExt16Plus1 : PatLeaf<(imm), [{
444 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
447 // Mips Address Mode! SDNode frameindex could possibily be a match
448 // since load and store instructions from stack used it.
450 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
453 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
456 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
459 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
461 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
463 //===----------------------------------------------------------------------===//
464 // Instructions specific format
465 //===----------------------------------------------------------------------===//
467 // Arithmetic and logical instructions with 3 register operands.
468 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
469 InstrItinClass Itin = NoItinerary,
470 SDPatternOperator OpNode = null_frag>:
471 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
472 !strconcat(opstr, "\t$rd, $rs, $rt"),
473 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
474 let isCommutable = isComm;
475 let isReMaterializable = 1;
476 let TwoOperandAliasConstraint = "$rd = $rs";
479 // Arithmetic and logical instructions with 2 register operands.
480 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
481 InstrItinClass Itin = NoItinerary,
482 SDPatternOperator imm_type = null_frag,
483 SDPatternOperator OpNode = null_frag> :
484 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
485 !strconcat(opstr, "\t$rt, $rs, $imm16"),
486 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
488 let isReMaterializable = 1;
489 let TwoOperandAliasConstraint = "$rs = $rt";
492 // Arithmetic Multiply ADD/SUB
493 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
494 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
495 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
496 let Defs = [HI0, LO0];
497 let Uses = [HI0, LO0];
498 let isCommutable = isComm;
502 class LogicNOR<string opstr, RegisterOperand RO>:
503 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
504 !strconcat(opstr, "\t$rd, $rs, $rt"),
505 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
506 let isCommutable = 1;
510 class shift_rotate_imm<string opstr, Operand ImmOpnd,
511 RegisterOperand RO, InstrItinClass itin,
512 SDPatternOperator OpNode = null_frag,
513 SDPatternOperator PF = null_frag> :
514 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
515 !strconcat(opstr, "\t$rd, $rt, $shamt"),
516 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
517 let TwoOperandAliasConstraint = "$rt = $rd";
520 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
521 SDPatternOperator OpNode = null_frag>:
522 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
523 !strconcat(opstr, "\t$rd, $rt, $rs"),
524 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
527 // Load Upper Imediate
528 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
529 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
530 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
531 let neverHasSideEffects = 1;
532 let isReMaterializable = 1;
536 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
537 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
538 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
539 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
540 let DecoderMethod = "DecodeMem";
541 let canFoldAsLoad = 1;
545 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
546 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
547 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
548 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
549 let DecoderMethod = "DecodeMem";
553 // Load/Store Left/Right
554 let canFoldAsLoad = 1 in
555 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
556 InstrItinClass Itin> :
557 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
558 !strconcat(opstr, "\t$rt, $addr"),
559 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
560 let DecoderMethod = "DecodeMem";
561 string Constraints = "$src = $rt";
564 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
565 InstrItinClass Itin> :
566 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
567 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
568 let DecoderMethod = "DecodeMem";
571 // Conditional Branch
572 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
573 RegisterOperand RO> :
574 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
575 !strconcat(opstr, "\t$rs, $rt, $offset"),
576 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
579 let isTerminator = 1;
580 let hasDelaySlot = 1;
584 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
585 RegisterOperand RO> :
586 InstSE<(outs), (ins RO:$rs, opnd:$offset),
587 !strconcat(opstr, "\t$rs, $offset"),
588 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
591 let isTerminator = 1;
592 let hasDelaySlot = 1;
597 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
598 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
599 !strconcat(opstr, "\t$rd, $rs, $rt"),
600 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
601 II_SLT_SLTU, FrmR, opstr>;
603 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
605 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
606 !strconcat(opstr, "\t$rt, $rs, $imm16"),
607 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
608 II_SLTI_SLTIU, FrmI, opstr>;
611 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
612 SDPatternOperator targetoperator, string bopstr> :
613 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
614 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
617 let hasDelaySlot = 1;
618 let DecoderMethod = "DecodeJumpTarget";
622 // Unconditional branch
623 class UncondBranch<Instruction BEQInst> :
624 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
625 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
627 let isTerminator = 1;
629 let hasDelaySlot = 1;
630 let AdditionalPredicates = [RelocPIC];
634 // Base class for indirect branch and return instruction classes.
635 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
636 class JumpFR<string opstr, RegisterOperand RO,
637 SDPatternOperator operator = null_frag>:
638 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
642 class IndirectBranch<string opstr, RegisterOperand RO> :
643 JumpFR<opstr, RO, brind> {
645 let isIndirectBranch = 1;
648 // Return instruction
649 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
651 let isCodeGenOnly = 1;
653 let hasExtraSrcRegAllocReq = 1;
656 // Jump and Link (Call)
657 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
658 class JumpLink<string opstr, DAGOperand opnd> :
659 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
660 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
661 let DecoderMethod = "DecodeJumpTarget";
664 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
665 Register RetReg, RegisterOperand ResRO = RO>:
666 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
667 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
669 class JumpLinkReg<string opstr, RegisterOperand RO>:
670 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
673 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
674 InstSE<(outs), (ins RO:$rs, opnd:$offset),
675 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
679 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
680 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
681 class TailCall<Instruction JumpInst> :
682 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
683 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
685 class TailCallReg<RegisterOperand RO, Instruction JRInst,
686 RegisterOperand ResRO = RO> :
687 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
688 PseudoInstExpansion<(JRInst ResRO:$rs)>;
691 class BAL_BR_Pseudo<Instruction RealInst> :
692 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
693 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
695 let isTerminator = 1;
697 let hasDelaySlot = 1;
702 class SYS_FT<string opstr> :
703 InstSE<(outs), (ins uimm20:$code_),
704 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
706 class BRK_FT<string opstr> :
707 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
708 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
712 class ER_FT<string opstr> :
713 InstSE<(outs), (ins),
714 opstr, [], NoItinerary, FrmOther, opstr>;
717 class DEI_FT<string opstr, RegisterOperand RO> :
718 InstSE<(outs RO:$rt), (ins),
719 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
722 class WAIT_FT<string opstr> :
723 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
726 let hasSideEffects = 1 in
727 class SYNC_FT<string opstr> :
728 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
729 NoItinerary, FrmOther, opstr>;
731 let hasSideEffects = 1 in
732 class TEQ_FT<string opstr, RegisterOperand RO> :
733 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
734 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
737 class TEQI_FT<string opstr, RegisterOperand RO> :
738 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
739 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
741 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
742 list<Register> DefRegs> :
743 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
745 let isCommutable = 1;
747 let neverHasSideEffects = 1;
750 // Pseudo multiply/divide instruction with explicit accumulator register
752 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
753 SDPatternOperator OpNode, InstrItinClass Itin,
754 bit IsComm = 1, bit HasSideEffects = 0,
755 bit UsesCustomInserter = 0> :
756 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
757 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
758 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
759 let isCommutable = IsComm;
760 let hasSideEffects = HasSideEffects;
761 let usesCustomInserter = UsesCustomInserter;
764 // Pseudo multiply add/sub instruction with explicit accumulator register
766 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
768 : PseudoSE<(outs ACC64:$ac),
769 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
771 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
773 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
774 string Constraints = "$acin = $ac";
777 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
778 list<Register> DefRegs> :
779 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
780 [], itin, FrmR, opstr> {
785 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
786 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
787 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
789 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
790 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
793 let neverHasSideEffects = 1;
796 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
797 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
798 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
801 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
802 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
805 let neverHasSideEffects = 1;
808 class EffectiveAddress<string opstr, RegisterOperand RO> :
809 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
810 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
811 !strconcat(opstr, "_lea")> {
812 let isCodeGenOnly = 1;
813 let DecoderMethod = "DecodeMem";
816 // Count Leading Ones/Zeros in Word
817 class CountLeading0<string opstr, RegisterOperand RO>:
818 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
819 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
820 AdditionalRequires<[HasBitCount]>;
822 class CountLeading1<string opstr, RegisterOperand RO>:
823 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
824 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
825 AdditionalRequires<[HasBitCount]>;
827 // Sign Extend in Register.
828 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
829 InstrItinClass itin> :
830 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
831 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>,
835 class SubwordSwap<string opstr, RegisterOperand RO>:
836 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
837 NoItinerary, FrmR, opstr>, INSN_SWAP {
838 let neverHasSideEffects = 1;
842 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
843 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
847 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
848 SDPatternOperator Op = null_frag>:
849 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
850 !strconcat(opstr, " $rt, $rs, $pos, $size"),
851 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
852 FrmR, opstr>, ISA_MIPS32R2;
854 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
855 SDPatternOperator Op = null_frag>:
856 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
857 !strconcat(opstr, " $rt, $rs, $pos, $size"),
858 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
859 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
860 let Constraints = "$src = $rt";
863 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
864 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
865 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
866 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
868 // Atomic Compare & Swap.
869 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
870 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
871 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
873 class LLBase<string opstr, RegisterOperand RO> :
874 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
875 [], NoItinerary, FrmI> {
876 let DecoderMethod = "DecodeMem";
880 class SCBase<string opstr, RegisterOperand RO> :
881 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
882 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
883 let DecoderMethod = "DecodeMem";
885 let Constraints = "$rt = $dst";
888 class MFC3OP<string asmstr, RegisterOperand RO> :
889 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
890 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
892 class TrapBase<Instruction RealInst>
893 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
894 PseudoInstExpansion<(RealInst 0, 0)> {
896 let isTerminator = 1;
897 let isCodeGenOnly = 1;
900 //===----------------------------------------------------------------------===//
901 // Pseudo instructions
902 //===----------------------------------------------------------------------===//
905 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
906 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
908 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
909 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
910 [(callseq_start timm:$amt)]>;
911 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
912 [(callseq_end timm:$amt1, timm:$amt2)]>;
915 let usesCustomInserter = 1 in {
916 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
917 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
918 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
919 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
920 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
921 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
922 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
923 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
924 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
925 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
926 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
927 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
928 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
929 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
930 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
931 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
932 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
933 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
935 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
936 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
937 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
939 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
940 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
941 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
944 /// Pseudo instructions for loading and storing accumulator registers.
945 let isPseudo = 1, isCodeGenOnly = 1 in {
946 def LOAD_ACC64 : Load<"", ACC64>;
947 def STORE_ACC64 : Store<"", ACC64>;
950 // We need these two pseudo instructions to avoid offset calculation for long
951 // branches. See the comment in file MipsLongBranch.cpp for detailed
954 // Expands to: lui $dst, %hi($tgt - $baltgt)
955 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
956 (ins brtarget:$tgt, brtarget:$baltgt), []>;
958 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
959 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
960 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
962 //===----------------------------------------------------------------------===//
963 // Instruction definition
964 //===----------------------------------------------------------------------===//
965 //===----------------------------------------------------------------------===//
966 // MipsI Instructions
967 //===----------------------------------------------------------------------===//
969 /// Arithmetic Instructions (ALU Immediate)
970 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
972 ADDI_FM<0x9>, IsAsCheapAsAMove;
973 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
974 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
976 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
978 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
981 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
984 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
987 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
989 /// Arithmetic Instructions (3-Operand, R-Type)
990 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
992 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
994 let Defs = [HI0, LO0] in
995 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
997 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
998 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
999 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1000 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1001 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1003 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1005 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1007 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1009 /// Shift Instructions
1010 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1011 immZExt5>, SRA_FM<0, 0>;
1012 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1013 immZExt5>, SRA_FM<2, 0>;
1014 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1015 immZExt5>, SRA_FM<3, 0>;
1016 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1018 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1020 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1023 // Rotate Instructions
1024 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1026 SRA_FM<2, 1>, ISA_MIPS32R2;
1027 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1028 SRLV_FM<6, 1>, ISA_MIPS32R2;
1030 /// Load and Store Instructions
1032 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1033 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1035 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1037 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1038 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1040 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1041 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1042 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1044 /// load/store left/right
1045 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1046 AdditionalPredicates = [NotInMicroMips] in {
1047 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1048 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1049 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1050 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1053 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1054 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1055 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1056 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1057 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1058 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1059 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1061 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, ISA_MIPS2;
1062 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, ISA_MIPS2;
1063 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, ISA_MIPS2;
1064 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, ISA_MIPS2;
1065 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, ISA_MIPS2;
1066 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, ISA_MIPS2;
1068 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1069 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1070 def TRAP : TrapBase<BREAK>;
1072 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1073 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1075 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1076 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1078 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1079 AdditionalPredicates = [NotInMicroMips] in {
1080 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1082 /// Load-linked, Store-conditional
1083 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1084 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1087 /// Jump and Branch Instructions
1088 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1089 AdditionalRequires<[RelocStatic]>, IsBranch;
1090 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1091 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1092 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1093 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1095 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1097 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1099 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1101 def B : UncondBranch<BEQ>;
1103 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1104 let AdditionalPredicates = [NotInMicroMips] in {
1105 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1106 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1108 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1109 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1110 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1111 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1112 def TAILCALL : TailCall<J>;
1113 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1115 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1117 // Exception handling related node and instructions.
1118 // The conversion sequence is:
1119 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1120 // MIPSeh_return -> (stack change + indirect branch)
1122 // MIPSeh_return takes the place of regular return instruction
1123 // but takes two arguments (V1, V0) which are used for storing
1124 // the offset and return address respectively.
1125 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1127 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1128 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1130 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1131 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1132 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1133 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1135 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1138 /// Multiply and Divide Instructions.
1139 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1141 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1143 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1145 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1148 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1149 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1150 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1151 AdditionalPredicates = [NotInMicroMips] in {
1152 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1153 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1156 /// Sign Ext In Register Instructions.
1157 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1158 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1161 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1162 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1164 /// Word Swap Bytes Within Halfwords
1165 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1168 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1170 // FrameIndexes are legalized when they are operands from load/store
1171 // instructions. The same not happens for stack address copies, so an
1172 // add op with mem ComplexPattern is used and the stack address copy
1173 // can be matched. It's similar to Sparc LEA_ADDRi
1174 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1177 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1178 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1179 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1180 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1182 let AdditionalPredicates = [NotDSP] in {
1183 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1184 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1185 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1186 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1187 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1188 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1189 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1190 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1191 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1194 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1196 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1199 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1201 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1202 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1204 /// Move Control Registers From/To CPU Registers
1205 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1206 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1207 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1208 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1210 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1212 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1213 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1214 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1216 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1218 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1219 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1220 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1221 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1223 //===----------------------------------------------------------------------===//
1224 // Instruction aliases
1225 //===----------------------------------------------------------------------===//
1226 def : MipsInstAlias<"move $dst, $src",
1227 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1228 Requires<[IsGP32, NotInMicroMips]>;
1229 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1230 def : MipsInstAlias<"addu $rs, $rt, $imm",
1231 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1232 def : MipsInstAlias<"add $rs, $rt, $imm",
1233 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1234 def : MipsInstAlias<"and $rs, $rt, $imm",
1235 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1236 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1237 let Predicates = [NotInMicroMips] in {
1238 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1240 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1241 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1242 def : MipsInstAlias<"not $rt, $rs",
1243 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1244 def : MipsInstAlias<"neg $rt, $rs",
1245 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1246 def : MipsInstAlias<"negu $rt",
1247 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1248 def : MipsInstAlias<"negu $rt, $rs",
1249 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1250 def : MipsInstAlias<"slt $rs, $rt, $imm",
1251 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1252 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1253 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1254 def : MipsInstAlias<"xor $rs, $rt, $imm",
1255 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1256 def : MipsInstAlias<"or $rs, $rt, $imm",
1257 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1258 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1259 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1260 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1261 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1262 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1263 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1264 def : MipsInstAlias<"bnez $rs,$offset",
1265 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1266 def : MipsInstAlias<"beqz $rs,$offset",
1267 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1268 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1270 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1271 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1272 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1273 def : MipsInstAlias<"di", (DI ZERO), 1>;
1275 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1276 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1277 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1279 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1280 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1282 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1283 def : MipsInstAlias<"sll $rd, $rt, $rs",
1284 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1285 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1286 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1287 InvertedImOperand:$imm)>;
1288 def : MipsInstAlias<"sub $rs, $imm",
1289 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1291 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1292 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1293 InvertedImOperand:$imm)>;
1294 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1295 InvertedImOperand:$imm), 0>;
1296 def : MipsInstAlias<"sra $rd, $rt, $rs",
1297 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1298 def : MipsInstAlias<"srl $rd, $rt, $rs",
1299 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1300 //===----------------------------------------------------------------------===//
1301 // Assembler Pseudo Instructions
1302 //===----------------------------------------------------------------------===//
1304 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1305 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1306 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1307 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1309 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1310 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1311 !strconcat(instr_asm, "\t$rt, $addr")> ;
1312 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1314 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1315 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1316 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1317 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1319 //===----------------------------------------------------------------------===//
1320 // Arbitrary patterns that map to one or more instructions
1321 //===----------------------------------------------------------------------===//
1323 // Load/store pattern templates.
1324 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1325 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1327 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1328 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1331 def : MipsPat<(i32 immSExt16:$in),
1332 (ADDiu ZERO, imm:$in)>;
1333 def : MipsPat<(i32 immZExt16:$in),
1334 (ORi ZERO, imm:$in)>;
1335 def : MipsPat<(i32 immLow16Zero:$in),
1336 (LUi (HI16 imm:$in))>;
1338 // Arbitrary immediates
1339 def : MipsPat<(i32 imm:$imm),
1340 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1342 // Carry MipsPatterns
1343 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1344 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1345 let AdditionalPredicates = [NotDSP] in {
1346 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1347 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1348 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1349 (ADDiu GPR32:$src, imm:$imm)>;
1353 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1354 (JAL tglobaladdr:$dst)>;
1355 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1356 (JAL texternalsym:$dst)>;
1357 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1358 // (JALR GPR32:$dst)>;
1361 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1362 (TAILCALL tglobaladdr:$dst)>;
1363 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1364 (TAILCALL texternalsym:$dst)>;
1366 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1367 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1368 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1369 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1370 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1371 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1373 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1374 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1375 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1376 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1377 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1378 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1380 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1381 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1382 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1383 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1384 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1385 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1386 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1387 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1388 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1389 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1392 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1393 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1394 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1395 (ADDiu GPR32:$gp, tconstpool:$in)>;
1398 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1399 MipsPat<(MipsWrapper RC:$gp, node:$in),
1400 (ADDiuOp RC:$gp, node:$in)>;
1402 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1403 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1404 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1405 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1406 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1407 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1409 // Mips does not have "not", so we expand our way
1410 def : MipsPat<(not GPR32:$in),
1411 (NOR GPR32Opnd:$in, ZERO)>;
1414 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1415 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1416 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1419 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1422 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1423 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1424 Instruction SLTiuOp, Register ZEROReg> {
1425 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1426 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1427 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1428 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1430 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1431 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1432 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1433 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1434 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1435 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1436 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1437 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1438 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1439 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1440 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1441 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1443 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1444 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1445 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1446 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1448 def : MipsPat<(brcond RC:$cond, bb:$dst),
1449 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1452 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1454 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1455 (BLEZ i32:$lhs, bb:$dst)>;
1456 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1457 (BGEZ i32:$lhs, bb:$dst)>;
1460 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1461 Instruction SLTuOp, Register ZEROReg> {
1462 def : MipsPat<(seteq RC:$lhs, 0),
1463 (SLTiuOp RC:$lhs, 1)>;
1464 def : MipsPat<(setne RC:$lhs, 0),
1465 (SLTuOp ZEROReg, RC:$lhs)>;
1466 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1467 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1468 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1469 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1472 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1473 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1474 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1475 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1476 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1479 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1480 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1481 (SLTOp RC:$rhs, RC:$lhs)>;
1482 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1483 (SLTuOp RC:$rhs, RC:$lhs)>;
1486 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1487 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1488 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1489 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1490 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1493 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1494 Instruction SLTiuOp> {
1495 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1496 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1497 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1498 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1501 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1502 defm : SetlePats<GPR32, SLT, SLTu>;
1503 defm : SetgtPats<GPR32, SLT, SLTu>;
1504 defm : SetgePats<GPR32, SLT, SLTu>;
1505 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1508 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1510 // Load halfword/word patterns.
1511 let AddedComplexity = 40 in {
1512 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1513 def : LoadRegImmPat<LH, i32, sextloadi16>;
1514 def : LoadRegImmPat<LW, i32, load>;
1517 //===----------------------------------------------------------------------===//
1518 // Floating Point Support
1519 //===----------------------------------------------------------------------===//
1521 include "MipsInstrFPU.td"
1522 include "Mips64InstrInfo.td"
1523 include "MipsCondMov.td"
1525 include "Mips32r6InstrInfo.td"
1526 include "Mips64r6InstrInfo.td"
1531 include "Mips16InstrFormats.td"
1532 include "Mips16InstrInfo.td"
1535 include "MipsDSPInstrFormats.td"
1536 include "MipsDSPInstrInfo.td"
1539 include "MipsMSAInstrFormats.td"
1540 include "MipsMSAInstrInfo.td"
1543 include "MicroMipsInstrFormats.td"
1544 include "MicroMipsInstrInfo.td"
1545 include "MicroMipsInstrFPU.td"