1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 def MipsERet : SDNode<"MipsISD::ERet", SDTNone,
81 [SDNPHasChain, SDNPOptInGlue, SDNPSideEffect]>;
83 // These are target-independent nodes, but have target-specific formats.
84 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
85 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
86 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
87 [SDNPHasChain, SDNPSideEffect,
88 SDNPOptInGlue, SDNPOutGlue]>;
90 // Nodes used to extract LO/HI registers.
91 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
92 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
94 // Node used to insert 32-bit integers to LOHI register pair.
95 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
98 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
99 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
102 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
103 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
104 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
105 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
108 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
109 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
110 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
112 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
115 // Target constant nodes that are not part of any isel patterns and remain
116 // unchanged can cause instructions with illegal operands to be emitted.
117 // Wrapper node patterns give the instruction selector a chance to replace
118 // target constant nodes that would otherwise remain unchanged with ADDiu
119 // nodes. Without these wrapper node patterns, the following conditional move
120 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
122 // movn %got(d)($gp), %got(c)($gp), $4
123 // This instruction is illegal since movn can take only register operands.
125 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
127 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
129 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
130 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
132 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
135 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
136 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
139 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
140 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
143 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
144 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
147 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
149 //===----------------------------------------------------------------------===//
150 // Mips Instruction Predicate Definitions.
151 //===----------------------------------------------------------------------===//
152 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
153 AssemblerPredicate<"FeatureMips2">;
154 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
155 AssemblerPredicate<"FeatureMips3_32">;
156 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
157 AssemblerPredicate<"FeatureMips3_32r2">;
158 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
159 AssemblerPredicate<"FeatureMips3">;
160 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
161 AssemblerPredicate<"FeatureMips4_32">;
162 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
163 AssemblerPredicate<"!FeatureMips4_32">;
164 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
165 AssemblerPredicate<"FeatureMips4_32r2">;
166 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
167 AssemblerPredicate<"FeatureMips5_32r2">;
168 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
169 AssemblerPredicate<"FeatureMips32">;
170 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
171 AssemblerPredicate<"FeatureMips32r2">;
172 def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
173 AssemblerPredicate<"FeatureMips32r5">;
174 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
175 AssemblerPredicate<"FeatureMips32r6">;
176 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
177 AssemblerPredicate<"!FeatureMips32r6">;
178 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
179 AssemblerPredicate<"FeatureGP64Bit">;
180 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
181 AssemblerPredicate<"!FeatureGP64Bit">;
182 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
183 AssemblerPredicate<"FeatureMips64">;
184 def NotMips64 : Predicate<"!Subtarget->hasMips64()">,
185 AssemblerPredicate<"!FeatureMips64">;
186 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
187 AssemblerPredicate<"FeatureMips64r2">;
188 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
189 AssemblerPredicate<"FeatureMips64r6">;
190 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
191 AssemblerPredicate<"!FeatureMips64r6">;
192 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
193 AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
194 def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
195 AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
196 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
197 AssemblerPredicate<"FeatureMips16">;
198 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
199 AssemblerPredicate<"FeatureCnMips">;
200 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
201 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
202 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
203 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
204 AssemblerPredicate<"!FeatureMips16">;
205 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
206 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
207 AssemblerPredicate<"FeatureMicroMips">;
208 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
209 AssemblerPredicate<"!FeatureMicroMips">;
210 def IsLE : Predicate<"Subtarget->isLittle()">;
211 def IsBE : Predicate<"!Subtarget->isLittle()">;
212 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
213 def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
214 def HasEVA : Predicate<"Subtarget->hasEVA()">,
215 AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
216 def HasMSA : Predicate<"Subtarget->hasMSA()">,
217 AssemblerPredicate<"FeatureMSA">;
220 //===----------------------------------------------------------------------===//
221 // Mips GPR size adjectives.
222 // They are mutually exclusive.
223 //===----------------------------------------------------------------------===//
225 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
226 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
228 //===----------------------------------------------------------------------===//
229 // Mips ISA/ASE membership and instruction group membership adjectives.
230 // They are mutually exclusive.
231 //===----------------------------------------------------------------------===//
233 // FIXME: I'd prefer to use additive predicates to build the instruction sets
234 // but we are short on assembler feature bits at the moment. Using a
235 // subtractive predicate will hopefully keep us under the 32 predicate
236 // limit long enough to develop an alternative way to handle P1||P2
238 class ISA_MIPS1_NOT_4_32 {
239 list<Predicate> InsnPredicates = [NotMips4_32];
241 class ISA_MIPS1_NOT_32R6_64R6 {
242 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
244 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
245 class ISA_MIPS2_NOT_32R6_64R6 {
246 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
248 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
249 class ISA_MIPS3_NOT_32R6_64R6 {
250 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
252 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
253 class ISA_MIPS32_NOT_32R6_64R6 {
254 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
256 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
257 class ISA_MIPS32R2_NOT_32R6_64R6 {
258 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
260 class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
261 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
262 class ISA_MIPS64_NOT_64R6 {
263 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
265 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
266 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
267 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
268 class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
269 class ISA_MICROMIPS32R6 {
270 list<Predicate> InsnPredicates = [HasMicroMips32r6];
272 class ISA_MICROMIPS64R6 {
273 list<Predicate> InsnPredicates = [HasMicroMips64r6];
275 class ISA_MICROMIPS32_NOT_MIPS32R6 {
276 list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
279 class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
280 class INSN_EVA_NOT_32R6_64R6 {
281 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
284 // The portions of MIPS-III that were also added to MIPS32
285 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
287 // The portions of MIPS-III that were also added to MIPS32 but were removed in
288 // MIPS32r6 and MIPS64r6.
289 class INSN_MIPS3_32_NOT_32R6_64R6 {
290 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
293 // The portions of MIPS-III that were also added to MIPS32
294 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
296 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
297 // MIPS32r6 and MIPS64r6.
298 class INSN_MIPS4_32_NOT_32R6_64R6 {
299 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
302 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
303 // MIPS32r6 and MIPS64r6.
304 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
305 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
308 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
309 // MIPS32r6 and MIPS64r6.
310 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
311 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
315 list<Predicate> InsnPredicates = [HasMSA];
318 class ASE_MSA_NOT_MSA64 {
319 list<Predicate> InsnPredicates = [HasMSA, NotMips64];
323 list<Predicate> InsnPredicates = [HasMSA, HasMips64];
326 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
327 // It can be used only on instructions that doesn't inherit PredicateControl.
328 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
329 let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
332 //===----------------------------------------------------------------------===//
334 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
335 let EncodingPredicates = [HasStdEnc];
338 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
339 InstAlias<Asm, Result, Emit>, PredicateControl;
342 bit isCommutable = 1;
359 bit isTerminator = 1;
362 bit hasExtraSrcRegAllocReq = 1;
363 bit isCodeGenOnly = 1;
366 class IsAsCheapAsAMove {
367 bit isAsCheapAsAMove = 1;
370 class NeverHasSideEffects {
371 bit hasSideEffects = 0;
374 //===----------------------------------------------------------------------===//
375 // Instruction format superclass
376 //===----------------------------------------------------------------------===//
378 include "MipsInstrFormats.td"
380 //===----------------------------------------------------------------------===//
381 // Mips Operand, Complex Patterns and Transformations Definitions.
382 //===----------------------------------------------------------------------===//
384 class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [],
385 int Offset = 0> : AsmOperandClass {
386 let Name = "ConstantUImm" # Bits # "_" # Offset;
387 let RenderMethod = "addConstantUImmOperands<" # Bits # ", " # Offset # ">";
388 let PredicateMethod = "isConstantUImm<" # Bits # ", " # Offset # ">";
389 let SuperClasses = Supers;
390 let DiagnosticType = "UImm" # Bits # "_" # Offset;
393 def ConstantUImm4AsmOperandClass
394 : ConstantUImmAsmOperandClass<4, []>;
395 def ConstantUImm3AsmOperandClass
396 : ConstantUImmAsmOperandClass<3, [ConstantUImm4AsmOperandClass]>;
397 def ConstantUImm2Plus1AsmOperandClass
398 : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass], 1>;
399 def ConstantUImm2AsmOperandClass
400 : ConstantUImmAsmOperandClass<2, [ConstantUImm3AsmOperandClass]>;
401 def ConstantUImm1AsmOperandClass
402 : ConstantUImmAsmOperandClass<1, [ConstantUImm2AsmOperandClass]>;
403 def ConstantImmzAsmOperandClass : AsmOperandClass {
404 let Name = "ConstantImmz";
405 let RenderMethod = "addConstantUImmOperands<1>";
406 let PredicateMethod = "isConstantImmz";
407 let SuperClasses = [ConstantUImm1AsmOperandClass];
408 let DiagnosticType = "Immz";
411 def MipsJumpTargetAsmOperand : AsmOperandClass {
412 let Name = "JumpTarget";
413 let ParserMethod = "parseJumpTarget";
414 let PredicateMethod = "isImm";
415 let RenderMethod = "addImmOperands";
418 // Instruction operand types
419 def jmptarget : Operand<OtherVT> {
420 let EncoderMethod = "getJumpTargetOpValue";
421 let ParserMatchClass = MipsJumpTargetAsmOperand;
423 def brtarget : Operand<OtherVT> {
424 let EncoderMethod = "getBranchTargetOpValue";
425 let OperandType = "OPERAND_PCREL";
426 let DecoderMethod = "DecodeBranchTarget";
427 let ParserMatchClass = MipsJumpTargetAsmOperand;
429 def calltarget : Operand<iPTR> {
430 let EncoderMethod = "getJumpTargetOpValue";
431 let ParserMatchClass = MipsJumpTargetAsmOperand;
434 def imm64: Operand<i64>;
436 def simm9 : Operand<i32>;
437 def simm10 : Operand<i32>;
438 def simm11 : Operand<i32>;
440 def simm16 : Operand<i32> {
441 let DecoderMethod= "DecodeSimm16";
444 def simm19_lsl2 : Operand<i32> {
445 let EncoderMethod = "getSimm19Lsl2Encoding";
446 let DecoderMethod = "DecodeSimm19Lsl2";
447 let ParserMatchClass = MipsJumpTargetAsmOperand;
450 def simm18_lsl3 : Operand<i32> {
451 let EncoderMethod = "getSimm18Lsl3Encoding";
452 let DecoderMethod = "DecodeSimm18Lsl3";
453 let ParserMatchClass = MipsJumpTargetAsmOperand;
456 def simm20 : Operand<i32> {
459 def uimm20 : Operand<i32> {
462 def MipsUImm10AsmOperand : AsmOperandClass {
464 let RenderMethod = "addImmOperands";
465 let ParserMethod = "parseImm";
466 let PredicateMethod = "isUImm<10>";
469 def uimm10 : Operand<i32> {
470 let ParserMatchClass = MipsUImm10AsmOperand;
473 def simm16_64 : Operand<i64> {
474 let DecoderMethod = "DecodeSimm16";
478 def uimmz : Operand<i32> {
479 let PrintMethod = "printUnsignedImm";
480 let ParserMatchClass = ConstantImmzAsmOperandClass;
484 foreach I = {1, 2, 3, 4} in
485 def uimm # I : Operand<i32> {
486 let PrintMethod = "printUnsignedImm";
487 let ParserMatchClass =
488 !cast<AsmOperandClass>("ConstantUImm" # I # "AsmOperandClass");
491 def uimm2_plus1 : Operand<i32> {
492 let PrintMethod = "printUnsignedImm";
493 let EncoderMethod = "getUImmWithOffsetEncoding<2, 1>";
494 let DecoderMethod = "DecodeUImmWithOffset<2, 1>";
495 let ParserMatchClass = ConstantUImm2Plus1AsmOperandClass;
498 def uimm5 : Operand<i32> {
499 let PrintMethod = "printUnsignedImm";
502 def uimm6 : Operand<i32> {
503 let PrintMethod = "printUnsignedImm";
506 def uimm16 : Operand<i32> {
507 let PrintMethod = "printUnsignedImm";
510 def pcrel16 : Operand<i32> {
513 def MipsMemAsmOperand : AsmOperandClass {
515 let ParserMethod = "parseMemOperand";
518 def MipsMemSimm9AsmOperand : AsmOperandClass {
519 let Name = "MemOffsetSimm9";
520 let SuperClasses = [MipsMemAsmOperand];
521 let RenderMethod = "addMemOperands";
522 let ParserMethod = "parseMemOperand";
523 let PredicateMethod = "isMemWithSimmOffset<9>";
526 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
527 let Name = "MemOffsetSimm9GPR";
528 let SuperClasses = [MipsMemAsmOperand];
529 let RenderMethod = "addMemOperands";
530 let ParserMethod = "parseMemOperand";
531 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
534 def MipsMemSimm11AsmOperand : AsmOperandClass {
535 let Name = "MemOffsetSimm11";
536 let SuperClasses = [MipsMemAsmOperand];
537 let RenderMethod = "addMemOperands";
538 let ParserMethod = "parseMemOperand";
539 let PredicateMethod = "isMemWithSimmOffset<11>";
542 def MipsMemSimm16AsmOperand : AsmOperandClass {
543 let Name = "MemOffsetSimm16";
544 let SuperClasses = [MipsMemAsmOperand];
545 let RenderMethod = "addMemOperands";
546 let ParserMethod = "parseMemOperand";
547 let PredicateMethod = "isMemWithSimmOffset<16>";
550 def MipsInvertedImmoperand : AsmOperandClass {
552 let RenderMethod = "addImmOperands";
553 let ParserMethod = "parseInvNum";
556 def InvertedImOperand : Operand<i32> {
557 let ParserMatchClass = MipsInvertedImmoperand;
560 def InvertedImOperand64 : Operand<i64> {
561 let ParserMatchClass = MipsInvertedImmoperand;
564 class mem_generic : Operand<iPTR> {
565 let PrintMethod = "printMemOperand";
566 let MIOperandInfo = (ops ptr_rc, simm16);
567 let EncoderMethod = "getMemEncoding";
568 let ParserMatchClass = MipsMemAsmOperand;
569 let OperandType = "OPERAND_MEMORY";
573 def mem : mem_generic;
575 // MSA specific address operand
576 def mem_msa : mem_generic {
577 let MIOperandInfo = (ops ptr_rc, simm10);
578 let EncoderMethod = "getMSAMemEncoding";
581 def mem_simm9 : mem_generic {
582 let MIOperandInfo = (ops ptr_rc, simm9);
583 let EncoderMethod = "getMemEncoding";
584 let ParserMatchClass = MipsMemSimm9AsmOperand;
587 def mem_simm9gpr : mem_generic {
588 let MIOperandInfo = (ops ptr_rc, simm9);
589 let EncoderMethod = "getMemEncoding";
590 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
593 def mem_simm11 : mem_generic {
594 let MIOperandInfo = (ops ptr_rc, simm11);
595 let EncoderMethod = "getMemEncoding";
596 let ParserMatchClass = MipsMemSimm11AsmOperand;
599 def mem_simm16 : mem_generic {
600 let MIOperandInfo = (ops ptr_rc, simm16);
601 let EncoderMethod = "getMemEncoding";
602 let ParserMatchClass = MipsMemSimm16AsmOperand;
605 def mem_ea : Operand<iPTR> {
606 let PrintMethod = "printMemOperandEA";
607 let MIOperandInfo = (ops ptr_rc, simm16);
608 let EncoderMethod = "getMemEncoding";
609 let OperandType = "OPERAND_MEMORY";
612 def PtrRC : Operand<iPTR> {
613 let MIOperandInfo = (ops ptr_rc);
614 let DecoderMethod = "DecodePtrRegisterClass";
615 let ParserMatchClass = GPR32AsmOperand;
618 // size operand of ext instruction
619 def size_ext : Operand<i32> {
620 let EncoderMethod = "getSizeExtEncoding";
621 let DecoderMethod = "DecodeExtSize";
624 // size operand of ins instruction
625 def size_ins : Operand<i32> {
626 let EncoderMethod = "getSizeInsEncoding";
627 let DecoderMethod = "DecodeInsSize";
630 // Transformation Function - get the lower 16 bits.
631 def LO16 : SDNodeXForm<imm, [{
632 return getImm(N, N->getZExtValue() & 0xFFFF);
635 // Transformation Function - get the higher 16 bits.
636 def HI16 : SDNodeXForm<imm, [{
637 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
641 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
643 // Node immediate is zero (e.g. insve.d)
644 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
646 // Node immediate fits as 16-bit sign extended on target immediate.
648 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
650 // Node immediate fits as 16-bit sign extended on target immediate.
652 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
654 // Node immediate fits as 15-bit sign extended on target immediate.
656 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
658 // Node immediate fits as 16-bit zero extended on target immediate.
659 // The LO16 param means that only the lower 16 bits of the node
660 // immediate are caught.
662 def immZExt16 : PatLeaf<(imm), [{
663 if (N->getValueType(0) == MVT::i32)
664 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
666 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
669 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
670 def immLow16Zero : PatLeaf<(imm), [{
671 int64_t Val = N->getSExtValue();
672 return isInt<32>(Val) && !(Val & 0xffff);
675 // shamt field must fit in 5 bits.
676 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
678 // True if (N + 1) fits in 16-bit field.
679 def immSExt16Plus1 : PatLeaf<(imm), [{
680 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
683 // Mips Address Mode! SDNode frameindex could possibily be a match
684 // since load and store instructions from stack used it.
686 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
689 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
692 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
695 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
697 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
699 //===----------------------------------------------------------------------===//
700 // Instructions specific format
701 //===----------------------------------------------------------------------===//
703 // Arithmetic and logical instructions with 3 register operands.
704 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
705 InstrItinClass Itin = NoItinerary,
706 SDPatternOperator OpNode = null_frag>:
707 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
708 !strconcat(opstr, "\t$rd, $rs, $rt"),
709 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
710 let isCommutable = isComm;
711 let isReMaterializable = 1;
712 let TwoOperandAliasConstraint = "$rd = $rs";
715 // Arithmetic and logical instructions with 2 register operands.
716 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
717 InstrItinClass Itin = NoItinerary,
718 SDPatternOperator imm_type = null_frag,
719 SDPatternOperator OpNode = null_frag> :
720 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
721 !strconcat(opstr, "\t$rt, $rs, $imm16"),
722 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
724 let isReMaterializable = 1;
725 let TwoOperandAliasConstraint = "$rs = $rt";
728 // Arithmetic Multiply ADD/SUB
729 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
730 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
731 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
732 let Defs = [HI0, LO0];
733 let Uses = [HI0, LO0];
734 let isCommutable = isComm;
738 class LogicNOR<string opstr, RegisterOperand RO>:
739 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
740 !strconcat(opstr, "\t$rd, $rs, $rt"),
741 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
742 let isCommutable = 1;
746 class shift_rotate_imm<string opstr, Operand ImmOpnd,
747 RegisterOperand RO, InstrItinClass itin,
748 SDPatternOperator OpNode = null_frag,
749 SDPatternOperator PF = null_frag> :
750 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
751 !strconcat(opstr, "\t$rd, $rt, $shamt"),
752 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
753 let TwoOperandAliasConstraint = "$rt = $rd";
756 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
757 SDPatternOperator OpNode = null_frag>:
758 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
759 !strconcat(opstr, "\t$rd, $rt, $rs"),
760 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
763 // Load Upper Immediate
764 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
765 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
766 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
767 let hasSideEffects = 0;
768 let isReMaterializable = 1;
772 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
773 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
774 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
775 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
776 let DecoderMethod = "DecodeMem";
777 let canFoldAsLoad = 1;
781 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
782 SDPatternOperator OpNode = null_frag,
783 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
784 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
785 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
786 let DecoderMethod = "DecodeMem";
790 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
791 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
792 StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
794 // Load/Store Left/Right
795 let canFoldAsLoad = 1 in
796 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
797 InstrItinClass Itin> :
798 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
799 !strconcat(opstr, "\t$rt, $addr"),
800 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
801 let DecoderMethod = "DecodeMem";
802 string Constraints = "$src = $rt";
805 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
806 InstrItinClass Itin> :
807 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
808 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
809 let DecoderMethod = "DecodeMem";
813 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
814 SDPatternOperator OpNode= null_frag> :
815 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
816 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
817 let DecoderMethod = "DecodeFMem2";
821 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
822 SDPatternOperator OpNode= null_frag> :
823 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
824 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
825 let DecoderMethod = "DecodeFMem2";
830 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
831 SDPatternOperator OpNode= null_frag> :
832 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
833 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
834 let DecoderMethod = "DecodeFMem3";
838 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
839 SDPatternOperator OpNode= null_frag> :
840 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
841 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
842 let DecoderMethod = "DecodeFMem3";
846 // Conditional Branch
847 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
848 RegisterOperand RO, bit DelaySlot = 1> :
849 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
850 !strconcat(opstr, "\t$rs, $rt, $offset"),
851 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
854 let isTerminator = 1;
855 let hasDelaySlot = DelaySlot;
859 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
860 RegisterOperand RO, bit DelaySlot = 1> :
861 InstSE<(outs), (ins RO:$rs, opnd:$offset),
862 !strconcat(opstr, "\t$rs, $offset"),
863 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
866 let isTerminator = 1;
867 let hasDelaySlot = DelaySlot;
872 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
873 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
874 !strconcat(opstr, "\t$rd, $rs, $rt"),
875 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
876 II_SLT_SLTU, FrmR, opstr>;
878 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
880 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
881 !strconcat(opstr, "\t$rt, $rs, $imm16"),
882 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
883 II_SLTI_SLTIU, FrmI, opstr>;
886 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
887 SDPatternOperator targetoperator, string bopstr> :
888 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
889 [(operator targetoperator:$target)], II_J, FrmJ, bopstr> {
892 let hasDelaySlot = 1;
893 let DecoderMethod = "DecodeJumpTarget";
897 // Unconditional branch
898 class UncondBranch<Instruction BEQInst> :
899 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
900 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
902 let isTerminator = 1;
904 let hasDelaySlot = 1;
905 let AdditionalPredicates = [RelocPIC];
909 // Base class for indirect branch and return instruction classes.
910 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
911 class JumpFR<string opstr, RegisterOperand RO,
912 SDPatternOperator operator = null_frag>:
913 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
917 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
919 let isIndirectBranch = 1;
922 // Jump and Link (Call)
923 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
924 class JumpLink<string opstr, DAGOperand opnd> :
925 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
926 [(MipsJmpLink imm:$target)], II_JAL, FrmJ, opstr> {
927 let DecoderMethod = "DecodeJumpTarget";
930 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
931 Register RetReg, RegisterOperand ResRO = RO>:
932 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
933 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
935 class JumpLinkReg<string opstr, RegisterOperand RO>:
936 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
937 [], II_JALR, FrmR, opstr>;
939 class BGEZAL_FT<string opstr, DAGOperand opnd,
940 RegisterOperand RO, bit DelaySlot = 1> :
941 InstSE<(outs), (ins RO:$rs, opnd:$offset),
942 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
943 let hasDelaySlot = DelaySlot;
948 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
949 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
950 class TailCall<Instruction JumpInst> :
951 PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
952 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
954 class TailCallReg<RegisterOperand RO, Instruction JRInst,
955 RegisterOperand ResRO = RO> :
956 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
957 PseudoInstExpansion<(JRInst ResRO:$rs)>;
960 class BAL_BR_Pseudo<Instruction RealInst> :
961 PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
962 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
964 let isTerminator = 1;
966 let hasDelaySlot = 1;
971 class SYS_FT<string opstr> :
972 InstSE<(outs), (ins uimm20:$code_),
973 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
975 class BRK_FT<string opstr> :
976 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
977 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
981 class ER_FT<string opstr> :
982 InstSE<(outs), (ins),
983 opstr, [], NoItinerary, FrmOther, opstr>;
986 class DEI_FT<string opstr, RegisterOperand RO> :
987 InstSE<(outs RO:$rt), (ins),
988 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
991 class WAIT_FT<string opstr> :
992 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
995 let hasSideEffects = 1 in
996 class SYNC_FT<string opstr> :
997 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
998 NoItinerary, FrmOther, opstr>;
1000 class SYNCI_FT<string opstr> :
1001 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
1002 NoItinerary, FrmOther, opstr> {
1003 let hasSideEffects = 1;
1004 let DecoderMethod = "DecodeSyncI";
1007 let hasSideEffects = 1 in
1008 class TEQ_FT<string opstr, RegisterOperand RO> :
1009 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
1010 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
1013 class TEQI_FT<string opstr, RegisterOperand RO> :
1014 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
1015 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
1017 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
1018 list<Register> DefRegs> :
1019 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
1020 itin, FrmR, opstr> {
1021 let isCommutable = 1;
1023 let hasSideEffects = 0;
1026 // Pseudo multiply/divide instruction with explicit accumulator register
1028 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
1029 SDPatternOperator OpNode, InstrItinClass Itin,
1030 bit IsComm = 1, bit HasSideEffects = 0,
1031 bit UsesCustomInserter = 0> :
1032 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
1033 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
1034 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
1035 let isCommutable = IsComm;
1036 let hasSideEffects = HasSideEffects;
1037 let usesCustomInserter = UsesCustomInserter;
1040 // Pseudo multiply add/sub instruction with explicit accumulator register
1042 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
1043 InstrItinClass itin>
1044 : PseudoSE<(outs ACC64:$ac),
1045 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
1047 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
1049 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
1050 string Constraints = "$acin = $ac";
1053 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1054 list<Register> DefRegs> :
1055 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1056 [], itin, FrmR, opstr> {
1061 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
1062 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
1063 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
1065 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1066 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1068 let Uses = [UseReg];
1069 let hasSideEffects = 0;
1072 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
1073 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
1074 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
1077 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1078 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1081 let hasSideEffects = 0;
1084 class EffectiveAddress<string opstr, RegisterOperand RO> :
1085 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1086 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
1087 !strconcat(opstr, "_lea")> {
1088 let isCodeGenOnly = 1;
1089 let DecoderMethod = "DecodeMem";
1092 // Count Leading Ones/Zeros in Word
1093 class CountLeading0<string opstr, RegisterOperand RO>:
1094 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1095 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
1097 class CountLeading1<string opstr, RegisterOperand RO>:
1098 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1099 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
1101 // Sign Extend in Register.
1102 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1103 InstrItinClass itin> :
1104 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1105 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1108 class SubwordSwap<string opstr, RegisterOperand RO,
1109 InstrItinClass itin = NoItinerary>:
1110 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1112 let hasSideEffects = 0;
1116 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1117 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
1118 II_RDHWR, FrmR, "rdhwr">;
1121 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1122 SDPatternOperator Op = null_frag>:
1123 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1124 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1125 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
1126 FrmR, opstr>, ISA_MIPS32R2;
1128 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1129 SDPatternOperator Op = null_frag>:
1130 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1131 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1132 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1133 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
1134 let Constraints = "$src = $rt";
1137 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1138 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1139 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1140 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1142 // Atomic Compare & Swap.
1143 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1144 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1145 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1147 class LLBase<string opstr, RegisterOperand RO> :
1148 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1149 [], NoItinerary, FrmI> {
1150 let DecoderMethod = "DecodeMem";
1154 class SCBase<string opstr, RegisterOperand RO> :
1155 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1156 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1157 let DecoderMethod = "DecodeMem";
1159 let Constraints = "$rt = $dst";
1162 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1163 InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
1164 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1166 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1167 InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
1168 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1170 class TrapBase<Instruction RealInst>
1171 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1172 PseudoInstExpansion<(RealInst 0, 0)> {
1174 let isTerminator = 1;
1175 let isCodeGenOnly = 1;
1178 //===----------------------------------------------------------------------===//
1179 // Pseudo instructions
1180 //===----------------------------------------------------------------------===//
1183 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1184 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1186 let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, hasSideEffects=1 in
1187 def ERet : PseudoSE<(outs), (ins), [(MipsERet)]>;
1189 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1190 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1191 [(callseq_start timm:$amt)]>;
1192 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1193 [(callseq_end timm:$amt1, timm:$amt2)]>;
1196 let usesCustomInserter = 1 in {
1197 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1198 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1199 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1200 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1201 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1202 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1203 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1204 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1205 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1206 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1207 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1208 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1209 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1210 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1211 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1212 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1213 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1214 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1216 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1217 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1218 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1220 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1221 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1222 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1225 /// Pseudo instructions for loading and storing accumulator registers.
1226 let isPseudo = 1, isCodeGenOnly = 1 in {
1227 def LOAD_ACC64 : Load<"", ACC64>;
1228 def STORE_ACC64 : Store<"", ACC64>;
1231 // We need these two pseudo instructions to avoid offset calculation for long
1232 // branches. See the comment in file MipsLongBranch.cpp for detailed
1235 // Expands to: lui $dst, %hi($tgt - $baltgt)
1236 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1237 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1239 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1240 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1241 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1243 //===----------------------------------------------------------------------===//
1244 // Instruction definition
1245 //===----------------------------------------------------------------------===//
1246 //===----------------------------------------------------------------------===//
1247 // MipsI Instructions
1248 //===----------------------------------------------------------------------===//
1250 /// Arithmetic Instructions (ALU Immediate)
1251 let AdditionalPredicates = [NotInMicroMips] in {
1252 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1253 II_ADDIU, immSExt16, add>,
1254 ADDI_FM<0x9>, IsAsCheapAsAMove;
1256 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1257 ISA_MIPS1_NOT_32R6_64R6;
1258 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1260 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1262 let AdditionalPredicates = [NotInMicroMips] in {
1263 def ANDi : MMRel, StdMMR6Rel,
1264 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
1267 def ORi : MMRel, StdMMR6Rel,
1268 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
1270 def XORi : MMRel, StdMMR6Rel,
1271 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
1273 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1274 let AdditionalPredicates = [NotInMicroMips] in {
1275 /// Arithmetic Instructions (3-Operand, R-Type)
1276 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1278 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1281 let Defs = [HI0, LO0] in
1282 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1283 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1284 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1285 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1286 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1287 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1288 let AdditionalPredicates = [NotInMicroMips] in {
1289 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1291 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1293 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1296 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1298 /// Shift Instructions
1299 let AdditionalPredicates = [NotInMicroMips] in {
1300 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1301 immZExt5>, SRA_FM<0, 0>;
1302 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1303 immZExt5>, SRA_FM<2, 0>;
1305 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1306 immZExt5>, SRA_FM<3, 0>;
1307 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1309 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1311 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1314 // Rotate Instructions
1315 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1317 SRA_FM<2, 1>, ISA_MIPS32R2;
1318 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1319 SRLV_FM<6, 1>, ISA_MIPS32R2;
1321 /// Load and Store Instructions
1323 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1324 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1326 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1328 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1329 let AdditionalPredicates = [NotInMicroMips] in {
1330 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1333 def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
1335 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1336 let AdditionalPredicates = [NotInMicroMips] in {
1337 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1340 /// load/store left/right
1341 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1342 AdditionalPredicates = [NotInMicroMips] in {
1343 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1344 ISA_MIPS1_NOT_32R6_64R6;
1345 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1346 ISA_MIPS1_NOT_32R6_64R6;
1347 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1348 ISA_MIPS1_NOT_32R6_64R6;
1349 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1350 ISA_MIPS1_NOT_32R6_64R6;
1353 let AdditionalPredicates = [NotInMicroMips] in {
1354 // COP2 Memory Instructions
1355 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1356 ISA_MIPS1_NOT_32R6_64R6;
1357 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1358 ISA_MIPS1_NOT_32R6_64R6;
1359 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1360 ISA_MIPS2_NOT_32R6_64R6;
1361 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1362 ISA_MIPS2_NOT_32R6_64R6;
1364 // COP3 Memory Instructions
1365 let DecoderNamespace = "COP3_" in {
1366 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1367 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1368 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1370 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1375 def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1376 def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1378 let AdditionalPredicates = [NotInMicroMips] in {
1379 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1380 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1381 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1382 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1383 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1384 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1387 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1388 ISA_MIPS2_NOT_32R6_64R6;
1389 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1390 ISA_MIPS2_NOT_32R6_64R6;
1391 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1392 ISA_MIPS2_NOT_32R6_64R6;
1393 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1394 ISA_MIPS2_NOT_32R6_64R6;
1395 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1396 ISA_MIPS2_NOT_32R6_64R6;
1397 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1398 ISA_MIPS2_NOT_32R6_64R6;
1400 let AdditionalPredicates = [NotInMicroMips] in {
1401 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
1403 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1404 def TRAP : TrapBase<BREAK>;
1405 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1407 let AdditionalPredicates = [NotInMicroMips] in {
1408 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
1409 def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
1411 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
1413 let AdditionalPredicates = [NotInMicroMips] in {
1414 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1416 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1418 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1419 AdditionalPredicates = [NotInMicroMips] in {
1420 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1422 /// Load-linked, Store-conditional
1423 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1424 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1427 /// Jump and Branch Instructions
1428 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1429 AdditionalRequires<[RelocStatic]>, IsBranch;
1430 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1431 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1432 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1433 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1434 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1435 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1436 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1437 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1439 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1440 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1441 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1443 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1444 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1445 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1447 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1448 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1449 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1451 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1452 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1453 def B : UncondBranch<BEQ>;
1455 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1456 let AdditionalPredicates = [NotInMicroMips] in {
1457 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1458 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1461 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1462 ISA_MIPS32_NOT_32R6_64R6;
1463 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1464 ISA_MIPS1_NOT_32R6_64R6;
1465 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1466 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1467 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1468 ISA_MIPS1_NOT_32R6_64R6;
1469 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1470 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1471 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1472 def TAILCALL : TailCall<J>;
1473 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1475 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1476 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1477 class PseudoIndirectBranchBase<RegisterOperand RO> :
1478 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1479 II_IndirectBranchPseudo> {
1482 let hasDelaySlot = 1;
1484 let isIndirectBranch = 1;
1487 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1489 // Return instructions are matched as a RetRA instruction, then are expanded
1490 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1491 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1493 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1494 [], II_ReturnPseudo> {
1495 let isTerminator = 1;
1497 let hasDelaySlot = 1;
1499 let isCodeGenOnly = 1;
1501 let hasExtraSrcRegAllocReq = 1;
1504 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1506 // Exception handling related node and instructions.
1507 // The conversion sequence is:
1508 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1509 // MIPSeh_return -> (stack change + indirect branch)
1511 // MIPSeh_return takes the place of regular return instruction
1512 // but takes two arguments (V1, V0) which are used for storing
1513 // the offset and return address respectively.
1514 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1516 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1517 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1519 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1520 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1521 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1522 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1524 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1527 /// Multiply and Divide Instructions.
1528 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1529 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1530 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1531 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1532 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1533 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1534 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1535 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1537 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1538 ISA_MIPS1_NOT_32R6_64R6;
1539 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1540 ISA_MIPS1_NOT_32R6_64R6;
1541 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1542 AdditionalPredicates = [NotInMicroMips] in {
1543 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1544 ISA_MIPS1_NOT_32R6_64R6;
1545 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1546 ISA_MIPS1_NOT_32R6_64R6;
1549 /// Sign Ext In Register Instructions.
1550 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1551 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1552 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1553 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1556 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1557 ISA_MIPS32_NOT_32R6_64R6;
1558 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1559 ISA_MIPS32_NOT_32R6_64R6;
1561 let AdditionalPredicates = [NotInMicroMips] in {
1562 /// Word Swap Bytes Within Halfwords
1563 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
1568 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1570 // FrameIndexes are legalized when they are operands from load/store
1571 // instructions. The same not happens for stack address copies, so an
1572 // add op with mem ComplexPattern is used and the stack address copy
1573 // can be matched. It's similar to Sparc LEA_ADDRi
1574 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1577 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1578 ISA_MIPS32_NOT_32R6_64R6;
1579 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1580 ISA_MIPS32_NOT_32R6_64R6;
1581 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1582 ISA_MIPS32_NOT_32R6_64R6;
1583 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1584 ISA_MIPS32_NOT_32R6_64R6;
1586 let AdditionalPredicates = [NotDSP] in {
1587 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1588 ISA_MIPS1_NOT_32R6_64R6;
1589 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1590 ISA_MIPS1_NOT_32R6_64R6;
1591 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1592 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1593 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1594 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1595 ISA_MIPS32_NOT_32R6_64R6;
1596 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1597 ISA_MIPS32_NOT_32R6_64R6;
1598 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1599 ISA_MIPS32_NOT_32R6_64R6;
1600 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1601 ISA_MIPS32_NOT_32R6_64R6;
1604 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1605 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1606 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1607 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1608 let AdditionalPredicates = [NotInMicroMips] in {
1609 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1611 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1612 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1614 /// Move Control Registers From/To CPU Registers
1615 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1616 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1617 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
1618 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1620 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1622 def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop">, BARRIER_FM<1>;
1623 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1624 def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1626 // JR_HB and JALR_HB are defined here using the new style naming
1627 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1628 // and because of that it doesn't follow the naming convention of the
1629 // rest of the file. To avoid a mixture of old vs new style, the new
1630 // style was chosen.
1631 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1632 dag OutOperandList = (outs);
1633 dag InOperandList = (ins GPROpnd:$rs);
1634 string AsmString = !strconcat(instr_asm, "\t$rs");
1635 list<dag> Pattern = [];
1638 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1639 dag OutOperandList = (outs GPROpnd:$rd);
1640 dag InOperandList = (ins GPROpnd:$rs);
1641 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1642 list<dag> Pattern = [];
1645 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1646 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1648 let isIndirectBranch=1;
1654 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1655 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1656 let isIndirectBranch=1;
1660 class JR_HB_ENC : JR_HB_FM<8>;
1661 class JALR_HB_ENC : JALR_HB_FM<9>;
1663 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1664 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1666 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1668 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1669 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1670 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1671 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1673 class CacheOp<string instr_asm, Operand MemOpnd> :
1674 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1675 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1677 let DecoderMethod = "DecodeCacheOp";
1680 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1681 INSN_MIPS3_32_NOT_32R6_64R6;
1682 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1683 INSN_MIPS3_32_NOT_32R6_64R6;
1685 //===----------------------------------------------------------------------===//
1686 // Instruction aliases
1687 //===----------------------------------------------------------------------===//
1688 def : MipsInstAlias<"move $dst, $src",
1689 (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1691 let AdditionalPredicates = [NotInMicroMips];
1693 def : MipsInstAlias<"move $dst, $src",
1694 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1696 let AdditionalPredicates = [NotInMicroMips];
1698 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1699 ISA_MIPS1_NOT_32R6_64R6;
1700 def : MipsInstAlias<"addu $rs, $rt, $imm",
1701 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1702 def : MipsInstAlias<"addu $rs, $imm",
1703 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1704 def : MipsInstAlias<"add $rs, $rt, $imm",
1705 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1706 ISA_MIPS1_NOT_32R6_64R6;
1707 def : MipsInstAlias<"add $rs, $imm",
1708 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1709 ISA_MIPS1_NOT_32R6_64R6;
1710 def : MipsInstAlias<"and $rs, $rt, $imm",
1711 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1712 def : MipsInstAlias<"and $rs, $imm",
1713 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1714 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1715 let Predicates = [NotInMicroMips] in {
1716 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1718 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1719 def : MipsInstAlias<"not $rt, $rs",
1720 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1721 def : MipsInstAlias<"neg $rt, $rs",
1722 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1723 def : MipsInstAlias<"negu $rt",
1724 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1725 def : MipsInstAlias<"negu $rt, $rs",
1726 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1727 def : MipsInstAlias<"slt $rs, $rt, $imm",
1728 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1729 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1730 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1731 def : MipsInstAlias<"xor $rs, $rt, $imm",
1732 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1733 def : MipsInstAlias<"xor $rs, $imm",
1734 (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1735 def : MipsInstAlias<"or $rs, $rt, $imm",
1736 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1737 def : MipsInstAlias<"or $rs, $imm",
1738 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1739 let AdditionalPredicates = [NotInMicroMips] in {
1740 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1742 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
1743 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1744 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
1745 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1746 let AdditionalPredicates = [NotInMicroMips] in {
1747 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1749 def : MipsInstAlias<"bnez $rs,$offset",
1750 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1751 def : MipsInstAlias<"bnezl $rs,$offset",
1752 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1753 def : MipsInstAlias<"beqz $rs,$offset",
1754 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1755 def : MipsInstAlias<"beqzl $rs,$offset",
1756 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1757 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1759 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1760 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1761 let AdditionalPredicates = [NotInMicroMips] in {
1762 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1764 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1765 let AdditionalPredicates = [NotInMicroMips] in {
1766 def : MipsInstAlias<"teq $rs, $rt",
1767 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1768 def : MipsInstAlias<"tge $rs, $rt",
1769 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1770 def : MipsInstAlias<"tgeu $rs, $rt",
1771 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1772 def : MipsInstAlias<"tlt $rs, $rt",
1773 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1774 def : MipsInstAlias<"tltu $rs, $rt",
1775 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1776 def : MipsInstAlias<"tne $rs, $rt",
1777 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1779 def : MipsInstAlias<"sll $rd, $rt, $rs",
1780 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1781 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1782 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1783 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1784 def : MipsInstAlias<"sub $rs, $imm",
1785 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1786 0>, ISA_MIPS1_NOT_32R6_64R6;
1787 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1788 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1789 InvertedImOperand:$imm), 0>;
1790 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1791 InvertedImOperand:$imm), 0>;
1792 def : MipsInstAlias<"sra $rd, $rt, $rs",
1793 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1794 def : MipsInstAlias<"srl $rd, $rt, $rs",
1795 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1796 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1797 def : MipsInstAlias<"sync",
1798 (SYNC 0), 1>, ISA_MIPS2;
1799 //===----------------------------------------------------------------------===//
1800 // Assembler Pseudo Instructions
1801 //===----------------------------------------------------------------------===//
1803 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
1804 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1805 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1806 def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
1808 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
1809 RegisterOperand RO> :
1810 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1811 !strconcat(instr_asm, "\t$rt, $addr")> ;
1812 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
1814 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
1815 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1816 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1817 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
1819 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1821 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1824 def NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
1825 "nor\t$rs, $rt, $imm"> ;
1827 let hasDelaySlot = 1 in {
1828 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1829 (ins imm64:$imm64, brtarget:$offset),
1830 "bne\t$rt, $imm64, $offset">;
1831 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1832 (ins imm64:$imm64, brtarget:$offset),
1833 "beq\t$rt, $imm64, $offset">;
1835 class CondBranchPseudo<string instr_asm> :
1836 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
1838 !strconcat(instr_asm, "\t$rs, $rt, $offset")>;
1841 def BLT : CondBranchPseudo<"blt">;
1842 def BLE : CondBranchPseudo<"ble">;
1843 def BGE : CondBranchPseudo<"bge">;
1844 def BGT : CondBranchPseudo<"bgt">;
1845 def BLTU : CondBranchPseudo<"bltu">;
1846 def BLEU : CondBranchPseudo<"bleu">;
1847 def BGEU : CondBranchPseudo<"bgeu">;
1848 def BGTU : CondBranchPseudo<"bgtu">;
1849 def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
1850 def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
1851 def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
1852 def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
1853 def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
1854 def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
1855 def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
1856 def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
1858 class CondBranchImmPseudo<string instr_asm> :
1859 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset),
1860 !strconcat(instr_asm, "\t$rs, $imm, $offset")>;
1862 def BLTImmMacro : CondBranchImmPseudo<"blt">;
1863 def BLEImmMacro : CondBranchImmPseudo<"ble">;
1864 def BGEImmMacro : CondBranchImmPseudo<"bge">;
1865 def BGTImmMacro : CondBranchImmPseudo<"bgt">;
1866 def BLTUImmMacro : CondBranchImmPseudo<"bltu">;
1867 def BLEUImmMacro : CondBranchImmPseudo<"bleu">;
1868 def BGEUImmMacro : CondBranchImmPseudo<"bgeu">;
1869 def BGTUImmMacro : CondBranchImmPseudo<"bgtu">;
1870 def BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
1871 def BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
1872 def BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
1873 def BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
1874 def BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
1875 def BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
1876 def BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
1877 def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
1879 // FIXME: Predicates are removed because instructions are matched regardless of
1880 // predicates, because PredicateControl was not in the hierarchy. This was
1881 // done to emit more precise error message from expansion function.
1882 // Once the tablegen-erated errors are made better, this needs to be fixed and
1883 // predicates needs to be restored.
1885 def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1886 "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
1888 def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1889 "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
1891 def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1892 "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
1894 def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1895 "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
1897 def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1898 "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
1900 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1901 "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
1903 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1904 "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
1906 //===----------------------------------------------------------------------===//
1907 // Arbitrary patterns that map to one or more instructions
1908 //===----------------------------------------------------------------------===//
1910 // Load/store pattern templates.
1911 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1912 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1914 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1915 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1918 let AdditionalPredicates = [NotInMicroMips] in {
1919 def : MipsPat<(i32 immSExt16:$in),
1920 (ADDiu ZERO, imm:$in)>;
1921 def : MipsPat<(i32 immZExt16:$in),
1922 (ORi ZERO, imm:$in)>;
1924 def : MipsPat<(i32 immLow16Zero:$in),
1925 (LUi (HI16 imm:$in))>;
1927 // Arbitrary immediates
1928 def : MipsPat<(i32 imm:$imm),
1929 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1931 // Carry MipsPatterns
1932 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1933 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1934 let AdditionalPredicates = [NotDSP] in {
1935 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1936 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1937 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1938 (ADDiu GPR32:$src, imm:$imm)>;
1941 // Support multiplication for pre-Mips32 targets that don't have
1942 // the MUL instruction.
1943 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1944 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1945 ISA_MIPS1_NOT_32R6_64R6;
1948 def : MipsPat<(MipsSync (i32 immz)),
1949 (SYNC 0)>, ISA_MIPS2;
1952 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1953 (JAL tglobaladdr:$dst)>;
1954 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1955 (JAL texternalsym:$dst)>;
1956 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1957 // (JALR GPR32:$dst)>;
1960 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1961 (TAILCALL tglobaladdr:$dst)>;
1962 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1963 (TAILCALL texternalsym:$dst)>;
1965 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1966 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1967 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1968 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1969 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1970 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1972 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1973 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1974 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1975 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1976 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1977 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1979 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1980 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1981 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1982 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1983 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1984 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1985 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1986 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1987 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1988 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1991 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1992 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1993 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1994 (ADDiu GPR32:$gp, tconstpool:$in)>;
1997 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1998 MipsPat<(MipsWrapper RC:$gp, node:$in),
1999 (ADDiuOp RC:$gp, node:$in)>;
2001 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
2002 def : WrapperPat<tconstpool, ADDiu, GPR32>;
2003 def : WrapperPat<texternalsym, ADDiu, GPR32>;
2004 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
2005 def : WrapperPat<tjumptable, ADDiu, GPR32>;
2006 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
2008 let AdditionalPredicates = [NotInMicroMips] in {
2009 // Mips does not have "not", so we expand our way
2010 def : MipsPat<(not GPR32:$in),
2011 (NOR GPR32Opnd:$in, ZERO)>;
2015 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
2016 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
2017 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
2020 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
2023 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
2024 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
2025 Instruction SLTiuOp, Register ZEROReg> {
2026 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
2027 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
2028 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
2029 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
2031 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
2032 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
2033 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
2034 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
2035 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
2036 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
2037 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
2038 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
2039 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
2040 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
2041 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
2042 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
2044 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
2045 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
2046 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
2047 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
2049 def : MipsPat<(brcond RC:$cond, bb:$dst),
2050 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
2053 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
2055 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
2056 (BLEZ i32:$lhs, bb:$dst)>;
2057 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
2058 (BGEZ i32:$lhs, bb:$dst)>;
2061 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
2062 Instruction SLTuOp, Register ZEROReg> {
2063 def : MipsPat<(seteq RC:$lhs, 0),
2064 (SLTiuOp RC:$lhs, 1)>;
2065 def : MipsPat<(setne RC:$lhs, 0),
2066 (SLTuOp ZEROReg, RC:$lhs)>;
2067 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
2068 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
2069 def : MipsPat<(setne RC:$lhs, RC:$rhs),
2070 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
2073 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2074 def : MipsPat<(setle RC:$lhs, RC:$rhs),
2075 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
2076 def : MipsPat<(setule RC:$lhs, RC:$rhs),
2077 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
2080 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2081 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
2082 (SLTOp RC:$rhs, RC:$lhs)>;
2083 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
2084 (SLTuOp RC:$rhs, RC:$lhs)>;
2087 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2088 def : MipsPat<(setge RC:$lhs, RC:$rhs),
2089 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
2090 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
2091 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
2094 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
2095 Instruction SLTiuOp> {
2096 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
2097 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
2098 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
2099 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
2102 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
2103 defm : SetlePats<GPR32, SLT, SLTu>;
2104 defm : SetgtPats<GPR32, SLT, SLTu>;
2105 defm : SetgePats<GPR32, SLT, SLTu>;
2106 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
2109 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
2111 // Load halfword/word patterns.
2112 let AddedComplexity = 40 in {
2113 def : LoadRegImmPat<LBu, i32, zextloadi8>;
2114 def : LoadRegImmPat<LH, i32, sextloadi16>;
2115 let AdditionalPredicates = [NotInMicroMips] in {
2116 def : LoadRegImmPat<LW, i32, load>;
2120 // Atomic load patterns.
2121 def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>;
2122 def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>;
2123 def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>;
2125 // Atomic store patterns.
2126 def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>;
2127 def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>;
2128 def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>;
2130 //===----------------------------------------------------------------------===//
2131 // Floating Point Support
2132 //===----------------------------------------------------------------------===//
2134 include "MipsInstrFPU.td"
2135 include "Mips64InstrInfo.td"
2136 include "MipsCondMov.td"
2138 include "Mips32r6InstrInfo.td"
2139 include "Mips64r6InstrInfo.td"
2144 include "Mips16InstrFormats.td"
2145 include "Mips16InstrInfo.td"
2148 include "MipsDSPInstrFormats.td"
2149 include "MipsDSPInstrInfo.td"
2152 include "MipsMSAInstrFormats.td"
2153 include "MipsMSAInstrInfo.td"
2156 include "MipsEVAInstrFormats.td"
2157 include "MipsEVAInstrInfo.td"
2160 include "MicroMipsInstrFormats.td"
2161 include "MicroMipsInstrInfo.td"
2162 include "MicroMipsInstrFPU.td"
2165 include "MicroMips32r6InstrFormats.td"
2166 include "MicroMips32r6InstrInfo.td"
2169 include "MicroMips64r6InstrFormats.td"
2170 include "MicroMips64r6InstrInfo.td"
2173 include "MicroMipsDSPInstrFormats.td"
2174 include "MicroMipsDSPInstrInfo.td"