1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
172 AssemblerPredicate<"!FeatureN64">;
173 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
174 AssemblerPredicate<"FeatureMips16">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
191 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
192 let Predicates = [HasStdEnc];
196 bit isCommutable = 1;
213 bit isTerminator = 1;
216 bit hasExtraSrcRegAllocReq = 1;
217 bit isCodeGenOnly = 1;
220 class IsAsCheapAsAMove {
221 bit isAsCheapAsAMove = 1;
224 class NeverHasSideEffects {
225 bit neverHasSideEffects = 1;
228 //===----------------------------------------------------------------------===//
229 // Instruction format superclass
230 //===----------------------------------------------------------------------===//
232 include "MipsInstrFormats.td"
234 //===----------------------------------------------------------------------===//
235 // Mips Operand, Complex Patterns and Transformations Definitions.
236 //===----------------------------------------------------------------------===//
238 // Instruction operand types
239 def jmptarget : Operand<OtherVT> {
240 let EncoderMethod = "getJumpTargetOpValue";
242 def brtarget : Operand<OtherVT> {
243 let EncoderMethod = "getBranchTargetOpValue";
244 let OperandType = "OPERAND_PCREL";
245 let DecoderMethod = "DecodeBranchTarget";
247 def calltarget : Operand<iPTR> {
248 let EncoderMethod = "getJumpTargetOpValue";
251 def simm16 : Operand<i32> {
252 let DecoderMethod= "DecodeSimm16";
255 def simm20 : Operand<i32> {
258 def uimm20 : Operand<i32> {
261 def uimm10 : Operand<i32> {
264 def simm16_64 : Operand<i64> {
265 let DecoderMethod = "DecodeSimm16";
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm6 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def uimm16 : Operand<i32> {
278 let PrintMethod = "printUnsignedImm";
281 def MipsMemAsmOperand : AsmOperandClass {
283 let ParserMethod = "parseMemOperand";
286 def MipsInvertedImmoperand : AsmOperandClass {
288 let RenderMethod = "addImmOperands";
289 let ParserMethod = "parseInvNum";
292 def PtrRegAsmOperand : AsmOperandClass {
294 let ParserMethod = "parsePtrReg";
298 def InvertedImOperand : Operand<i32> {
299 let ParserMatchClass = MipsInvertedImmoperand;
303 def mem : Operand<iPTR> {
304 let PrintMethod = "printMemOperand";
305 let MIOperandInfo = (ops ptr_rc, simm16);
306 let EncoderMethod = "getMemEncoding";
307 let ParserMatchClass = MipsMemAsmOperand;
308 let OperandType = "OPERAND_MEMORY";
311 def mem_ea : Operand<iPTR> {
312 let PrintMethod = "printMemOperandEA";
313 let MIOperandInfo = (ops ptr_rc, simm16);
314 let EncoderMethod = "getMemEncoding";
315 let OperandType = "OPERAND_MEMORY";
318 def PtrRC : Operand<iPTR> {
319 let MIOperandInfo = (ops ptr_rc);
320 let DecoderMethod = "DecodePtrRegisterClass";
321 let ParserMatchClass = PtrRegAsmOperand;
324 // size operand of ext instruction
325 def size_ext : Operand<i32> {
326 let EncoderMethod = "getSizeExtEncoding";
327 let DecoderMethod = "DecodeExtSize";
330 // size operand of ins instruction
331 def size_ins : Operand<i32> {
332 let EncoderMethod = "getSizeInsEncoding";
333 let DecoderMethod = "DecodeInsSize";
336 // Transformation Function - get the lower 16 bits.
337 def LO16 : SDNodeXForm<imm, [{
338 return getImm(N, N->getZExtValue() & 0xFFFF);
341 // Transformation Function - get the higher 16 bits.
342 def HI16 : SDNodeXForm<imm, [{
343 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
347 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
349 // Node immediate fits as 16-bit sign extended on target immediate.
351 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
353 // Node immediate fits as 16-bit sign extended on target immediate.
355 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
357 // Node immediate fits as 15-bit sign extended on target immediate.
359 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
361 // Node immediate fits as 16-bit zero extended on target immediate.
362 // The LO16 param means that only the lower 16 bits of the node
363 // immediate are caught.
365 def immZExt16 : PatLeaf<(imm), [{
366 if (N->getValueType(0) == MVT::i32)
367 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
369 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
372 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
373 def immLow16Zero : PatLeaf<(imm), [{
374 int64_t Val = N->getSExtValue();
375 return isInt<32>(Val) && !(Val & 0xffff);
378 // shamt field must fit in 5 bits.
379 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
381 // True if (N + 1) fits in 16-bit field.
382 def immSExt16Plus1 : PatLeaf<(imm), [{
383 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
386 // Mips Address Mode! SDNode frameindex could possibily be a match
387 // since load and store instructions from stack used it.
389 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
392 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
395 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
398 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
400 //===----------------------------------------------------------------------===//
401 // Instructions specific format
402 //===----------------------------------------------------------------------===//
404 // Arithmetic and logical instructions with 3 register operands.
405 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
406 InstrItinClass Itin = NoItinerary,
407 SDPatternOperator OpNode = null_frag>:
408 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
409 !strconcat(opstr, "\t$rd, $rs, $rt"),
410 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
411 let isCommutable = isComm;
412 let isReMaterializable = 1;
415 // Arithmetic and logical instructions with 2 register operands.
416 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
417 InstrItinClass Itin = NoItinerary,
418 SDPatternOperator imm_type = null_frag,
419 SDPatternOperator OpNode = null_frag> :
420 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
421 !strconcat(opstr, "\t$rt, $rs, $imm16"),
422 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
424 let isReMaterializable = 1;
425 let TwoOperandAliasConstraint = "$rs = $rt";
428 // Arithmetic Multiply ADD/SUB
429 class MArithR<string opstr, bit isComm = 0> :
430 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
431 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
432 let Defs = [HI0, LO0];
433 let Uses = [HI0, LO0];
434 let isCommutable = isComm;
438 class LogicNOR<string opstr, RegisterOperand RO>:
439 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
440 !strconcat(opstr, "\t$rd, $rs, $rt"),
441 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
442 let isCommutable = 1;
446 class shift_rotate_imm<string opstr, Operand ImmOpnd,
447 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
448 SDPatternOperator PF = null_frag> :
449 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
450 !strconcat(opstr, "\t$rd, $rt, $shamt"),
451 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
453 class shift_rotate_reg<string opstr, RegisterOperand RO,
454 SDPatternOperator OpNode = null_frag>:
455 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
456 !strconcat(opstr, "\t$rd, $rt, $rs"),
457 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
459 // Load Upper Imediate
460 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
461 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
462 [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
463 let neverHasSideEffects = 1;
464 let isReMaterializable = 1;
468 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
469 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
470 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
471 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
472 let DecoderMethod = "DecodeMem";
473 let canFoldAsLoad = 1;
477 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
478 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
479 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
480 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
481 let DecoderMethod = "DecodeMem";
485 // Load/Store Left/Right
486 let canFoldAsLoad = 1 in
487 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
488 InstrItinClass Itin> :
489 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
490 !strconcat(opstr, "\t$rt, $addr"),
491 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
492 let DecoderMethod = "DecodeMem";
493 string Constraints = "$src = $rt";
496 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
497 InstrItinClass Itin> :
498 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
499 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
500 let DecoderMethod = "DecodeMem";
503 // Conditional Branch
504 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
505 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
506 !strconcat(opstr, "\t$rs, $rt, $offset"),
507 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
510 let isTerminator = 1;
511 let hasDelaySlot = 1;
515 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
516 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
517 !strconcat(opstr, "\t$rs, $offset"),
518 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
520 let isTerminator = 1;
521 let hasDelaySlot = 1;
526 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
527 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
528 !strconcat(opstr, "\t$rd, $rs, $rt"),
529 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
532 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
534 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
535 !strconcat(opstr, "\t$rt, $rs, $imm16"),
536 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
540 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
541 SDPatternOperator targetoperator> :
542 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
543 [(operator targetoperator:$target)], IIBranch, FrmJ> {
546 let hasDelaySlot = 1;
547 let DecoderMethod = "DecodeJumpTarget";
551 // Unconditional branch
552 class UncondBranch<Instruction BEQInst> :
553 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
554 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
556 let isTerminator = 1;
558 let hasDelaySlot = 1;
559 let Predicates = [RelocPIC, HasStdEnc];
563 // Base class for indirect branch and return instruction classes.
564 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
565 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
566 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
569 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
571 let isIndirectBranch = 1;
574 // Return instruction
575 class RetBase<RegisterOperand RO>: JumpFR<RO> {
577 let isCodeGenOnly = 1;
579 let hasExtraSrcRegAllocReq = 1;
582 // Jump and Link (Call)
583 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
584 class JumpLink<string opstr> :
585 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
586 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
587 let DecoderMethod = "DecodeJumpTarget";
590 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
591 Register RetReg, RegisterOperand ResRO = RO>:
592 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
593 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
595 class JumpLinkReg<string opstr, RegisterOperand RO>:
596 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
599 class BGEZAL_FT<string opstr, RegisterOperand RO> :
600 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
601 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
605 class BAL_BR_Pseudo<Instruction RealInst> :
606 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
607 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
609 let isTerminator = 1;
611 let hasDelaySlot = 1;
616 class SYS_FT<string opstr> :
617 InstSE<(outs), (ins uimm20:$code_),
618 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
620 class BRK_FT<string opstr> :
621 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
622 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
625 class ER_FT<string opstr> :
626 InstSE<(outs), (ins),
627 opstr, [], NoItinerary, FrmOther>;
630 class DEI_FT<string opstr, RegisterOperand RO> :
631 InstSE<(outs RO:$rt), (ins),
632 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
635 class WAIT_FT<string opstr> :
636 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
637 let Inst{31-26} = 0x10;
640 let Inst{5-0} = 0x20;
644 let hasSideEffects = 1 in
646 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
647 NoItinerary, FrmOther>;
649 let hasSideEffects = 1 in
650 class TEQ_FT<string opstr, RegisterOperand RO> :
651 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
652 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
654 class TEQI_FT<string opstr, RegisterOperand RO> :
655 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
656 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
658 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
659 list<Register> DefRegs> :
660 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
662 let isCommutable = 1;
664 let neverHasSideEffects = 1;
667 // Pseudo multiply/divide instruction with explicit accumulator register
669 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
670 SDPatternOperator OpNode, InstrItinClass Itin,
671 bit IsComm = 1, bit HasSideEffects = 0,
672 bit UsesCustomInserter = 0> :
673 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
674 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
675 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
676 let isCommutable = IsComm;
677 let hasSideEffects = HasSideEffects;
678 let usesCustomInserter = UsesCustomInserter;
681 // Pseudo multiply add/sub instruction with explicit accumulator register
683 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
684 : PseudoSE<(outs ACC64:$ac),
685 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
687 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
689 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
690 string Constraints = "$acin = $ac";
693 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
694 list<Register> DefRegs> :
695 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
696 [], itin, FrmR, opstr> {
701 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
702 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
703 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>;
705 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
706 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR,
709 let neverHasSideEffects = 1;
712 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
713 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
714 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], IIHiLo>;
716 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
717 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
720 let neverHasSideEffects = 1;
723 class EffectiveAddress<string opstr, RegisterOperand RO> :
724 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
725 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
726 let isCodeGenOnly = 1;
727 let DecoderMethod = "DecodeMem";
730 // Count Leading Ones/Zeros in Word
731 class CountLeading0<string opstr, RegisterOperand RO>:
732 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
733 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
734 Requires<[HasBitCount, HasStdEnc]>;
736 class CountLeading1<string opstr, RegisterOperand RO>:
737 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
738 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
739 Requires<[HasBitCount, HasStdEnc]>;
742 // Sign Extend in Register.
743 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
744 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
745 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> {
746 let Predicates = [HasSEInReg, HasStdEnc];
750 class SubwordSwap<string opstr, RegisterOperand RO>:
751 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
752 NoItinerary, FrmR, opstr> {
753 let Predicates = [HasSwap, HasStdEnc];
754 let neverHasSideEffects = 1;
758 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
759 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
763 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
764 SDPatternOperator Op = null_frag>:
765 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
766 !strconcat(opstr, " $rt, $rs, $pos, $size"),
767 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
769 let Predicates = [HasMips32r2, HasStdEnc];
772 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
773 SDPatternOperator Op = null_frag>:
774 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
775 !strconcat(opstr, " $rt, $rs, $pos, $size"),
776 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
777 NoItinerary, FrmR, opstr> {
778 let Predicates = [HasMips32r2, HasStdEnc];
779 let Constraints = "$src = $rt";
782 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
783 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
784 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
785 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
787 // Atomic Compare & Swap.
788 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
789 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
790 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
792 class LLBase<string opstr, RegisterOperand RO> :
793 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
794 [], NoItinerary, FrmI> {
795 let DecoderMethod = "DecodeMem";
799 class SCBase<string opstr, RegisterOperand RO> :
800 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
801 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
802 let DecoderMethod = "DecodeMem";
804 let Constraints = "$rt = $dst";
807 class MFC3OP<string asmstr, RegisterOperand RO> :
808 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
809 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
811 class TrapBase<Instruction RealInst>
812 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
813 PseudoInstExpansion<(RealInst 0, 0)> {
815 let isTerminator = 1;
816 let isCodeGenOnly = 1;
819 //===----------------------------------------------------------------------===//
820 // Pseudo instructions
821 //===----------------------------------------------------------------------===//
824 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
825 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
827 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
828 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
829 [(callseq_start timm:$amt)]>;
830 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
831 [(callseq_end timm:$amt1, timm:$amt2)]>;
834 let usesCustomInserter = 1 in {
835 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
836 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
837 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
838 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
839 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
840 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
841 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
842 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
843 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
844 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
845 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
846 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
847 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
848 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
849 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
850 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
851 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
852 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
854 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
855 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
856 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
858 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
859 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
860 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
863 /// Pseudo instructions for loading and storing accumulator registers.
864 let isPseudo = 1, isCodeGenOnly = 1 in {
865 def LOAD_ACC64 : Load<"", ACC64>;
866 def STORE_ACC64 : Store<"", ACC64>;
869 //===----------------------------------------------------------------------===//
870 // Instruction definition
871 //===----------------------------------------------------------------------===//
872 //===----------------------------------------------------------------------===//
873 // MipsI Instructions
874 //===----------------------------------------------------------------------===//
876 /// Arithmetic Instructions (ALU Immediate)
877 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
879 ADDI_FM<0x9>, IsAsCheapAsAMove;
880 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
881 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
883 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
885 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
888 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
891 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
894 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
896 /// Arithmetic Instructions (3-Operand, R-Type)
897 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
899 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
901 let Defs = [HI0, LO0] in
902 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
904 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
905 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
906 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
907 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
908 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
910 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
912 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
914 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
916 /// Shift Instructions
917 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
919 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
921 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
923 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
924 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
925 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
927 // Rotate Instructions
928 let Predicates = [HasMips32r2, HasStdEnc] in {
929 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
932 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
936 /// Load and Store Instructions
938 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
939 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
941 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
943 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
944 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
946 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
947 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
948 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
950 /// load/store left/right
951 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
952 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
953 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
954 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
956 def SYNC : SYNC_FT, SYNC_FM;
957 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
958 def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
959 def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
960 def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
961 def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
962 def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
964 def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
965 def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
966 def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
967 def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
968 def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
969 def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
971 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
972 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
973 def TRAP : TrapBase<BREAK>;
975 def ERET : ER_FT<"eret">, ER_FM<0x18>;
976 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
978 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
979 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
981 def WAIT : WAIT_FT<"wait">;
983 /// Load-linked, Store-conditional
984 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
985 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
987 /// Jump and Branch Instructions
988 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
989 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
990 def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>;
991 def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
992 def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
993 def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
994 def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
995 def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
996 def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
997 def B : UncondBranch<BEQ>;
999 def JAL : JumpLink<"jal">, FJ<3>;
1000 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1001 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1002 def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
1003 def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
1004 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1005 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
1006 def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
1008 def RET : RetBase<GPR32Opnd>, MTLO_FM<8>;
1010 // Exception handling related node and instructions.
1011 // The conversion sequence is:
1012 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1013 // MIPSeh_return -> (stack change + indirect branch)
1015 // MIPSeh_return takes the place of regular return instruction
1016 // but takes two arguments (V1, V0) which are used for storing
1017 // the offset and return address respectively.
1018 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1020 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1021 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1023 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1024 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1025 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1026 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1028 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1031 /// Multiply and Divide Instructions.
1032 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1034 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1036 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
1037 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
1039 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1040 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1041 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1042 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1044 /// Sign Ext In Register Instructions.
1045 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1046 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1049 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1050 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1052 /// Word Swap Bytes Within Halfwords
1053 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1056 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1058 // FrameIndexes are legalized when they are operands from load/store
1059 // instructions. The same not happens for stack address copies, so an
1060 // add op with mem ComplexPattern is used and the stack address copy
1061 // can be matched. It's similar to Sparc LEA_ADDRi
1062 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1065 def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1066 def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1067 def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1068 def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1070 let Predicates = [HasStdEnc, NotDSP] in {
1071 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1072 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1073 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1074 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1075 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1076 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1077 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1078 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1079 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1082 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1084 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1087 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1089 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1090 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1092 /// Move Control Registers From/To CPU Registers
1093 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1094 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1095 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1096 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1098 //===----------------------------------------------------------------------===//
1099 // Instruction aliases
1100 //===----------------------------------------------------------------------===//
1101 def : InstAlias<"move $dst, $src",
1102 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1103 Requires<[NotMips64]>;
1104 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1105 def : InstAlias<"addu $rs, $rt, $imm",
1106 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1107 def : InstAlias<"add $rs, $rt, $imm",
1108 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1109 def : InstAlias<"and $rs, $rt, $imm",
1110 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1111 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1112 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1113 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1114 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1115 def : InstAlias<"not $rt, $rs",
1116 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1117 def : InstAlias<"neg $rt, $rs",
1118 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1119 def : InstAlias<"negu $rt, $rs",
1120 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1121 def : InstAlias<"slt $rs, $rt, $imm",
1122 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1123 def : InstAlias<"xor $rs, $rt, $imm",
1124 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1125 def : InstAlias<"or $rs, $rt, $imm",
1126 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1127 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1128 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1129 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1130 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1131 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1132 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1133 def : InstAlias<"bnez $rs,$offset",
1134 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1135 def : InstAlias<"beqz $rs,$offset",
1136 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1137 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1139 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1140 def : InstAlias<"break", (BREAK 0, 0), 1>;
1141 def : InstAlias<"ei", (EI ZERO), 1>;
1142 def : InstAlias<"di", (DI ZERO), 1>;
1144 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1145 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1146 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1147 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1148 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1149 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1150 def : InstAlias<"sub, $rd, $rs, $imm",
1151 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1152 def : InstAlias<"subu, $rd, $rs, $imm",
1153 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1155 //===----------------------------------------------------------------------===//
1156 // Assembler Pseudo Instructions
1157 //===----------------------------------------------------------------------===//
1159 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1160 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1161 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1162 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1164 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1165 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1166 !strconcat(instr_asm, "\t$rt, $addr")> ;
1167 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1169 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1170 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1171 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1172 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1174 //===----------------------------------------------------------------------===//
1175 // Arbitrary patterns that map to one or more instructions
1176 //===----------------------------------------------------------------------===//
1178 // Load/store pattern templates.
1179 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1180 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1182 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1183 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1186 def : MipsPat<(i32 immSExt16:$in),
1187 (ADDiu ZERO, imm:$in)>;
1188 def : MipsPat<(i32 immZExt16:$in),
1189 (ORi ZERO, imm:$in)>;
1190 def : MipsPat<(i32 immLow16Zero:$in),
1191 (LUi (HI16 imm:$in))>;
1193 // Arbitrary immediates
1194 def : MipsPat<(i32 imm:$imm),
1195 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1197 // Carry MipsPatterns
1198 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1199 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1200 let Predicates = [HasStdEnc, NotDSP] in {
1201 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1202 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1203 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1204 (ADDiu GPR32:$src, imm:$imm)>;
1208 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1209 (JAL tglobaladdr:$dst)>;
1210 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1211 (JAL texternalsym:$dst)>;
1212 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1213 // (JALR GPR32:$dst)>;
1216 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1217 (TAILCALL tglobaladdr:$dst)>;
1218 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1219 (TAILCALL texternalsym:$dst)>;
1221 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1222 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1223 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1224 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1225 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1226 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1228 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1229 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1230 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1231 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1232 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1233 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1235 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1236 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1237 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1238 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1239 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1240 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1241 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1242 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1243 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1244 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1247 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1248 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1249 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1250 (ADDiu GPR32:$gp, tconstpool:$in)>;
1253 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1254 MipsPat<(MipsWrapper RC:$gp, node:$in),
1255 (ADDiuOp RC:$gp, node:$in)>;
1257 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1258 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1259 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1260 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1261 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1262 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1264 // Mips does not have "not", so we expand our way
1265 def : MipsPat<(not GPR32:$in),
1266 (NOR GPR32Opnd:$in, ZERO)>;
1269 let Predicates = [HasStdEnc] in {
1270 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1271 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1272 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1276 let Predicates = [HasStdEnc] in
1277 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1280 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1281 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1282 Instruction SLTiuOp, Register ZEROReg> {
1283 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1284 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1285 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1286 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1288 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1289 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1290 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1291 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1292 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1293 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1294 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1295 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1296 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1297 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1298 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1299 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1301 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1302 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1303 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1304 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1306 def : MipsPat<(brcond RC:$cond, bb:$dst),
1307 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1310 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1312 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1313 (BLEZ i32:$lhs, bb:$dst)>;
1314 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1315 (BGEZ i32:$lhs, bb:$dst)>;
1318 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1319 Instruction SLTuOp, Register ZEROReg> {
1320 def : MipsPat<(seteq RC:$lhs, 0),
1321 (SLTiuOp RC:$lhs, 1)>;
1322 def : MipsPat<(setne RC:$lhs, 0),
1323 (SLTuOp ZEROReg, RC:$lhs)>;
1324 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1325 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1326 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1327 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1330 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1331 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1332 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1333 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1334 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1337 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1338 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1339 (SLTOp RC:$rhs, RC:$lhs)>;
1340 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1341 (SLTuOp RC:$rhs, RC:$lhs)>;
1344 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1345 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1346 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1347 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1348 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1351 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1352 Instruction SLTiuOp> {
1353 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1354 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1355 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1356 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1359 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1360 defm : SetlePats<GPR32, SLT, SLTu>;
1361 defm : SetgtPats<GPR32, SLT, SLTu>;
1362 defm : SetgePats<GPR32, SLT, SLTu>;
1363 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1366 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1368 // Load halfword/word patterns.
1369 let AddedComplexity = 40 in {
1370 let Predicates = [HasStdEnc] in {
1371 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1372 def : LoadRegImmPat<LH, i32, sextloadi16>;
1373 def : LoadRegImmPat<LW, i32, load>;
1377 //===----------------------------------------------------------------------===//
1378 // Floating Point Support
1379 //===----------------------------------------------------------------------===//
1381 include "MipsInstrFPU.td"
1382 include "Mips64InstrInfo.td"
1383 include "MipsCondMov.td"
1388 include "Mips16InstrFormats.td"
1389 include "Mips16InstrInfo.td"
1392 include "MipsDSPInstrFormats.td"
1393 include "MipsDSPInstrInfo.td"
1396 include "MipsMSAInstrFormats.td"
1397 include "MipsMSAInstrInfo.td"
1400 include "MicroMipsInstrFormats.td"
1401 include "MicroMipsInstrInfo.td"