1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
172 AssemblerPredicate<"!FeatureN64">;
173 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
174 AssemblerPredicate<"FeatureMips16">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
191 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
192 let Predicates = [HasStdEnc];
196 bit isCommutable = 1;
213 bit isTerminator = 1;
216 bit hasExtraSrcRegAllocReq = 1;
217 bit isCodeGenOnly = 1;
220 class IsAsCheapAsAMove {
221 bit isAsCheapAsAMove = 1;
224 class NeverHasSideEffects {
225 bit neverHasSideEffects = 1;
228 //===----------------------------------------------------------------------===//
229 // Instruction format superclass
230 //===----------------------------------------------------------------------===//
232 include "MipsInstrFormats.td"
234 //===----------------------------------------------------------------------===//
235 // Mips Operand, Complex Patterns and Transformations Definitions.
236 //===----------------------------------------------------------------------===//
238 // Instruction operand types
239 def jmptarget : Operand<OtherVT> {
240 let EncoderMethod = "getJumpTargetOpValue";
242 def brtarget : Operand<OtherVT> {
243 let EncoderMethod = "getBranchTargetOpValue";
244 let OperandType = "OPERAND_PCREL";
245 let DecoderMethod = "DecodeBranchTarget";
247 def calltarget : Operand<iPTR> {
248 let EncoderMethod = "getJumpTargetOpValue";
251 def simm16 : Operand<i32> {
252 let DecoderMethod= "DecodeSimm16";
255 def simm20 : Operand<i32> {
258 def uimm20 : Operand<i32> {
261 def uimm10 : Operand<i32> {
264 def simm16_64 : Operand<i64> {
265 let DecoderMethod = "DecodeSimm16";
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm6 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def uimm16 : Operand<i32> {
278 let PrintMethod = "printUnsignedImm";
281 def pcrel16 : Operand<i32> {
284 def MipsMemAsmOperand : AsmOperandClass {
286 let ParserMethod = "parseMemOperand";
289 def MipsInvertedImmoperand : AsmOperandClass {
291 let RenderMethod = "addImmOperands";
292 let ParserMethod = "parseInvNum";
295 def PtrRegAsmOperand : AsmOperandClass {
297 let ParserMethod = "parsePtrReg";
301 def InvertedImOperand : Operand<i32> {
302 let ParserMatchClass = MipsInvertedImmoperand;
306 def mem : Operand<iPTR> {
307 let PrintMethod = "printMemOperand";
308 let MIOperandInfo = (ops ptr_rc, simm16);
309 let EncoderMethod = "getMemEncoding";
310 let ParserMatchClass = MipsMemAsmOperand;
311 let OperandType = "OPERAND_MEMORY";
314 def mem_ea : Operand<iPTR> {
315 let PrintMethod = "printMemOperandEA";
316 let MIOperandInfo = (ops ptr_rc, simm16);
317 let EncoderMethod = "getMemEncoding";
318 let OperandType = "OPERAND_MEMORY";
321 def PtrRC : Operand<iPTR> {
322 let MIOperandInfo = (ops ptr_rc);
323 let DecoderMethod = "DecodePtrRegisterClass";
324 let ParserMatchClass = PtrRegAsmOperand;
327 // size operand of ext instruction
328 def size_ext : Operand<i32> {
329 let EncoderMethod = "getSizeExtEncoding";
330 let DecoderMethod = "DecodeExtSize";
333 // size operand of ins instruction
334 def size_ins : Operand<i32> {
335 let EncoderMethod = "getSizeInsEncoding";
336 let DecoderMethod = "DecodeInsSize";
339 // Transformation Function - get the lower 16 bits.
340 def LO16 : SDNodeXForm<imm, [{
341 return getImm(N, N->getZExtValue() & 0xFFFF);
344 // Transformation Function - get the higher 16 bits.
345 def HI16 : SDNodeXForm<imm, [{
346 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
350 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
352 // Node immediate fits as 16-bit sign extended on target immediate.
354 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
356 // Node immediate fits as 16-bit sign extended on target immediate.
358 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
360 // Node immediate fits as 15-bit sign extended on target immediate.
362 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
364 // Node immediate fits as 16-bit zero extended on target immediate.
365 // The LO16 param means that only the lower 16 bits of the node
366 // immediate are caught.
368 def immZExt16 : PatLeaf<(imm), [{
369 if (N->getValueType(0) == MVT::i32)
370 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
372 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
375 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
376 def immLow16Zero : PatLeaf<(imm), [{
377 int64_t Val = N->getSExtValue();
378 return isInt<32>(Val) && !(Val & 0xffff);
381 // shamt field must fit in 5 bits.
382 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
384 // True if (N + 1) fits in 16-bit field.
385 def immSExt16Plus1 : PatLeaf<(imm), [{
386 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
389 // Mips Address Mode! SDNode frameindex could possibily be a match
390 // since load and store instructions from stack used it.
392 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
395 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
398 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
401 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
403 //===----------------------------------------------------------------------===//
404 // Instructions specific format
405 //===----------------------------------------------------------------------===//
407 // Arithmetic and logical instructions with 3 register operands.
408 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
409 InstrItinClass Itin = NoItinerary,
410 SDPatternOperator OpNode = null_frag>:
411 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
412 !strconcat(opstr, "\t$rd, $rs, $rt"),
413 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
414 let isCommutable = isComm;
415 let isReMaterializable = 1;
418 // Arithmetic and logical instructions with 2 register operands.
419 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
420 InstrItinClass Itin = NoItinerary,
421 SDPatternOperator imm_type = null_frag,
422 SDPatternOperator OpNode = null_frag> :
423 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
424 !strconcat(opstr, "\t$rt, $rs, $imm16"),
425 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
427 let isReMaterializable = 1;
428 let TwoOperandAliasConstraint = "$rs = $rt";
431 // Arithmetic Multiply ADD/SUB
432 class MArithR<string opstr, bit isComm = 0> :
433 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
434 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
435 let Defs = [HI0, LO0];
436 let Uses = [HI0, LO0];
437 let isCommutable = isComm;
441 class LogicNOR<string opstr, RegisterOperand RO>:
442 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
443 !strconcat(opstr, "\t$rd, $rs, $rt"),
444 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
445 let isCommutable = 1;
449 class shift_rotate_imm<string opstr, Operand ImmOpnd,
450 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
451 SDPatternOperator PF = null_frag> :
452 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
453 !strconcat(opstr, "\t$rd, $rt, $shamt"),
454 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
456 class shift_rotate_reg<string opstr, RegisterOperand RO,
457 SDPatternOperator OpNode = null_frag>:
458 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
459 !strconcat(opstr, "\t$rd, $rt, $rs"),
460 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
462 // Load Upper Imediate
463 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
464 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
465 [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
466 let neverHasSideEffects = 1;
467 let isReMaterializable = 1;
471 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
472 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
473 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
474 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
475 let DecoderMethod = "DecodeMem";
476 let canFoldAsLoad = 1;
480 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
481 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
482 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
483 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
484 let DecoderMethod = "DecodeMem";
488 // Load/Store Left/Right
489 let canFoldAsLoad = 1 in
490 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
491 InstrItinClass Itin> :
492 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
493 !strconcat(opstr, "\t$rt, $addr"),
494 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
495 let DecoderMethod = "DecodeMem";
496 string Constraints = "$src = $rt";
499 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
500 InstrItinClass Itin> :
501 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
502 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
503 let DecoderMethod = "DecodeMem";
506 // Conditional Branch
507 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
508 RegisterOperand RO> :
509 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
510 !strconcat(opstr, "\t$rs, $rt, $offset"),
511 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
514 let isTerminator = 1;
515 let hasDelaySlot = 1;
519 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
520 RegisterOperand RO> :
521 InstSE<(outs), (ins RO:$rs, opnd:$offset),
522 !strconcat(opstr, "\t$rs, $offset"),
523 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
526 let isTerminator = 1;
527 let hasDelaySlot = 1;
532 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
533 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
534 !strconcat(opstr, "\t$rd, $rs, $rt"),
535 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
538 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
540 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
541 !strconcat(opstr, "\t$rt, $rs, $imm16"),
542 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
546 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
547 SDPatternOperator targetoperator, string bopstr> :
548 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
549 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
552 let hasDelaySlot = 1;
553 let DecoderMethod = "DecodeJumpTarget";
557 // Unconditional branch
558 class UncondBranch<Instruction BEQInst> :
559 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
560 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
562 let isTerminator = 1;
564 let hasDelaySlot = 1;
565 let Predicates = [RelocPIC, HasStdEnc];
569 // Base class for indirect branch and return instruction classes.
570 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
571 class JumpFR<string opstr, RegisterOperand RO,
572 SDPatternOperator operator = null_frag>:
573 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
577 class IndirectBranch<string opstr, RegisterOperand RO> :
578 JumpFR<opstr, RO, brind> {
580 let isIndirectBranch = 1;
583 // Return instruction
584 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
586 let isCodeGenOnly = 1;
588 let hasExtraSrcRegAllocReq = 1;
591 // Jump and Link (Call)
592 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
593 class JumpLink<string opstr, DAGOperand opnd> :
594 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
595 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
596 let DecoderMethod = "DecodeJumpTarget";
599 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
600 Register RetReg, RegisterOperand ResRO = RO>:
601 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
602 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
604 class JumpLinkReg<string opstr, RegisterOperand RO>:
605 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
606 [], IIBranch, FrmR, opstr>;
608 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
609 InstSE<(outs), (ins RO:$rs, opnd:$offset),
610 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
614 class BAL_BR_Pseudo<Instruction RealInst> :
615 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
616 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
618 let isTerminator = 1;
620 let hasDelaySlot = 1;
625 class SYS_FT<string opstr> :
626 InstSE<(outs), (ins uimm20:$code_),
627 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
629 class BRK_FT<string opstr> :
630 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
631 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
634 class ER_FT<string opstr> :
635 InstSE<(outs), (ins),
636 opstr, [], NoItinerary, FrmOther>;
639 class DEI_FT<string opstr, RegisterOperand RO> :
640 InstSE<(outs RO:$rt), (ins),
641 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
644 class WAIT_FT<string opstr> :
645 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
646 let Inst{31-26} = 0x10;
649 let Inst{5-0} = 0x20;
653 let hasSideEffects = 1 in
655 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
656 NoItinerary, FrmOther>;
658 let hasSideEffects = 1 in
659 class TEQ_FT<string opstr, RegisterOperand RO> :
660 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
661 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
664 class TEQI_FT<string opstr, RegisterOperand RO> :
665 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
666 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
668 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
669 list<Register> DefRegs> :
670 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
672 let isCommutable = 1;
674 let neverHasSideEffects = 1;
677 // Pseudo multiply/divide instruction with explicit accumulator register
679 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
680 SDPatternOperator OpNode, InstrItinClass Itin,
681 bit IsComm = 1, bit HasSideEffects = 0,
682 bit UsesCustomInserter = 0> :
683 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
684 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
685 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
686 let isCommutable = IsComm;
687 let hasSideEffects = HasSideEffects;
688 let usesCustomInserter = UsesCustomInserter;
691 // Pseudo multiply add/sub instruction with explicit accumulator register
693 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
694 : PseudoSE<(outs ACC64:$ac),
695 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
697 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
699 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
700 string Constraints = "$acin = $ac";
703 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
704 list<Register> DefRegs> :
705 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
706 [], itin, FrmR, opstr> {
711 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
712 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
713 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>;
715 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
716 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR,
719 let neverHasSideEffects = 1;
722 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
723 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
724 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], IIHiLo>;
726 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
727 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
730 let neverHasSideEffects = 1;
733 class EffectiveAddress<string opstr, RegisterOperand RO> :
734 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
735 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
736 let isCodeGenOnly = 1;
737 let DecoderMethod = "DecodeMem";
740 // Count Leading Ones/Zeros in Word
741 class CountLeading0<string opstr, RegisterOperand RO>:
742 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
743 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
744 Requires<[HasBitCount, HasStdEnc]>;
746 class CountLeading1<string opstr, RegisterOperand RO>:
747 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
748 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
749 Requires<[HasBitCount, HasStdEnc]>;
752 // Sign Extend in Register.
753 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
754 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
755 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> {
756 let Predicates = [HasSEInReg, HasStdEnc];
760 class SubwordSwap<string opstr, RegisterOperand RO>:
761 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
762 NoItinerary, FrmR, opstr> {
763 let Predicates = [HasSwap, HasStdEnc];
764 let neverHasSideEffects = 1;
768 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
769 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
773 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
774 SDPatternOperator Op = null_frag>:
775 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
776 !strconcat(opstr, " $rt, $rs, $pos, $size"),
777 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
779 let Predicates = [HasMips32r2, HasStdEnc];
782 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
783 SDPatternOperator Op = null_frag>:
784 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
785 !strconcat(opstr, " $rt, $rs, $pos, $size"),
786 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
787 NoItinerary, FrmR, opstr> {
788 let Predicates = [HasMips32r2, HasStdEnc];
789 let Constraints = "$src = $rt";
792 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
793 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
794 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
795 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
797 // Atomic Compare & Swap.
798 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
799 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
800 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
802 class LLBase<string opstr, RegisterOperand RO> :
803 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
804 [], NoItinerary, FrmI> {
805 let DecoderMethod = "DecodeMem";
809 class SCBase<string opstr, RegisterOperand RO> :
810 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
811 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
812 let DecoderMethod = "DecodeMem";
814 let Constraints = "$rt = $dst";
817 class MFC3OP<string asmstr, RegisterOperand RO> :
818 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
819 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
821 class TrapBase<Instruction RealInst>
822 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
823 PseudoInstExpansion<(RealInst 0, 0)> {
825 let isTerminator = 1;
826 let isCodeGenOnly = 1;
829 //===----------------------------------------------------------------------===//
830 // Pseudo instructions
831 //===----------------------------------------------------------------------===//
834 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
835 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
837 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
838 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
839 [(callseq_start timm:$amt)]>;
840 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
841 [(callseq_end timm:$amt1, timm:$amt2)]>;
844 let usesCustomInserter = 1 in {
845 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
846 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
847 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
848 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
849 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
850 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
851 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
852 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
853 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
854 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
855 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
856 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
857 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
858 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
859 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
860 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
861 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
862 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
864 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
865 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
866 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
868 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
869 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
870 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
873 /// Pseudo instructions for loading and storing accumulator registers.
874 let isPseudo = 1, isCodeGenOnly = 1 in {
875 def LOAD_ACC64 : Load<"", ACC64>;
876 def STORE_ACC64 : Store<"", ACC64>;
879 //===----------------------------------------------------------------------===//
880 // Instruction definition
881 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
883 // MipsI Instructions
884 //===----------------------------------------------------------------------===//
886 /// Arithmetic Instructions (ALU Immediate)
887 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
889 ADDI_FM<0x9>, IsAsCheapAsAMove;
890 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
891 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
893 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
895 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
898 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
901 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
904 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
906 /// Arithmetic Instructions (3-Operand, R-Type)
907 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
909 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
911 let Defs = [HI0, LO0] in
912 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
914 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
915 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
916 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
917 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
918 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
920 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
922 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
924 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
926 /// Shift Instructions
927 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
929 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
931 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
933 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
934 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
935 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
937 // Rotate Instructions
938 let Predicates = [HasMips32r2, HasStdEnc] in {
939 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
942 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
946 /// Load and Store Instructions
948 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
949 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
951 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
953 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
954 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
956 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
957 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
958 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
960 /// load/store left/right
961 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
962 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
963 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
964 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
966 def SYNC : SYNC_FT, SYNC_FM;
967 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
968 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
969 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
970 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
971 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
972 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
974 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
975 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
976 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
977 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
978 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
979 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
981 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
982 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
983 def TRAP : TrapBase<BREAK>;
985 def ERET : ER_FT<"eret">, ER_FM<0x18>;
986 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
988 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
989 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
991 def WAIT : WAIT_FT<"wait">;
993 /// Load-linked, Store-conditional
994 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
995 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
997 /// Jump and Branch Instructions
998 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
999 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1000 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1001 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1002 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1003 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1005 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1007 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1009 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1011 def B : UncondBranch<BEQ>;
1013 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1014 def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1015 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1016 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1017 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1018 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1019 def TAILCALL : MMRel, JumpFJ<calltarget, "j", MipsTailCall, imm, "tcall">,
1021 def TAILCALL_R : MMRel, JumpFR<"tcallr", GPR32Opnd, MipsTailCall>, MTLO_FM<8>,
1024 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1026 // Exception handling related node and instructions.
1027 // The conversion sequence is:
1028 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1029 // MIPSeh_return -> (stack change + indirect branch)
1031 // MIPSeh_return takes the place of regular return instruction
1032 // but takes two arguments (V1, V0) which are used for storing
1033 // the offset and return address respectively.
1034 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1036 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1037 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1039 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1040 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1041 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1042 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1044 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1047 /// Multiply and Divide Instructions.
1048 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1050 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1052 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
1053 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
1055 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1056 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1057 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1058 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1060 /// Sign Ext In Register Instructions.
1061 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1062 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1065 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1066 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1068 /// Word Swap Bytes Within Halfwords
1069 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1072 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1074 // FrameIndexes are legalized when they are operands from load/store
1075 // instructions. The same not happens for stack address copies, so an
1076 // add op with mem ComplexPattern is used and the stack address copy
1077 // can be matched. It's similar to Sparc LEA_ADDRi
1078 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1081 def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1082 def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1083 def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1084 def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1086 let Predicates = [HasStdEnc, NotDSP] in {
1087 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1088 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1089 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1090 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1091 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1092 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1093 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1094 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1095 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1098 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1100 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1103 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1105 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1106 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1108 /// Move Control Registers From/To CPU Registers
1109 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1110 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1111 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1112 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1114 //===----------------------------------------------------------------------===//
1115 // Instruction aliases
1116 //===----------------------------------------------------------------------===//
1117 def : InstAlias<"move $dst, $src",
1118 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1119 Requires<[NotMips64]>;
1120 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1121 def : InstAlias<"addu $rs, $rt, $imm",
1122 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1123 def : InstAlias<"add $rs, $rt, $imm",
1124 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1125 def : InstAlias<"and $rs, $rt, $imm",
1126 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1127 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1128 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1129 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1130 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1131 def : InstAlias<"not $rt, $rs",
1132 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1133 def : InstAlias<"neg $rt, $rs",
1134 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1135 def : InstAlias<"negu $rt, $rs",
1136 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1137 def : InstAlias<"slt $rs, $rt, $imm",
1138 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1139 def : InstAlias<"xor $rs, $rt, $imm",
1140 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1141 def : InstAlias<"or $rs, $rt, $imm",
1142 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1143 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1144 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1145 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1146 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1147 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1148 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1149 def : InstAlias<"bnez $rs,$offset",
1150 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1151 def : InstAlias<"beqz $rs,$offset",
1152 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1153 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1155 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1156 def : InstAlias<"break", (BREAK 0, 0), 1>;
1157 def : InstAlias<"ei", (EI ZERO), 1>;
1158 def : InstAlias<"di", (DI ZERO), 1>;
1160 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1161 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1162 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1163 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1164 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1165 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1166 def : InstAlias<"sub, $rd, $rs, $imm",
1167 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1168 def : InstAlias<"subu, $rd, $rs, $imm",
1169 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1171 //===----------------------------------------------------------------------===//
1172 // Assembler Pseudo Instructions
1173 //===----------------------------------------------------------------------===//
1175 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1176 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1177 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1178 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1180 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1181 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1182 !strconcat(instr_asm, "\t$rt, $addr")> ;
1183 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1185 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1186 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1187 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1188 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1190 //===----------------------------------------------------------------------===//
1191 // Arbitrary patterns that map to one or more instructions
1192 //===----------------------------------------------------------------------===//
1194 // Load/store pattern templates.
1195 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1196 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1198 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1199 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1202 def : MipsPat<(i32 immSExt16:$in),
1203 (ADDiu ZERO, imm:$in)>;
1204 def : MipsPat<(i32 immZExt16:$in),
1205 (ORi ZERO, imm:$in)>;
1206 def : MipsPat<(i32 immLow16Zero:$in),
1207 (LUi (HI16 imm:$in))>;
1209 // Arbitrary immediates
1210 def : MipsPat<(i32 imm:$imm),
1211 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1213 // Carry MipsPatterns
1214 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1215 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1216 let Predicates = [HasStdEnc, NotDSP] in {
1217 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1218 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1219 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1220 (ADDiu GPR32:$src, imm:$imm)>;
1224 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1225 (JAL tglobaladdr:$dst)>;
1226 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1227 (JAL texternalsym:$dst)>;
1228 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1229 // (JALR GPR32:$dst)>;
1232 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1233 (TAILCALL tglobaladdr:$dst)>;
1234 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1235 (TAILCALL texternalsym:$dst)>;
1237 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1238 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1239 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1240 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1241 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1242 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1244 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1245 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1246 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1247 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1248 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1249 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1251 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1252 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1253 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1254 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1255 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1256 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1257 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1258 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1259 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1260 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1263 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1264 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1265 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1266 (ADDiu GPR32:$gp, tconstpool:$in)>;
1269 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1270 MipsPat<(MipsWrapper RC:$gp, node:$in),
1271 (ADDiuOp RC:$gp, node:$in)>;
1273 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1274 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1275 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1276 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1277 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1278 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1280 // Mips does not have "not", so we expand our way
1281 def : MipsPat<(not GPR32:$in),
1282 (NOR GPR32Opnd:$in, ZERO)>;
1285 let Predicates = [HasStdEnc] in {
1286 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1287 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1288 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1292 let Predicates = [HasStdEnc] in
1293 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1296 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1297 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1298 Instruction SLTiuOp, Register ZEROReg> {
1299 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1300 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1301 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1302 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1304 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1305 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1306 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1307 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1308 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1309 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1310 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1311 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1312 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1313 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1314 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1315 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1317 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1318 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1319 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1320 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1322 def : MipsPat<(brcond RC:$cond, bb:$dst),
1323 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1326 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1328 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1329 (BLEZ i32:$lhs, bb:$dst)>;
1330 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1331 (BGEZ i32:$lhs, bb:$dst)>;
1334 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1335 Instruction SLTuOp, Register ZEROReg> {
1336 def : MipsPat<(seteq RC:$lhs, 0),
1337 (SLTiuOp RC:$lhs, 1)>;
1338 def : MipsPat<(setne RC:$lhs, 0),
1339 (SLTuOp ZEROReg, RC:$lhs)>;
1340 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1341 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1342 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1343 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1346 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1347 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1348 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1349 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1350 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1353 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1354 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1355 (SLTOp RC:$rhs, RC:$lhs)>;
1356 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1357 (SLTuOp RC:$rhs, RC:$lhs)>;
1360 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1361 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1362 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1363 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1364 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1367 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1368 Instruction SLTiuOp> {
1369 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1370 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1371 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1372 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1375 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1376 defm : SetlePats<GPR32, SLT, SLTu>;
1377 defm : SetgtPats<GPR32, SLT, SLTu>;
1378 defm : SetgePats<GPR32, SLT, SLTu>;
1379 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1382 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1384 // Load halfword/word patterns.
1385 let AddedComplexity = 40 in {
1386 let Predicates = [HasStdEnc] in {
1387 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1388 def : LoadRegImmPat<LH, i32, sextloadi16>;
1389 def : LoadRegImmPat<LW, i32, load>;
1393 //===----------------------------------------------------------------------===//
1394 // Floating Point Support
1395 //===----------------------------------------------------------------------===//
1397 include "MipsInstrFPU.td"
1398 include "Mips64InstrInfo.td"
1399 include "MipsCondMov.td"
1404 include "Mips16InstrFormats.td"
1405 include "Mips16InstrInfo.td"
1408 include "MipsDSPInstrFormats.td"
1409 include "MipsDSPInstrInfo.td"
1412 include "MipsMSAInstrFormats.td"
1413 include "MipsMSAInstrInfo.td"
1416 include "MicroMipsInstrFormats.td"
1417 include "MicroMipsInstrInfo.td"