1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSINSTRUCTIONINFO_H
15 #define MIPSINSTRUCTIONINFO_H
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "MipsRegisterInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "MipsGenInstrInfo.inc"
38 // Mips Condition Codes
40 // To be used with float branch True
58 // To be used with float branch False
59 // This conditions have the same mnemonic as the
60 // above ones, but are used with a branch False;
79 /// GetOppositeBranchOpc - Return the inverse of the specified
80 /// opcode, e.g. turning BEQ to BNE.
81 unsigned GetOppositeBranchOpc(unsigned Opc);
83 /// MipsCCToString - Map each FP condition code to its string
84 inline static const char *MipsFCCToString(Mips::CondCode CC)
87 default: llvm_unreachable("Unknown condition code");
89 case FCOND_T: return "f";
91 case FCOND_OR: return "un";
93 case FCOND_UNE: return "eq";
95 case FCOND_ONE: return "ueq";
97 case FCOND_UGE: return "olt";
99 case FCOND_OGE: return "ult";
101 case FCOND_UGT: return "ole";
103 case FCOND_OGT: return "ule";
105 case FCOND_ST: return "sf";
107 case FCOND_GLE: return "ngle";
109 case FCOND_SNE: return "seq";
111 case FCOND_GL: return "ngl";
113 case FCOND_NLT: return "lt";
115 case FCOND_GE: return "nge";
117 case FCOND_NLE: return "le";
119 case FCOND_GT: return "ngt";
124 /// MipsII - This namespace holds all of the target specific flags that
125 /// instruction info tracks.
128 /// Target Operand Flag enum.
130 //===------------------------------------------------------------------===//
131 // Mips Specific MachineOperand flags.
135 /// MO_GOT - Represents the offset into the global offset table at which
136 /// the address the relocation entry symbol resides during execution.
139 /// MO_GOT_CALL - Represents the offset into the global offset table at
140 /// which the address of a call site relocation entry symbol resides
141 /// during execution. This is different from the above since this flag
142 /// can only be present in call instructions.
145 /// MO_GPREL - Represents the offset from the current gp value to be used
146 /// for the relocatable object file being produced.
149 /// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
154 /// MO_TLSGD - Represents the offset into the global offset table at which
155 // the module ID and TSL block offset reside during execution (General
159 /// MO_GOTTPREL - Represents the offset from the thread pointer (Initial
163 /// MO_TPREL_HI/LO - Represents the hi and low part of the offset from
164 // the thread pointer (Local Exec TLS).
170 class MipsInstrInfo : public MipsGenInstrInfo {
171 MipsTargetMachine &TM;
172 const MipsRegisterInfo RI;
174 explicit MipsInstrInfo(MipsTargetMachine &TM);
176 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
177 /// such, whenever a client has an instance of instruction info, it should
178 /// always be able to get register info as well (through this method).
180 virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
182 /// isLoadFromStackSlot - If the specified machine instruction is a direct
183 /// load from a stack slot, return the virtual or physical register number of
184 /// the destination along with the FrameIndex of the loaded stack slot. If
185 /// not, return 0. This predicate must return 0 if the instruction has
186 /// any side effects other than loading from the stack slot.
187 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
188 int &FrameIndex) const;
190 /// isStoreToStackSlot - If the specified machine instruction is a direct
191 /// store to a stack slot, return the virtual or physical register number of
192 /// the source reg along with the FrameIndex of the loaded stack slot. If
193 /// not, return 0. This predicate must return 0 if the instruction has
194 /// any side effects other than storing to the stack slot.
195 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
196 int &FrameIndex) const;
199 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
200 MachineBasicBlock *&FBB,
201 SmallVectorImpl<MachineOperand> &Cond,
202 bool AllowModify) const;
203 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
206 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
207 const SmallVectorImpl<MachineOperand>& Cond) const;
210 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
211 MachineBasicBlock *FBB,
212 const SmallVectorImpl<MachineOperand> &Cond,
214 virtual void copyPhysReg(MachineBasicBlock &MBB,
215 MachineBasicBlock::iterator MI, DebugLoc DL,
216 unsigned DestReg, unsigned SrcReg,
218 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator MBBI,
220 unsigned SrcReg, bool isKill, int FrameIndex,
221 const TargetRegisterClass *RC,
222 const TargetRegisterInfo *TRI) const;
224 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
225 MachineBasicBlock::iterator MBBI,
226 unsigned DestReg, int FrameIndex,
227 const TargetRegisterClass *RC,
228 const TargetRegisterInfo *TRI) const;
230 virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
231 int FrameIx, uint64_t Offset,
236 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
238 /// Insert nop instruction when hazard condition is found
239 virtual void insertNoop(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator MI) const;
242 /// getGlobalBaseReg - Return a virtual register initialized with the
243 /// the global base register value. Output instructions required to
244 /// initialize the register in the function entry block, if necessary.
246 unsigned getGlobalBaseReg(MachineFunction *MF) const;