1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "MipsGenInstrInfo.inc"
22 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
23 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
24 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
26 static bool isZeroImm(const MachineOperand &op) {
27 return op.isImm() && op.getImm() == 0;
30 /// Return true if the instruction is a register to register move and
31 /// leave the source and dest operands in the passed parameters.
33 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
34 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
36 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
38 // addu $dst, $src, $zero || addu $dst, $zero, $src
39 // or $dst, $src, $zero || or $dst, $zero, $src
40 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
41 if (MI.getOperand(1).getReg() == Mips::ZERO) {
42 DstReg = MI.getOperand(0).getReg();
43 SrcReg = MI.getOperand(2).getReg();
45 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
46 DstReg = MI.getOperand(0).getReg();
47 SrcReg = MI.getOperand(1).getReg();
55 if (MI.getOpcode() == Mips::FMOV_SO32 || MI.getOpcode() == Mips::FMOV_AS32 ||
56 MI.getOpcode() == Mips::FMOV_D32 || MI.getOpcode() == Mips::MFC1A ||
57 MI.getOpcode() == Mips::MFC1 || MI.getOpcode() == Mips::MTC1A ||
58 MI.getOpcode() == Mips::MTC1 ) {
59 DstReg = MI.getOperand(0).getReg();
60 SrcReg = MI.getOperand(1).getReg();
64 // addiu $dst, $src, 0
65 if (MI.getOpcode() == Mips::ADDiu) {
66 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
67 DstReg = MI.getOperand(0).getReg();
68 SrcReg = MI.getOperand(1).getReg();
75 /// isLoadFromStackSlot - If the specified machine instruction is a direct
76 /// load from a stack slot, return the virtual or physical register number of
77 /// the destination along with the FrameIndex of the loaded stack slot. If
78 /// not, return 0. This predicate must return 0 if the instruction has
79 /// any side effects other than loading from the stack slot.
80 unsigned MipsInstrInfo::
81 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
83 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
84 (MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) {
85 if ((MI->getOperand(2).isFI()) && // is a stack slot
86 (MI->getOperand(1).isImm()) && // the imm is zero
87 (isZeroImm(MI->getOperand(1)))) {
88 FrameIndex = MI->getOperand(2).getIndex();
89 return MI->getOperand(0).getReg();
96 /// isStoreToStackSlot - If the specified machine instruction is a direct
97 /// store to a stack slot, return the virtual or physical register number of
98 /// the source reg along with the FrameIndex of the loaded stack slot. If
99 /// not, return 0. This predicate must return 0 if the instruction has
100 /// any side effects other than storing to the stack slot.
101 unsigned MipsInstrInfo::
102 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
104 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
105 (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
106 if ((MI->getOperand(2).isFI()) && // is a stack slot
107 (MI->getOperand(1).isImm()) && // the imm is zero
108 (isZeroImm(MI->getOperand(1)))) {
109 FrameIndex = MI->getOperand(2).getIndex();
110 return MI->getOperand(0).getReg();
116 /// insertNoop - If data hazard condition is found insert the target nop
119 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
121 DebugLoc DL = DebugLoc::getUnknownLoc();
122 if (MI != MBB.end()) DL = MI->getDebugLoc();
123 BuildMI(MBB, MI, DL, get(Mips::NOP));
127 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
128 unsigned DestReg, unsigned SrcReg,
129 const TargetRegisterClass *DestRC,
130 const TargetRegisterClass *SrcRC) const {
131 DebugLoc DL = DebugLoc::getUnknownLoc();
132 if (I != MBB.end()) DL = I->getDebugLoc();
134 if (DestRC != SrcRC) {
135 if ((DestRC == Mips::CPURegsRegisterClass) &&
136 (SrcRC == Mips::FGR32RegisterClass))
137 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
138 else if ((DestRC == Mips::CPURegsRegisterClass) &&
139 (SrcRC == Mips::AFGR32RegisterClass))
140 BuildMI(MBB, I, DL, get(Mips::MFC1A), DestReg).addReg(SrcReg);
141 else if ((DestRC == Mips::FGR32RegisterClass) &&
142 (SrcRC == Mips::CPURegsRegisterClass))
143 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
144 else if ((DestRC == Mips::AFGR32RegisterClass) &&
145 (SrcRC == Mips::CPURegsRegisterClass))
146 BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg);
147 else if ((DestRC == Mips::AFGR32RegisterClass) &&
148 (SrcRC == Mips::CPURegsRegisterClass))
149 BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg);
150 else if ((SrcRC == Mips::CCRRegisterClass) &&
151 (SrcReg == Mips::FCR31))
152 return true; // This register is used implicitly, no copy needed.
153 else if ((DestRC == Mips::CCRRegisterClass) &&
154 (DestReg == Mips::FCR31))
155 return true; // This register is used implicitly, no copy needed.
156 else if ((DestRC == Mips::HILORegisterClass) &&
157 (SrcRC == Mips::CPURegsRegisterClass)) {
158 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
159 BuildMI(MBB, I, DL, get(Opc), DestReg);
160 } else if ((SrcRC == Mips::HILORegisterClass) &&
161 (DestRC == Mips::CPURegsRegisterClass)) {
162 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
163 BuildMI(MBB, I, DL, get(Opc), DestReg);
165 // DestRC != SrcRC, Can't copy this register
171 if (DestRC == Mips::CPURegsRegisterClass)
172 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
174 else if (DestRC == Mips::FGR32RegisterClass)
175 BuildMI(MBB, I, DL, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg);
176 else if (DestRC == Mips::AFGR32RegisterClass)
177 BuildMI(MBB, I, DL, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg);
178 else if (DestRC == Mips::AFGR64RegisterClass)
179 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
181 // Can't copy this register
188 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
189 unsigned SrcReg, bool isKill, int FI,
190 const TargetRegisterClass *RC) const
194 DebugLoc DL = DebugLoc::getUnknownLoc();
195 if (I != MBB.end()) DL = I->getDebugLoc();
197 if (RC == Mips::CPURegsRegisterClass)
199 else if (RC == Mips::FGR32RegisterClass)
201 else if (RC == Mips::AFGR32RegisterClass)
203 else if (RC == Mips::AFGR64RegisterClass)
206 assert(0 && "Can't store this register to stack slot");
208 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill)
209 .addImm(0).addFrameIndex(FI);
212 void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
213 bool isKill, SmallVectorImpl<MachineOperand> &Addr,
214 const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
217 if (RC == Mips::CPURegsRegisterClass)
219 else if (RC == Mips::FGR32RegisterClass)
221 else if (RC == Mips::AFGR32RegisterClass)
223 else if (RC == Mips::AFGR64RegisterClass)
226 assert(0 && "Can't store this register");
228 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
229 .addReg(SrcReg, false, false, isKill);
230 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
231 MachineOperand &MO = Addr[i];
233 MIB.addReg(MO.getReg());
235 MIB.addImm(MO.getImm());
237 MIB.addFrameIndex(MO.getIndex());
239 NewMIs.push_back(MIB);
244 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
245 unsigned DestReg, int FI,
246 const TargetRegisterClass *RC) const
249 if (RC == Mips::CPURegsRegisterClass)
251 else if (RC == Mips::FGR32RegisterClass)
253 else if (RC == Mips::AFGR32RegisterClass)
255 else if (RC == Mips::AFGR64RegisterClass)
258 assert(0 && "Can't load this register from stack slot");
260 DebugLoc DL = DebugLoc::getUnknownLoc();
261 if (I != MBB.end()) DL = I->getDebugLoc();
262 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
265 void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
266 SmallVectorImpl<MachineOperand> &Addr,
267 const TargetRegisterClass *RC,
268 SmallVectorImpl<MachineInstr*> &NewMIs) const {
270 if (RC == Mips::CPURegsRegisterClass)
272 else if (RC == Mips::FGR32RegisterClass)
274 else if (RC == Mips::AFGR32RegisterClass)
276 else if (RC == Mips::AFGR64RegisterClass)
279 assert(0 && "Can't load this register");
281 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
282 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
283 MachineOperand &MO = Addr[i];
285 MIB.addReg(MO.getReg());
287 MIB.addImm(MO.getImm());
289 MIB.addFrameIndex(MO.getIndex());
291 NewMIs.push_back(MIB);
295 MachineInstr *MipsInstrInfo::
296 foldMemoryOperandImpl(MachineFunction &MF,
298 const SmallVectorImpl<unsigned> &Ops, int FI) const
300 if (Ops.size() != 1) return NULL;
302 MachineInstr *NewMI = NULL;
304 switch (MI->getOpcode()) {
306 if ((MI->getOperand(0).isReg()) &&
307 (MI->getOperand(1).isReg()) &&
308 (MI->getOperand(1).getReg() == Mips::ZERO) &&
309 (MI->getOperand(2).isReg())) {
310 if (Ops[0] == 0) { // COPY -> STORE
311 unsigned SrcReg = MI->getOperand(2).getReg();
312 bool isKill = MI->getOperand(2).isKill();
313 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
314 .addReg(SrcReg, false, false, isKill)
315 .addImm(0).addFrameIndex(FI);
316 } else { // COPY -> LOAD
317 unsigned DstReg = MI->getOperand(0).getReg();
318 bool isDead = MI->getOperand(0).isDead();
319 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
320 .addReg(DstReg, true, false, false, isDead)
321 .addImm(0).addFrameIndex(FI);
325 case Mips::FMOV_SO32:
326 case Mips::FMOV_AS32:
328 if ((MI->getOperand(0).isReg()) &&
329 (MI->getOperand(1).isReg())) {
330 const TargetRegisterClass
331 *RC = RI.getRegClass(MI->getOperand(0).getReg());
332 unsigned StoreOpc, LoadOpc;
334 if (RC == Mips::FGR32RegisterClass) {
335 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
336 } else if (RC == Mips::AFGR32RegisterClass) {
337 LoadOpc = Mips::LWC1A; StoreOpc = Mips::SWC1A;
338 } else if (RC == Mips::AFGR64RegisterClass) {
339 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
341 assert(0 && "foldMemoryOperandImpl register unknown");
343 if (Ops[0] == 0) { // COPY -> STORE
344 unsigned SrcReg = MI->getOperand(1).getReg();
345 bool isKill = MI->getOperand(1).isKill();
346 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
347 .addReg(SrcReg, false, false, isKill)
348 .addImm(0).addFrameIndex(FI) ;
349 } else { // COPY -> LOAD
350 unsigned DstReg = MI->getOperand(0).getReg();
351 bool isDead = MI->getOperand(0).isDead();
352 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
353 .addReg(DstReg, true, false, false, isDead)
354 .addImm(0).addFrameIndex(FI);
363 //===----------------------------------------------------------------------===//
365 //===----------------------------------------------------------------------===//
367 /// GetCondFromBranchOpc - Return the Mips CC that matches
368 /// the correspondent Branch instruction opcode.
369 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
372 default: return Mips::COND_INVALID;
373 case Mips::BEQ : return Mips::COND_E;
374 case Mips::BNE : return Mips::COND_NE;
375 case Mips::BGTZ : return Mips::COND_GZ;
376 case Mips::BGEZ : return Mips::COND_GEZ;
377 case Mips::BLTZ : return Mips::COND_LZ;
378 case Mips::BLEZ : return Mips::COND_LEZ;
380 // We dont do fp branch analysis yet!
382 case Mips::BC1F : return Mips::COND_INVALID;
386 /// GetCondBranchFromCond - Return the Branch instruction
387 /// opcode that matches the cc.
388 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
391 default: assert(0 && "Illegal condition code!");
392 case Mips::COND_E : return Mips::BEQ;
393 case Mips::COND_NE : return Mips::BNE;
394 case Mips::COND_GZ : return Mips::BGTZ;
395 case Mips::COND_GEZ : return Mips::BGEZ;
396 case Mips::COND_LZ : return Mips::BLTZ;
397 case Mips::COND_LEZ : return Mips::BLEZ;
402 case Mips::FCOND_UEQ:
403 case Mips::FCOND_OLT:
404 case Mips::FCOND_ULT:
405 case Mips::FCOND_OLE:
406 case Mips::FCOND_ULE:
408 case Mips::FCOND_NGLE:
409 case Mips::FCOND_SEQ:
410 case Mips::FCOND_NGL:
412 case Mips::FCOND_NGE:
414 case Mips::FCOND_NGT: return Mips::BC1T;
418 case Mips::FCOND_NEQ:
419 case Mips::FCOND_OGL:
420 case Mips::FCOND_UGE:
421 case Mips::FCOND_OGE:
422 case Mips::FCOND_UGT:
423 case Mips::FCOND_OGT:
425 case Mips::FCOND_GLE:
426 case Mips::FCOND_SNE:
428 case Mips::FCOND_NLT:
430 case Mips::FCOND_NLE:
431 case Mips::FCOND_GT: return Mips::BC1F;
435 /// GetOppositeBranchCondition - Return the inverse of the specified
436 /// condition, e.g. turning COND_E to COND_NE.
437 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
440 default: assert(0 && "Illegal condition code!");
441 case Mips::COND_E : return Mips::COND_NE;
442 case Mips::COND_NE : return Mips::COND_E;
443 case Mips::COND_GZ : return Mips::COND_LEZ;
444 case Mips::COND_GEZ : return Mips::COND_LZ;
445 case Mips::COND_LZ : return Mips::COND_GEZ;
446 case Mips::COND_LEZ : return Mips::COND_GZ;
447 case Mips::FCOND_F : return Mips::FCOND_T;
448 case Mips::FCOND_UN : return Mips::FCOND_OR;
449 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
450 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
451 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
452 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
453 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
454 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
455 case Mips::FCOND_SF: return Mips::FCOND_ST;
456 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
457 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
458 case Mips::FCOND_NGL: return Mips::FCOND_GL;
459 case Mips::FCOND_LT: return Mips::FCOND_NLT;
460 case Mips::FCOND_NGE: return Mips::FCOND_GE;
461 case Mips::FCOND_LE: return Mips::FCOND_NLE;
462 case Mips::FCOND_NGT: return Mips::FCOND_GT;
466 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
467 MachineBasicBlock *&TBB,
468 MachineBasicBlock *&FBB,
469 SmallVectorImpl<MachineOperand> &Cond,
470 bool AllowModify) const
472 // If the block has no terminators, it just falls into the block after it.
473 MachineBasicBlock::iterator I = MBB.end();
474 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
477 // Get the last instruction in the block.
478 MachineInstr *LastInst = I;
480 // If there is only one terminator instruction, process it.
481 unsigned LastOpc = LastInst->getOpcode();
482 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
483 if (!LastInst->getDesc().isBranch())
486 // Unconditional branch
487 if (LastOpc == Mips::J) {
488 TBB = LastInst->getOperand(0).getMBB();
492 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
493 if (BranchCode == Mips::COND_INVALID)
494 return true; // Can't handle indirect branch.
496 // Conditional branch
497 // Block ends with fall-through condbranch.
498 if (LastOpc != Mips::COND_INVALID) {
499 int LastNumOp = LastInst->getNumOperands();
501 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
502 Cond.push_back(MachineOperand::CreateImm(BranchCode));
504 for (int i=0; i<LastNumOp-1; i++) {
505 Cond.push_back(LastInst->getOperand(i));
512 // Get the instruction before it if it is a terminator.
513 MachineInstr *SecondLastInst = I;
515 // If there are three terminators, we don't know what sort of block this is.
516 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
519 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
520 unsigned SecondLastOpc = SecondLastInst->getOpcode();
521 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
523 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
524 int SecondNumOp = SecondLastInst->getNumOperands();
526 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
527 Cond.push_back(MachineOperand::CreateImm(BranchCode));
529 for (int i=0; i<SecondNumOp-1; i++) {
530 Cond.push_back(SecondLastInst->getOperand(i));
533 FBB = LastInst->getOperand(0).getMBB();
537 // If the block ends with two unconditional branches, handle it. The last
538 // one is not executed, so remove it.
539 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
540 TBB = SecondLastInst->getOperand(0).getMBB();
543 I->eraseFromParent();
547 // Otherwise, can't handle this.
551 unsigned MipsInstrInfo::
552 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
553 MachineBasicBlock *FBB,
554 const SmallVectorImpl<MachineOperand> &Cond) const {
555 // Shouldn't be a fall through.
556 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
557 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
558 "Mips branch conditions can have two|three components!");
560 if (FBB == 0) { // One way branch.
562 // Unconditional branch?
563 BuildMI(&MBB, get(Mips::J)).addMBB(TBB);
565 // Conditional branch.
566 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
567 const TargetInstrDesc &TID = get(Opc);
569 if (TID.getNumOperands() == 3)
570 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
571 .addReg(Cond[2].getReg())
574 BuildMI(&MBB, TID).addReg(Cond[1].getReg())
581 // Two-way Conditional branch.
582 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
583 const TargetInstrDesc &TID = get(Opc);
585 if (TID.getNumOperands() == 3)
586 BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
589 BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
591 BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
595 unsigned MipsInstrInfo::
596 RemoveBranch(MachineBasicBlock &MBB) const
598 MachineBasicBlock::iterator I = MBB.end();
599 if (I == MBB.begin()) return 0;
601 if (I->getOpcode() != Mips::J &&
602 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
605 // Remove the branch.
606 I->eraseFromParent();
610 if (I == MBB.begin()) return 1;
612 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
615 // Remove the branch.
616 I->eraseFromParent();
620 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
621 /// fall-through into its successor block.
623 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
625 if (MBB.empty()) return false;
627 switch (MBB.back().getOpcode()) {
628 case Mips::RET: // Return.
629 case Mips::JR: // Indirect branch.
630 case Mips::J: // Uncond branch.
632 default: return false;
636 /// ReverseBranchCondition - Return the inverse opcode of the
637 /// specified Branch instruction.
639 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
641 assert( (Cond.size() == 3 || Cond.size() == 2) &&
642 "Invalid Mips branch condition!");
643 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));