1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "MipsGenInstrInfo.inc"
24 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
25 : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
26 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
28 static bool isZeroImm(const MachineOperand &op) {
29 return op.isImm() && op.getImm() == 0;
32 /// Return true if the instruction is a register to register move and
33 /// leave the source and dest operands in the passed parameters.
35 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
36 unsigned &SrcSubIdx, unsigned &DstSubIdx) const
38 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
40 // addu $dst, $src, $zero || addu $dst, $zero, $src
41 // or $dst, $src, $zero || or $dst, $zero, $src
42 if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
43 if (MI.getOperand(1).getReg() == Mips::ZERO) {
44 DstReg = MI.getOperand(0).getReg();
45 SrcReg = MI.getOperand(2).getReg();
47 } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
48 DstReg = MI.getOperand(0).getReg();
49 SrcReg = MI.getOperand(1).getReg();
57 if (MI.getOpcode() == Mips::FMOV_S32 ||
58 MI.getOpcode() == Mips::FMOV_D32 ||
59 MI.getOpcode() == Mips::MFC1 ||
60 MI.getOpcode() == Mips::MTC1 ||
61 MI.getOpcode() == Mips::MOVCCRToCCR) {
62 DstReg = MI.getOperand(0).getReg();
63 SrcReg = MI.getOperand(1).getReg();
67 // addiu $dst, $src, 0
68 if (MI.getOpcode() == Mips::ADDiu) {
69 if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
70 DstReg = MI.getOperand(0).getReg();
71 SrcReg = MI.getOperand(1).getReg();
79 /// isLoadFromStackSlot - If the specified machine instruction is a direct
80 /// load from a stack slot, return the virtual or physical register number of
81 /// the destination along with the FrameIndex of the loaded stack slot. If
82 /// not, return 0. This predicate must return 0 if the instruction has
83 /// any side effects other than loading from the stack slot.
84 unsigned MipsInstrInfo::
85 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
87 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
88 (MI->getOpcode() == Mips::LDC1)) {
89 if ((MI->getOperand(2).isFI()) && // is a stack slot
90 (MI->getOperand(1).isImm()) && // the imm is zero
91 (isZeroImm(MI->getOperand(1)))) {
92 FrameIndex = MI->getOperand(2).getIndex();
93 return MI->getOperand(0).getReg();
100 /// isStoreToStackSlot - If the specified machine instruction is a direct
101 /// store to a stack slot, return the virtual or physical register number of
102 /// the source reg along with the FrameIndex of the loaded stack slot. If
103 /// not, return 0. This predicate must return 0 if the instruction has
104 /// any side effects other than storing to the stack slot.
105 unsigned MipsInstrInfo::
106 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
108 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
109 (MI->getOpcode() == Mips::SDC1)) {
110 if ((MI->getOperand(2).isFI()) && // is a stack slot
111 (MI->getOperand(1).isImm()) && // the imm is zero
112 (isZeroImm(MI->getOperand(1)))) {
113 FrameIndex = MI->getOperand(2).getIndex();
114 return MI->getOperand(0).getReg();
120 /// insertNoop - If data hazard condition is found insert the target nop
123 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
125 DebugLoc DL = DebugLoc::getUnknownLoc();
126 if (MI != MBB.end()) DL = MI->getDebugLoc();
127 BuildMI(MBB, MI, DL, get(Mips::NOP));
131 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
132 unsigned DestReg, unsigned SrcReg,
133 const TargetRegisterClass *DestRC,
134 const TargetRegisterClass *SrcRC) const {
135 DebugLoc DL = DebugLoc::getUnknownLoc();
136 if (I != MBB.end()) DL = I->getDebugLoc();
138 if (DestRC != SrcRC) {
140 // Copy to/from FCR31 condition register
141 if ((DestRC == Mips::CPURegsRegisterClass) &&
142 (SrcRC == Mips::CCRRegisterClass))
143 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
144 else if ((DestRC == Mips::CCRRegisterClass) &&
145 (SrcRC == Mips::CPURegsRegisterClass))
146 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
148 // Moves between coprocessors and cpu
149 else if ((DestRC == Mips::CPURegsRegisterClass) &&
150 (SrcRC == Mips::FGR32RegisterClass))
151 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
152 else if ((DestRC == Mips::FGR32RegisterClass) &&
153 (SrcRC == Mips::CPURegsRegisterClass))
154 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
156 // Move from/to Hi/Lo registers
157 else if ((DestRC == Mips::HILORegisterClass) &&
158 (SrcRC == Mips::CPURegsRegisterClass)) {
159 unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
160 BuildMI(MBB, I, DL, get(Opc), DestReg);
161 } else if ((SrcRC == Mips::HILORegisterClass) &&
162 (DestRC == Mips::CPURegsRegisterClass)) {
163 unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
164 BuildMI(MBB, I, DL, get(Opc), DestReg);
166 // Can't copy this register
173 if (DestRC == Mips::CPURegsRegisterClass)
174 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
176 else if (DestRC == Mips::FGR32RegisterClass)
177 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
178 else if (DestRC == Mips::AFGR64RegisterClass)
179 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
180 else if (DestRC == Mips::CCRRegisterClass)
181 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
183 // Can't copy this register
190 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
191 unsigned SrcReg, bool isKill, int FI,
192 const TargetRegisterClass *RC) const {
195 DebugLoc DL = DebugLoc::getUnknownLoc();
196 if (I != MBB.end()) DL = I->getDebugLoc();
198 if (RC == Mips::CPURegsRegisterClass)
200 else if (RC == Mips::FGR32RegisterClass)
203 assert(RC == Mips::AFGR64RegisterClass);
207 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
208 .addImm(0).addFrameIndex(FI);
211 void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
212 bool isKill, SmallVectorImpl<MachineOperand> &Addr,
213 const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
216 if (RC == Mips::CPURegsRegisterClass)
218 else if (RC == Mips::FGR32RegisterClass)
221 assert(RC == Mips::AFGR64RegisterClass);
225 DebugLoc DL = DebugLoc::getUnknownLoc();
226 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
227 .addReg(SrcReg, getKillRegState(isKill));
228 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
229 MIB.addOperand(Addr[i]);
230 NewMIs.push_back(MIB);
235 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
236 unsigned DestReg, int FI,
237 const TargetRegisterClass *RC) const
240 if (RC == Mips::CPURegsRegisterClass)
242 else if (RC == Mips::FGR32RegisterClass)
245 assert(RC == Mips::AFGR64RegisterClass);
249 DebugLoc DL = DebugLoc::getUnknownLoc();
250 if (I != MBB.end()) DL = I->getDebugLoc();
251 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
254 void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
255 SmallVectorImpl<MachineOperand> &Addr,
256 const TargetRegisterClass *RC,
257 SmallVectorImpl<MachineInstr*> &NewMIs) const {
259 if (RC == Mips::CPURegsRegisterClass)
261 else if (RC == Mips::FGR32RegisterClass)
264 assert(RC == Mips::AFGR64RegisterClass);
268 DebugLoc DL = DebugLoc::getUnknownLoc();
269 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
270 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
271 MIB.addOperand(Addr[i]);
272 NewMIs.push_back(MIB);
276 MachineInstr *MipsInstrInfo::
277 foldMemoryOperandImpl(MachineFunction &MF,
279 const SmallVectorImpl<unsigned> &Ops, int FI) const
281 if (Ops.size() != 1) return NULL;
283 MachineInstr *NewMI = NULL;
285 switch (MI->getOpcode()) {
287 if ((MI->getOperand(0).isReg()) &&
288 (MI->getOperand(1).isReg()) &&
289 (MI->getOperand(1).getReg() == Mips::ZERO) &&
290 (MI->getOperand(2).isReg())) {
291 if (Ops[0] == 0) { // COPY -> STORE
292 unsigned SrcReg = MI->getOperand(2).getReg();
293 bool isKill = MI->getOperand(2).isKill();
294 bool isUndef = MI->getOperand(2).isUndef();
295 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
296 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
297 .addImm(0).addFrameIndex(FI);
298 } else { // COPY -> LOAD
299 unsigned DstReg = MI->getOperand(0).getReg();
300 bool isDead = MI->getOperand(0).isDead();
301 bool isUndef = MI->getOperand(0).isUndef();
302 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
303 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
304 getUndefRegState(isUndef))
305 .addImm(0).addFrameIndex(FI);
311 if ((MI->getOperand(0).isReg()) &&
312 (MI->getOperand(1).isReg())) {
313 const TargetRegisterClass
314 *RC = RI.getRegClass(MI->getOperand(0).getReg());
315 unsigned StoreOpc, LoadOpc;
317 if (RC == Mips::FGR32RegisterClass) {
318 LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
320 assert(RC == Mips::AFGR64RegisterClass);
321 LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
324 if (Ops[0] == 0) { // COPY -> STORE
325 unsigned SrcReg = MI->getOperand(1).getReg();
326 bool isKill = MI->getOperand(1).isKill();
327 bool isUndef = MI->getOperand(2).isUndef();
328 NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
329 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
330 .addImm(0).addFrameIndex(FI) ;
331 } else { // COPY -> LOAD
332 unsigned DstReg = MI->getOperand(0).getReg();
333 bool isDead = MI->getOperand(0).isDead();
334 bool isUndef = MI->getOperand(0).isUndef();
335 NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
336 .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
337 getUndefRegState(isUndef))
338 .addImm(0).addFrameIndex(FI);
347 //===----------------------------------------------------------------------===//
349 //===----------------------------------------------------------------------===//
351 /// GetCondFromBranchOpc - Return the Mips CC that matches
352 /// the correspondent Branch instruction opcode.
353 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
356 default: return Mips::COND_INVALID;
357 case Mips::BEQ : return Mips::COND_E;
358 case Mips::BNE : return Mips::COND_NE;
359 case Mips::BGTZ : return Mips::COND_GZ;
360 case Mips::BGEZ : return Mips::COND_GEZ;
361 case Mips::BLTZ : return Mips::COND_LZ;
362 case Mips::BLEZ : return Mips::COND_LEZ;
364 // We dont do fp branch analysis yet!
366 case Mips::BC1F : return Mips::COND_INVALID;
370 /// GetCondBranchFromCond - Return the Branch instruction
371 /// opcode that matches the cc.
372 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
375 default: assert(0 && "Illegal condition code!");
376 case Mips::COND_E : return Mips::BEQ;
377 case Mips::COND_NE : return Mips::BNE;
378 case Mips::COND_GZ : return Mips::BGTZ;
379 case Mips::COND_GEZ : return Mips::BGEZ;
380 case Mips::COND_LZ : return Mips::BLTZ;
381 case Mips::COND_LEZ : return Mips::BLEZ;
386 case Mips::FCOND_UEQ:
387 case Mips::FCOND_OLT:
388 case Mips::FCOND_ULT:
389 case Mips::FCOND_OLE:
390 case Mips::FCOND_ULE:
392 case Mips::FCOND_NGLE:
393 case Mips::FCOND_SEQ:
394 case Mips::FCOND_NGL:
396 case Mips::FCOND_NGE:
398 case Mips::FCOND_NGT: return Mips::BC1T;
402 case Mips::FCOND_NEQ:
403 case Mips::FCOND_OGL:
404 case Mips::FCOND_UGE:
405 case Mips::FCOND_OGE:
406 case Mips::FCOND_UGT:
407 case Mips::FCOND_OGT:
409 case Mips::FCOND_GLE:
410 case Mips::FCOND_SNE:
412 case Mips::FCOND_NLT:
414 case Mips::FCOND_NLE:
415 case Mips::FCOND_GT: return Mips::BC1F;
419 /// GetOppositeBranchCondition - Return the inverse of the specified
420 /// condition, e.g. turning COND_E to COND_NE.
421 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
424 default: assert(0 && "Illegal condition code!");
425 case Mips::COND_E : return Mips::COND_NE;
426 case Mips::COND_NE : return Mips::COND_E;
427 case Mips::COND_GZ : return Mips::COND_LEZ;
428 case Mips::COND_GEZ : return Mips::COND_LZ;
429 case Mips::COND_LZ : return Mips::COND_GEZ;
430 case Mips::COND_LEZ : return Mips::COND_GZ;
431 case Mips::FCOND_F : return Mips::FCOND_T;
432 case Mips::FCOND_UN : return Mips::FCOND_OR;
433 case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
434 case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
435 case Mips::FCOND_OLT: return Mips::FCOND_UGE;
436 case Mips::FCOND_ULT: return Mips::FCOND_OGE;
437 case Mips::FCOND_OLE: return Mips::FCOND_UGT;
438 case Mips::FCOND_ULE: return Mips::FCOND_OGT;
439 case Mips::FCOND_SF: return Mips::FCOND_ST;
440 case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
441 case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
442 case Mips::FCOND_NGL: return Mips::FCOND_GL;
443 case Mips::FCOND_LT: return Mips::FCOND_NLT;
444 case Mips::FCOND_NGE: return Mips::FCOND_GE;
445 case Mips::FCOND_LE: return Mips::FCOND_NLE;
446 case Mips::FCOND_NGT: return Mips::FCOND_GT;
450 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
451 MachineBasicBlock *&TBB,
452 MachineBasicBlock *&FBB,
453 SmallVectorImpl<MachineOperand> &Cond,
454 bool AllowModify) const
456 // If the block has no terminators, it just falls into the block after it.
457 MachineBasicBlock::iterator I = MBB.end();
458 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
461 // Get the last instruction in the block.
462 MachineInstr *LastInst = I;
464 // If there is only one terminator instruction, process it.
465 unsigned LastOpc = LastInst->getOpcode();
466 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
467 if (!LastInst->getDesc().isBranch())
470 // Unconditional branch
471 if (LastOpc == Mips::J) {
472 TBB = LastInst->getOperand(0).getMBB();
476 Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
477 if (BranchCode == Mips::COND_INVALID)
478 return true; // Can't handle indirect branch.
480 // Conditional branch
481 // Block ends with fall-through condbranch.
482 if (LastOpc != Mips::COND_INVALID) {
483 int LastNumOp = LastInst->getNumOperands();
485 TBB = LastInst->getOperand(LastNumOp-1).getMBB();
486 Cond.push_back(MachineOperand::CreateImm(BranchCode));
488 for (int i=0; i<LastNumOp-1; i++) {
489 Cond.push_back(LastInst->getOperand(i));
496 // Get the instruction before it if it is a terminator.
497 MachineInstr *SecondLastInst = I;
499 // If there are three terminators, we don't know what sort of block this is.
500 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
503 // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
504 unsigned SecondLastOpc = SecondLastInst->getOpcode();
505 Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
507 if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
508 int SecondNumOp = SecondLastInst->getNumOperands();
510 TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
511 Cond.push_back(MachineOperand::CreateImm(BranchCode));
513 for (int i=0; i<SecondNumOp-1; i++) {
514 Cond.push_back(SecondLastInst->getOperand(i));
517 FBB = LastInst->getOperand(0).getMBB();
521 // If the block ends with two unconditional branches, handle it. The last
522 // one is not executed, so remove it.
523 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
524 TBB = SecondLastInst->getOperand(0).getMBB();
527 I->eraseFromParent();
531 // Otherwise, can't handle this.
535 unsigned MipsInstrInfo::
536 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
537 MachineBasicBlock *FBB,
538 const SmallVectorImpl<MachineOperand> &Cond) const {
539 // FIXME this should probably have a DebugLoc argument
540 DebugLoc dl = DebugLoc::getUnknownLoc();
541 // Shouldn't be a fall through.
542 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
543 assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
544 "Mips branch conditions can have two|three components!");
546 if (FBB == 0) { // One way branch.
548 // Unconditional branch?
549 BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
551 // Conditional branch.
552 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
553 const TargetInstrDesc &TID = get(Opc);
555 if (TID.getNumOperands() == 3)
556 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
557 .addReg(Cond[2].getReg())
560 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
567 // Two-way Conditional branch.
568 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
569 const TargetInstrDesc &TID = get(Opc);
571 if (TID.getNumOperands() == 3)
572 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
575 BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
577 BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
581 unsigned MipsInstrInfo::
582 RemoveBranch(MachineBasicBlock &MBB) const
584 MachineBasicBlock::iterator I = MBB.end();
585 if (I == MBB.begin()) return 0;
587 if (I->getOpcode() != Mips::J &&
588 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
591 // Remove the branch.
592 I->eraseFromParent();
596 if (I == MBB.begin()) return 1;
598 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
601 // Remove the branch.
602 I->eraseFromParent();
606 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
607 /// fall-through into its successor block.
609 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
611 if (MBB.empty()) return false;
613 switch (MBB.back().getOpcode()) {
614 case Mips::RET: // Return.
615 case Mips::JR: // Indirect branch.
616 case Mips::J: // Uncond branch.
618 default: return false;
622 /// ReverseBranchCondition - Return the inverse opcode of the
623 /// specified Branch instruction.
625 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
627 assert( (Cond.size() == 3 || Cond.size() == 2) &&
628 "Invalid Mips branch condition!");
629 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
633 /// getGlobalBaseReg - Return a virtual register initialized with the
634 /// the global base register value. Output instructions required to
635 /// initialize the register in the function entry block, if necessary.
637 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
638 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
639 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
640 if (GlobalBaseReg != 0)
641 return GlobalBaseReg;
643 // Insert the set of GlobalBaseReg into the first MBB of the function
644 MachineBasicBlock &FirstMBB = MF->front();
645 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
646 MachineRegisterInfo &RegInfo = MF->getRegInfo();
647 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
649 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
650 bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
651 Mips::CPURegsRegisterClass,
652 Mips::CPURegsRegisterClass);
653 assert(Ok && "Couldn't assign to global base register!");
654 RegInfo.addLiveIn(Mips::GP);
656 MipsFI->setGlobalBaseReg(GlobalBaseReg);
657 return GlobalBaseReg;