1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
24 #define GET_INSTRINFO_CTOR
25 #include "MipsGenInstrInfo.inc"
29 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
30 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
31 TM(tm), IsN64(TM.getSubtarget<MipsSubtarget>().isABI_N64()),
32 RI(*TM.getSubtargetImpl(), *this),
33 UncondBrOpc(TM.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J) {}
35 const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
39 static bool isZeroImm(const MachineOperand &op) {
40 return op.isImm() && op.getImm() == 0;
43 /// isLoadFromStackSlot - If the specified machine instruction is a direct
44 /// load from a stack slot, return the virtual or physical register number of
45 /// the destination along with the FrameIndex of the loaded stack slot. If
46 /// not, return 0. This predicate must return 0 if the instruction has
47 /// any side effects other than loading from the stack slot.
48 unsigned MipsInstrInfo::
49 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
51 unsigned Opc = MI->getOpcode();
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
56 (Opc == Mips::LDC164_P8)) {
57 if ((MI->getOperand(1).isFI()) && // is a stack slot
58 (MI->getOperand(2).isImm()) && // the imm is zero
59 (isZeroImm(MI->getOperand(2)))) {
60 FrameIndex = MI->getOperand(1).getIndex();
61 return MI->getOperand(0).getReg();
68 /// isStoreToStackSlot - If the specified machine instruction is a direct
69 /// store to a stack slot, return the virtual or physical register number of
70 /// the source reg along with the FrameIndex of the loaded stack slot. If
71 /// not, return 0. This predicate must return 0 if the instruction has
72 /// any side effects other than storing to the stack slot.
73 unsigned MipsInstrInfo::
74 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
76 unsigned Opc = MI->getOpcode();
78 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) ||
79 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) ||
80 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) ||
81 (Opc == Mips::SDC164_P8)) {
82 if ((MI->getOperand(1).isFI()) && // is a stack slot
83 (MI->getOperand(2).isImm()) && // the imm is zero
84 (isZeroImm(MI->getOperand(2)))) {
85 FrameIndex = MI->getOperand(1).getIndex();
86 return MI->getOperand(0).getReg();
92 /// insertNoop - If data hazard condition is found insert the target nop
95 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
98 BuildMI(MBB, MI, DL, get(Mips::NOP));
102 copyPhysReg(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator I, DebugLoc DL,
104 unsigned DestReg, unsigned SrcReg,
105 bool KillSrc) const {
106 unsigned Opc = 0, ZeroReg = 0;
108 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
109 if (Mips::CPURegsRegClass.contains(SrcReg))
110 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
111 else if (Mips::CCRRegClass.contains(SrcReg))
113 else if (Mips::FGR32RegClass.contains(SrcReg))
115 else if (SrcReg == Mips::HI)
116 Opc = Mips::MFHI, SrcReg = 0;
117 else if (SrcReg == Mips::LO)
118 Opc = Mips::MFLO, SrcReg = 0;
120 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
121 if (Mips::CCRRegClass.contains(DestReg))
123 else if (Mips::FGR32RegClass.contains(DestReg))
125 else if (DestReg == Mips::HI)
126 Opc = Mips::MTHI, DestReg = 0;
127 else if (DestReg == Mips::LO)
128 Opc = Mips::MTLO, DestReg = 0;
130 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
132 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
133 Opc = Mips::FMOV_D32;
134 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
135 Opc = Mips::FMOV_D64;
136 else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
137 Opc = Mips::MOVCCRToCCR;
138 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
139 if (Mips::CPU64RegsRegClass.contains(SrcReg))
140 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
141 else if (SrcReg == Mips::HI64)
142 Opc = Mips::MFHI64, SrcReg = 0;
143 else if (SrcReg == Mips::LO64)
144 Opc = Mips::MFLO64, SrcReg = 0;
145 else if (Mips::FGR64RegClass.contains(SrcReg))
148 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
149 if (DestReg == Mips::HI64)
150 Opc = Mips::MTHI64, DestReg = 0;
151 else if (DestReg == Mips::LO64)
152 Opc = Mips::MTLO64, DestReg = 0;
153 else if (Mips::FGR64RegClass.contains(DestReg))
157 assert(Opc && "Cannot copy registers");
159 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
162 MIB.addReg(DestReg, RegState::Define);
168 MIB.addReg(SrcReg, getKillRegState(KillSrc));
171 static MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI,
173 MachineFunction &MF = *MBB.getParent();
174 MachineFrameInfo &MFI = *MF.getFrameInfo();
175 unsigned Align = MFI.getObjectAlignment(FI);
177 return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
178 MFI.getObjectSize(FI), Align);
182 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
183 unsigned SrcReg, bool isKill, int FI,
184 const TargetRegisterClass *RC,
185 const TargetRegisterInfo *TRI) const {
187 if (I != MBB.end()) DL = I->getDebugLoc();
188 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
192 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
193 Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
194 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
195 Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
196 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
197 Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
198 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
200 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
201 Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
203 assert(Opc && "Register class not handled!");
204 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
205 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
209 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
210 unsigned DestReg, int FI,
211 const TargetRegisterClass *RC,
212 const TargetRegisterInfo *TRI) const
215 if (I != MBB.end()) DL = I->getDebugLoc();
216 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
219 if (Mips::CPURegsRegClass.hasSubClassEq(RC))
220 Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
221 else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
222 Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
223 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
224 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
225 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
227 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
228 Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
230 assert(Opc && "Register class not handled!");
231 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
235 void MipsInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
236 MachineBasicBlock::iterator I) const {
237 const TargetInstrInfo *TII = TM.getInstrInfo();
238 unsigned DstReg = I->getOperand(0).getReg();
239 unsigned SrcReg = I->getOperand(1).getReg();
240 unsigned N = I->getOperand(2).getImm();
241 const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
242 DebugLoc dl = I->getDebugLoc();
244 assert(N < 2 && "Invalid immediate");
245 unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
246 unsigned SubReg = TM.getRegisterInfo()->getSubReg(SrcReg, SubIdx);
248 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
251 void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator I) const {
253 const TargetInstrInfo *TII = TM.getInstrInfo();
254 unsigned DstReg = I->getOperand(0).getReg();
255 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
256 const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
257 DebugLoc dl = I->getDebugLoc();
258 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
262 BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpeven))
264 BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpodd))
268 bool MipsInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
269 MachineBasicBlock &MBB = *MI->getParent();
271 switch(MI->getDesc().getOpcode()) {
274 case Mips::BuildPairF64:
275 ExpandBuildPairF64(MBB, MI);
277 case Mips::ExtractElementF64:
278 ExpandExtractElementF64(MBB, MI);
287 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
288 uint64_t Offset, const MDNode *MDPtr,
290 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
291 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
295 //===----------------------------------------------------------------------===//
297 //===----------------------------------------------------------------------===//
299 static unsigned GetAnalyzableBrOpc(unsigned Opc) {
300 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
301 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
302 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
303 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
304 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
309 /// GetOppositeBranchOpc - Return the inverse of the specified
310 /// opcode, e.g. turning BEQ to BNE.
311 unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
314 default: llvm_unreachable("Illegal opcode!");
315 case Mips::BEQ: return Mips::BNE;
316 case Mips::BNE: return Mips::BEQ;
317 case Mips::BGTZ: return Mips::BLEZ;
318 case Mips::BGEZ: return Mips::BLTZ;
319 case Mips::BLTZ: return Mips::BGEZ;
320 case Mips::BLEZ: return Mips::BGTZ;
321 case Mips::BEQ64: return Mips::BNE64;
322 case Mips::BNE64: return Mips::BEQ64;
323 case Mips::BGTZ64: return Mips::BLEZ64;
324 case Mips::BGEZ64: return Mips::BLTZ64;
325 case Mips::BLTZ64: return Mips::BGEZ64;
326 case Mips::BLEZ64: return Mips::BGTZ64;
327 case Mips::BC1T: return Mips::BC1F;
328 case Mips::BC1F: return Mips::BC1T;
332 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
333 MachineBasicBlock *&BB,
334 SmallVectorImpl<MachineOperand>& Cond) {
335 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
336 int NumOp = Inst->getNumExplicitOperands();
338 // for both int and fp branches, the last explicit operand is the
340 BB = Inst->getOperand(NumOp-1).getMBB();
341 Cond.push_back(MachineOperand::CreateImm(Opc));
343 for (int i=0; i<NumOp-1; i++)
344 Cond.push_back(Inst->getOperand(i));
347 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
348 MachineBasicBlock *&TBB,
349 MachineBasicBlock *&FBB,
350 SmallVectorImpl<MachineOperand> &Cond,
351 bool AllowModify) const
353 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
355 // Skip all the debug instructions.
356 while (I != REnd && I->isDebugValue())
359 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
360 // If this block ends with no branches (it just falls through to its succ)
361 // just return false, leaving TBB/FBB null.
366 MachineInstr *LastInst = &*I;
367 unsigned LastOpc = LastInst->getOpcode();
369 // Not an analyzable branch (must be an indirect jump).
370 if (!GetAnalyzableBrOpc(LastOpc))
373 // Get the second to last instruction in the block.
374 unsigned SecondLastOpc = 0;
375 MachineInstr *SecondLastInst = NULL;
378 SecondLastInst = &*I;
379 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
381 // Not an analyzable branch (must be an indirect jump).
382 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
386 // If there is only one terminator instruction, process it.
387 if (!SecondLastOpc) {
388 // Unconditional branch
389 if (LastOpc == UncondBrOpc) {
390 TBB = LastInst->getOperand(0).getMBB();
394 // Conditional branch
395 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
399 // If we reached here, there are two branches.
400 // If there are three terminators, we don't know what sort of block this is.
401 if (++I != REnd && isUnpredicatedTerminator(&*I))
404 // If second to last instruction is an unconditional branch,
405 // analyze it and remove the last instruction.
406 if (SecondLastOpc == UncondBrOpc) {
407 // Return if the last instruction cannot be removed.
411 TBB = SecondLastInst->getOperand(0).getMBB();
412 LastInst->eraseFromParent();
416 // Conditional branch followed by an unconditional branch.
417 // The last one must be unconditional.
418 if (LastOpc != UncondBrOpc)
421 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
422 FBB = LastInst->getOperand(0).getMBB();
427 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
428 MachineBasicBlock *TBB, DebugLoc DL,
429 const SmallVectorImpl<MachineOperand>& Cond)
431 unsigned Opc = Cond[0].getImm();
432 const MCInstrDesc &MCID = get(Opc);
433 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
435 for (unsigned i = 1; i < Cond.size(); ++i)
436 MIB.addReg(Cond[i].getReg());
441 unsigned MipsInstrInfo::
442 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
443 MachineBasicBlock *FBB,
444 const SmallVectorImpl<MachineOperand> &Cond,
446 // Shouldn't be a fall through.
447 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
449 // # of condition operands:
450 // Unconditional branches: 0
451 // Floating point branches: 1 (opc)
452 // Int BranchZero: 2 (opc, reg)
453 // Int Branch: 3 (opc, reg0, reg1)
454 assert((Cond.size() <= 3) &&
455 "# of Mips branch conditions must be <= 3!");
457 // Two-way Conditional branch.
459 BuildCondBr(MBB, TBB, DL, Cond);
460 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
465 // Unconditional branch.
467 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
468 else // Conditional branch.
469 BuildCondBr(MBB, TBB, DL, Cond);
473 unsigned MipsInstrInfo::
474 RemoveBranch(MachineBasicBlock &MBB) const
476 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
477 MachineBasicBlock::reverse_iterator FirstBr;
480 // Skip all the debug instructions.
481 while (I != REnd && I->isDebugValue())
486 // Up to 2 branches are removed.
487 // Note that indirect branches are not removed.
488 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
489 if (!GetAnalyzableBrOpc(I->getOpcode()))
492 MBB.erase(I.base(), FirstBr.base());
497 /// ReverseBranchCondition - Return the inverse opcode of the
498 /// specified Branch instruction.
500 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
502 assert( (Cond.size() && Cond.size() <= 3) &&
503 "Invalid Mips branch condition!");
504 Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));