1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsAnalyzeImmediate.h"
15 #include "MipsInstrInfo.h"
16 #include "MipsTargetMachine.h"
17 #include "MipsMachineFunction.h"
18 #include "InstPrinter/MipsInstPrinter.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/ADT/STLExtras.h"
25 #define GET_INSTRINFO_CTOR
26 #include "MipsGenInstrInfo.inc"
30 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
31 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
32 TM(tm), RI(*TM.getSubtargetImpl(), *this), UncondBrOpc(UncondBr) {}
34 const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
38 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
39 return op.isImm() && op.getImm() == 0;
42 /// insertNoop - If data hazard condition is found insert the target nop
45 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
48 BuildMI(MBB, MI, DL, get(Mips::NOP));
51 MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
52 unsigned Flag) const {
53 MachineFunction &MF = *MBB.getParent();
54 MachineFrameInfo &MFI = *MF.getFrameInfo();
55 unsigned Align = MFI.getObjectAlignment(FI);
57 return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
58 MFI.getObjectSize(FI), Align);
62 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
63 uint64_t Offset, const MDNode *MDPtr,
65 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
66 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
70 //===----------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
74 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
75 MachineBasicBlock *&BB,
76 SmallVectorImpl<MachineOperand> &Cond) const {
77 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
78 int NumOp = Inst->getNumExplicitOperands();
80 // for both int and fp branches, the last explicit operand is the
82 BB = Inst->getOperand(NumOp-1).getMBB();
83 Cond.push_back(MachineOperand::CreateImm(Opc));
85 for (int i=0; i<NumOp-1; i++)
86 Cond.push_back(Inst->getOperand(i));
89 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
90 MachineBasicBlock *&TBB,
91 MachineBasicBlock *&FBB,
92 SmallVectorImpl<MachineOperand> &Cond,
93 bool AllowModify) const
95 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
97 // Skip all the debug instructions.
98 while (I != REnd && I->isDebugValue())
101 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
102 // If this block ends with no branches (it just falls through to its succ)
103 // just return false, leaving TBB/FBB null.
108 MachineInstr *LastInst = &*I;
109 unsigned LastOpc = LastInst->getOpcode();
111 // Not an analyzable branch (must be an indirect jump).
112 if (!GetAnalyzableBrOpc(LastOpc))
115 // Get the second to last instruction in the block.
116 unsigned SecondLastOpc = 0;
117 MachineInstr *SecondLastInst = NULL;
120 SecondLastInst = &*I;
121 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
123 // Not an analyzable branch (must be an indirect jump).
124 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
128 // If there is only one terminator instruction, process it.
129 if (!SecondLastOpc) {
130 // Unconditional branch
131 if (LastOpc == UncondBrOpc) {
132 TBB = LastInst->getOperand(0).getMBB();
136 // Conditional branch
137 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
141 // If we reached here, there are two branches.
142 // If there are three terminators, we don't know what sort of block this is.
143 if (++I != REnd && isUnpredicatedTerminator(&*I))
146 // If second to last instruction is an unconditional branch,
147 // analyze it and remove the last instruction.
148 if (SecondLastOpc == UncondBrOpc) {
149 // Return if the last instruction cannot be removed.
153 TBB = SecondLastInst->getOperand(0).getMBB();
154 LastInst->eraseFromParent();
158 // Conditional branch followed by an unconditional branch.
159 // The last one must be unconditional.
160 if (LastOpc != UncondBrOpc)
163 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
164 FBB = LastInst->getOperand(0).getMBB();
169 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
170 MachineBasicBlock *TBB, DebugLoc DL,
171 const SmallVectorImpl<MachineOperand>& Cond)
173 unsigned Opc = Cond[0].getImm();
174 const MCInstrDesc &MCID = get(Opc);
175 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
177 for (unsigned i = 1; i < Cond.size(); ++i)
178 MIB.addReg(Cond[i].getReg());
183 unsigned MipsInstrInfo::
184 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
185 MachineBasicBlock *FBB,
186 const SmallVectorImpl<MachineOperand> &Cond,
188 // Shouldn't be a fall through.
189 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
191 // # of condition operands:
192 // Unconditional branches: 0
193 // Floating point branches: 1 (opc)
194 // Int BranchZero: 2 (opc, reg)
195 // Int Branch: 3 (opc, reg0, reg1)
196 assert((Cond.size() <= 3) &&
197 "# of Mips branch conditions must be <= 3!");
199 // Two-way Conditional branch.
201 BuildCondBr(MBB, TBB, DL, Cond);
202 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
207 // Unconditional branch.
209 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
210 else // Conditional branch.
211 BuildCondBr(MBB, TBB, DL, Cond);
215 unsigned MipsInstrInfo::
216 RemoveBranch(MachineBasicBlock &MBB) const
218 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
219 MachineBasicBlock::reverse_iterator FirstBr;
222 // Skip all the debug instructions.
223 while (I != REnd && I->isDebugValue())
228 // Up to 2 branches are removed.
229 // Note that indirect branches are not removed.
230 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
231 if (!GetAnalyzableBrOpc(I->getOpcode()))
234 MBB.erase(I.base(), FirstBr.base());
239 /// ReverseBranchCondition - Return the inverse opcode of the
240 /// specified Branch instruction.
242 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
244 assert( (Cond.size() && Cond.size() <= 3) &&
245 "Invalid Mips branch condition!");
246 Cond[0].setImm(GetOppositeBranchOpc(Cond[0].getImm()));
250 /// Return the number of bytes of code the specified instruction may be.
251 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
252 switch (MI->getOpcode()) {
254 return MI->getDesc().getSize();
255 case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
256 const MachineFunction *MF = MI->getParent()->getParent();
257 const char *AsmStr = MI->getOperand(0).getSymbolName();
258 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
264 llvm::Mips::loadImmediate(int64_t Imm, bool IsN64, const TargetInstrInfo &TII,
265 MachineBasicBlock& MBB,
266 MachineBasicBlock::iterator II, DebugLoc DL,
267 bool LastInstrIsADDiu,
268 MipsAnalyzeImmediate::Inst *LastInst) {
269 MipsAnalyzeImmediate AnalyzeImm;
270 unsigned Size = IsN64 ? 64 : 32;
271 unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
272 unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
273 unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
275 const MipsAnalyzeImmediate::InstSeq &Seq =
276 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
277 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
279 if (LastInst && (Seq.size() == 1)) {
284 // The first instruction can be a LUi, which is different from other
285 // instructions (ADDiu, ORI and SLL) in that it does not have a register
287 if (Inst->Opc == LUi)
288 BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
289 .addImm(SignExtend64<16>(Inst->ImmOpnd));
291 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
292 .addImm(SignExtend64<16>(Inst->ImmOpnd));
294 // Build the remaining instructions in Seq. Skip the last instruction if
295 // LastInst is not 0.
296 for (++Inst; Inst != Seq.end() - !!LastInst; ++Inst)
297 BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
298 .addImm(SignExtend64<16>(Inst->ImmOpnd));
303 return Seq.size() - !!LastInst;