1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsInstrInfo.h"
15 #include "MipsTargetMachine.h"
16 #include "MipsMachineFunction.h"
17 #include "InstPrinter/MipsInstPrinter.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/ADT/STLExtras.h"
24 #define GET_INSTRINFO_CTOR
25 #include "MipsGenInstrInfo.inc"
29 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
30 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
31 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
34 const MipsRegisterInfo &MipsInstrInfo::getRegisterInfo() const {
38 static bool isZeroImm(const MachineOperand &op) {
39 return op.isImm() && op.getImm() == 0;
42 /// isLoadFromStackSlot - If the specified machine instruction is a direct
43 /// load from a stack slot, return the virtual or physical register number of
44 /// the destination along with the FrameIndex of the loaded stack slot. If
45 /// not, return 0. This predicate must return 0 if the instruction has
46 /// any side effects other than loading from the stack slot.
47 unsigned MipsInstrInfo::
48 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
50 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
51 (MI->getOpcode() == Mips::LDC1)) {
52 if ((MI->getOperand(1).isFI()) && // is a stack slot
53 (MI->getOperand(2).isImm()) && // the imm is zero
54 (isZeroImm(MI->getOperand(2)))) {
55 FrameIndex = MI->getOperand(1).getIndex();
56 return MI->getOperand(0).getReg();
63 /// isStoreToStackSlot - If the specified machine instruction is a direct
64 /// store to a stack slot, return the virtual or physical register number of
65 /// the source reg along with the FrameIndex of the loaded stack slot. If
66 /// not, return 0. This predicate must return 0 if the instruction has
67 /// any side effects other than storing to the stack slot.
68 unsigned MipsInstrInfo::
69 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
71 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
72 (MI->getOpcode() == Mips::SDC1)) {
73 if ((MI->getOperand(1).isFI()) && // is a stack slot
74 (MI->getOperand(2).isImm()) && // the imm is zero
75 (isZeroImm(MI->getOperand(2)))) {
76 FrameIndex = MI->getOperand(1).getIndex();
77 return MI->getOperand(0).getReg();
83 /// insertNoop - If data hazard condition is found insert the target nop
86 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
89 BuildMI(MBB, MI, DL, get(Mips::NOP));
93 copyPhysReg(MachineBasicBlock &MBB,
94 MachineBasicBlock::iterator I, DebugLoc DL,
95 unsigned DestReg, unsigned SrcReg,
97 unsigned Opc = 0, ZeroReg = 0;
99 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
100 if (Mips::CPURegsRegClass.contains(SrcReg))
101 Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
102 else if (Mips::CCRRegClass.contains(SrcReg))
104 else if (Mips::FGR32RegClass.contains(SrcReg))
106 else if (SrcReg == Mips::HI)
107 Opc = Mips::MFHI, SrcReg = 0;
108 else if (SrcReg == Mips::LO)
109 Opc = Mips::MFLO, SrcReg = 0;
111 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
112 if (Mips::CCRRegClass.contains(DestReg))
114 else if (Mips::FGR32RegClass.contains(DestReg))
116 else if (DestReg == Mips::HI)
117 Opc = Mips::MTHI, DestReg = 0;
118 else if (DestReg == Mips::LO)
119 Opc = Mips::MTLO, DestReg = 0;
121 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
122 Opc = Mips::FMOV_S32;
123 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
124 Opc = Mips::FMOV_D32;
125 else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
126 Opc = Mips::MOVCCRToCCR;
127 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
128 if (Mips::CPU64RegsRegClass.contains(SrcReg))
129 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
130 else if (SrcReg == Mips::HI64)
131 Opc = Mips::MFHI64, SrcReg = 0;
132 else if (SrcReg == Mips::LO64)
133 Opc = Mips::MFLO64, SrcReg = 0;
135 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
136 if (DestReg == Mips::HI64)
137 Opc = Mips::MTHI64, DestReg = 0;
138 else if (DestReg == Mips::LO64)
139 Opc = Mips::MTLO64, DestReg = 0;
142 assert(Opc && "Cannot copy registers");
144 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
147 MIB.addReg(DestReg, RegState::Define);
153 MIB.addReg(SrcReg, getKillRegState(KillSrc));
157 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
158 unsigned SrcReg, bool isKill, int FI,
159 const TargetRegisterClass *RC,
160 const TargetRegisterInfo *TRI) const {
162 if (I != MBB.end()) DL = I->getDebugLoc();
164 if (RC == Mips::CPURegsRegisterClass)
165 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
166 .addFrameIndex(FI).addImm(0);
167 else if (RC == Mips::FGR32RegisterClass)
168 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill))
169 .addFrameIndex(FI).addImm(0);
170 else if (RC == Mips::AFGR64RegisterClass) {
171 BuildMI(MBB, I, DL, get(Mips::SDC1))
172 .addReg(SrcReg, getKillRegState(isKill))
173 .addFrameIndex(FI).addImm(0);
175 llvm_unreachable("Register class not handled!");
179 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
180 unsigned DestReg, int FI,
181 const TargetRegisterClass *RC,
182 const TargetRegisterInfo *TRI) const
185 if (I != MBB.end()) DL = I->getDebugLoc();
187 if (RC == Mips::CPURegsRegisterClass)
188 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addFrameIndex(FI).addImm(0);
189 else if (RC == Mips::FGR32RegisterClass)
190 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addFrameIndex(FI).addImm(0);
191 else if (RC == Mips::AFGR64RegisterClass) {
192 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addFrameIndex(FI).addImm(0);
194 llvm_unreachable("Register class not handled!");
198 MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
199 uint64_t Offset, const MDNode *MDPtr,
201 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
202 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
206 //===----------------------------------------------------------------------===//
208 //===----------------------------------------------------------------------===//
210 static unsigned GetAnalyzableBrOpc(unsigned Opc) {
211 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
212 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
213 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? Opc : 0;
216 /// GetOppositeBranchOpc - Return the inverse of the specified
217 /// opcode, e.g. turning BEQ to BNE.
218 unsigned Mips::GetOppositeBranchOpc(unsigned Opc)
221 default: llvm_unreachable("Illegal opcode!");
222 case Mips::BEQ : return Mips::BNE;
223 case Mips::BNE : return Mips::BEQ;
224 case Mips::BGTZ : return Mips::BLEZ;
225 case Mips::BGEZ : return Mips::BLTZ;
226 case Mips::BLTZ : return Mips::BGEZ;
227 case Mips::BLEZ : return Mips::BGTZ;
228 case Mips::BC1T : return Mips::BC1F;
229 case Mips::BC1F : return Mips::BC1T;
233 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
234 MachineBasicBlock *&BB,
235 SmallVectorImpl<MachineOperand>& Cond) {
236 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
237 int NumOp = Inst->getNumExplicitOperands();
239 // for both int and fp branches, the last explicit operand is the
241 BB = Inst->getOperand(NumOp-1).getMBB();
242 Cond.push_back(MachineOperand::CreateImm(Opc));
244 for (int i=0; i<NumOp-1; i++)
245 Cond.push_back(Inst->getOperand(i));
248 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
249 MachineBasicBlock *&TBB,
250 MachineBasicBlock *&FBB,
251 SmallVectorImpl<MachineOperand> &Cond,
252 bool AllowModify) const
254 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
256 // Skip all the debug instructions.
257 while (I != REnd && I->isDebugValue())
260 if (I == REnd || !isUnpredicatedTerminator(&*I)) {
261 // If this block ends with no branches (it just falls through to its succ)
262 // just return false, leaving TBB/FBB null.
267 MachineInstr *LastInst = &*I;
268 unsigned LastOpc = LastInst->getOpcode();
270 // Not an analyzable branch (must be an indirect jump).
271 if (!GetAnalyzableBrOpc(LastOpc))
274 // Get the second to last instruction in the block.
275 unsigned SecondLastOpc = 0;
276 MachineInstr *SecondLastInst = NULL;
279 SecondLastInst = &*I;
280 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode());
282 // Not an analyzable branch (must be an indirect jump).
283 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
287 // If there is only one terminator instruction, process it.
288 if (!SecondLastOpc) {
289 // Unconditional branch
290 if (LastOpc == Mips::J) {
291 TBB = LastInst->getOperand(0).getMBB();
295 // Conditional branch
296 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
300 // If we reached here, there are two branches.
301 // If there are three terminators, we don't know what sort of block this is.
302 if (++I != REnd && isUnpredicatedTerminator(&*I))
305 // If second to last instruction is an unconditional branch,
306 // analyze it and remove the last instruction.
307 if (SecondLastOpc == Mips::J) {
308 // Return if the last instruction cannot be removed.
312 TBB = SecondLastInst->getOperand(0).getMBB();
313 LastInst->eraseFromParent();
317 // Conditional branch followed by an unconditional branch.
318 // The last one must be unconditional.
319 if (LastOpc != Mips::J)
322 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
323 FBB = LastInst->getOperand(0).getMBB();
328 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB,
329 MachineBasicBlock *TBB, DebugLoc DL,
330 const SmallVectorImpl<MachineOperand>& Cond)
332 unsigned Opc = Cond[0].getImm();
333 const MCInstrDesc &MCID = get(Opc);
334 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
336 for (unsigned i = 1; i < Cond.size(); ++i)
337 MIB.addReg(Cond[i].getReg());
342 unsigned MipsInstrInfo::
343 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
344 MachineBasicBlock *FBB,
345 const SmallVectorImpl<MachineOperand> &Cond,
347 // Shouldn't be a fall through.
348 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
350 // # of condition operands:
351 // Unconditional branches: 0
352 // Floating point branches: 1 (opc)
353 // Int BranchZero: 2 (opc, reg)
354 // Int Branch: 3 (opc, reg0, reg1)
355 assert((Cond.size() <= 3) &&
356 "# of Mips branch conditions must be <= 3!");
358 // Two-way Conditional branch.
360 BuildCondBr(MBB, TBB, DL, Cond);
361 BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB);
366 // Unconditional branch.
368 BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB);
369 else // Conditional branch.
370 BuildCondBr(MBB, TBB, DL, Cond);
374 unsigned MipsInstrInfo::
375 RemoveBranch(MachineBasicBlock &MBB) const
377 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
378 MachineBasicBlock::reverse_iterator FirstBr;
381 // Skip all the debug instructions.
382 while (I != REnd && I->isDebugValue())
387 // Up to 2 branches are removed.
388 // Note that indirect branches are not removed.
389 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
390 if (!GetAnalyzableBrOpc(I->getOpcode()))
393 MBB.erase(I.base(), FirstBr.base());
398 /// ReverseBranchCondition - Return the inverse opcode of the
399 /// specified Branch instruction.
401 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
403 assert( (Cond.size() && Cond.size() <= 3) &&
404 "Invalid Mips branch condition!");
405 Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm()));
409 /// getGlobalBaseReg - Return a virtual register initialized with the
410 /// the global base register value. Output instructions required to
411 /// initialize the register in the function entry block, if necessary.
413 unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
414 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
415 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
416 if (GlobalBaseReg != 0)
417 return GlobalBaseReg;
419 // Insert the set of GlobalBaseReg into the first MBB of the function
420 MachineBasicBlock &FirstMBB = MF->front();
421 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
422 MachineRegisterInfo &RegInfo = MF->getRegInfo();
423 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
425 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
426 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
427 GlobalBaseReg).addReg(Mips::GP);
428 RegInfo.addLiveIn(Mips::GP);
430 MipsFI->setGlobalBaseReg(GlobalBaseReg);
431 return GlobalBaseReg;