1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe MIPS instructions format
13 // CPU INSTRUCTION FORMATS
15 // opcode - operation code.
17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18 // rd - dst reg, only used on 3 regs instr.
19 // shamt - only used on shift instructions, contains the shift amount.
20 // funct - combined with opcode field give us an operation code.
22 //===----------------------------------------------------------------------===//
24 // Format specifies the encoding used by the instruction. This is part of the
25 // ad-hoc solution used to emit machine instruction encodings by our machine
27 class Format<bits<4> val> {
31 def Pseudo : Format<0>;
35 def FrmFR : Format<4>;
36 def FrmFI : Format<5>;
37 def FrmOther : Format<6>; // Instruction w/ a custom format
39 // Generic Mips Format
40 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
41 InstrItinClass itin, Format f>: Instruction
46 let Namespace = "Mips";
52 // Top 6 bits are the 'opcode' field
53 let Inst{31-26} = Opcode;
55 let OutOperandList = outs;
56 let InOperandList = ins;
58 let AsmString = asmstr;
59 let Pattern = pattern;
63 // Attributes specific to Mips instructions...
65 bits<4> FormBits = Form.Value;
67 // TSFlags layout should be kept in sync with MipsInstrInfo.h.
68 let TSFlags{3-0} = FormBits;
70 let DecoderNamespace = "Mips";
72 field bits<32> SoftFail = 0;
75 // Mips32/64 Instruction Format
76 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
77 InstrItinClass itin, Format f>:
78 MipsInst<outs, ins, asmstr, pattern, itin, f> {
79 let Predicates = [HasStdEnc];
82 // Mips Pseudo Instructions Format
83 class MipsPseudo<dag outs, dag ins, list<dag> pattern,
84 InstrItinClass itin = IIPseudo> :
85 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
86 let isCodeGenOnly = 1;
90 // Mips32/64 Pseudo Instruction Format
91 class PseudoSE<dag outs, dag ins, list<dag> pattern,
92 InstrItinClass itin = IIPseudo>:
93 MipsPseudo<outs, ins, pattern, itin> {
94 let Predicates = [HasStdEnc];
97 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
98 // These are aliases that require C++ handling to convert to the target
99 // instruction, while InstAliases can be handled directly by tblgen.
100 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
101 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
105 //===----------------------------------------------------------------------===//
106 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
107 //===----------------------------------------------------------------------===//
109 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
110 list<dag> pattern, InstrItinClass itin>:
111 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
122 let Inst{25-21} = rs;
123 let Inst{20-16} = rt;
124 let Inst{15-11} = rd;
125 let Inst{10-6} = shamt;
126 let Inst{5-0} = funct;
129 //===----------------------------------------------------------------------===//
130 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
131 //===----------------------------------------------------------------------===//
133 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
134 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
142 let Inst{25-21} = rs;
143 let Inst{20-16} = rt;
144 let Inst{15-0} = imm16;
147 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
148 list<dag> pattern, InstrItinClass itin>:
149 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
157 let Inst{25-21} = rs;
158 let Inst{20-16} = rt;
159 let Inst{15-0} = imm16;
162 //===----------------------------------------------------------------------===//
163 // Format J instruction class in Mips : <|opcode|address|>
164 //===----------------------------------------------------------------------===//
172 let Inst{31-26} = op;
173 let Inst{25-0} = target;
176 //===----------------------------------------------------------------------===//
177 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
178 //===----------------------------------------------------------------------===//
179 class MFC3OP_FM<bits<6> op, bits<5> mfmt>
187 let Inst{31-26} = op;
188 let Inst{25-21} = mfmt;
189 let Inst{20-16} = rt;
190 let Inst{15-11} = rd;
195 class ADD_FM<bits<6> op, bits<6> funct> {
202 let Inst{31-26} = op;
203 let Inst{25-21} = rs;
204 let Inst{20-16} = rt;
205 let Inst{15-11} = rd;
207 let Inst{5-0} = funct;
210 class ADDI_FM<bits<6> op> {
217 let Inst{31-26} = op;
218 let Inst{25-21} = rs;
219 let Inst{20-16} = rt;
220 let Inst{15-0} = imm16;
223 class SRA_FM<bits<6> funct, bit rotate> {
232 let Inst{21} = rotate;
233 let Inst{20-16} = rt;
234 let Inst{15-11} = rd;
235 let Inst{10-6} = shamt;
236 let Inst{5-0} = funct;
239 class SRLV_FM<bits<6> funct, bit rotate> {
247 let Inst{25-21} = rs;
248 let Inst{20-16} = rt;
249 let Inst{15-11} = rd;
251 let Inst{6} = rotate;
252 let Inst{5-0} = funct;
255 class BEQ_FM<bits<6> op> {
262 let Inst{31-26} = op;
263 let Inst{25-21} = rs;
264 let Inst{20-16} = rt;
265 let Inst{15-0} = offset;
268 class BGEZ_FM<bits<6> op, bits<5> funct> {
274 let Inst{31-26} = op;
275 let Inst{25-21} = rs;
276 let Inst{20-16} = funct;
277 let Inst{15-0} = offset;
288 let Inst{15-0} = offset;
291 class SLTI_FM<bits<6> op> {
298 let Inst{31-26} = op;
299 let Inst{25-21} = rs;
300 let Inst{20-16} = rt;
301 let Inst{15-0} = imm16;
304 class MFLO_FM<bits<6> funct> {
311 let Inst{15-11} = rd;
313 let Inst{5-0} = funct;
316 class MTLO_FM<bits<6> funct> {
322 let Inst{25-21} = rs;
324 let Inst{5-0} = funct;
327 class SEB_FM<bits<5> funct, bits<6> funct2> {
333 let Inst{31-26} = 0x1f;
335 let Inst{20-16} = rt;
336 let Inst{15-11} = rd;
337 let Inst{10-6} = funct;
338 let Inst{5-0} = funct2;
341 class CLO_FM<bits<6> funct> {
348 let Inst{31-26} = 0x1c;
349 let Inst{25-21} = rs;
350 let Inst{20-16} = rt;
351 let Inst{15-11} = rd;
353 let Inst{5-0} = funct;
363 let Inst{31-26} = 0xf;
365 let Inst{20-16} = rt;
366 let Inst{15-0} = imm16;
376 let Inst{25-21} = rs;
378 let Inst{15-11} = rd;
390 let Inst{20-16} = 0x11;
391 let Inst{15-0} = offset;
394 class BGEZAL_FM<bits<5> funct> {
401 let Inst{25-21} = rs;
402 let Inst{20-16} = funct;
403 let Inst{15-0} = offset;
412 let Inst{10-6} = stype;
416 class MULT_FM<bits<6> op, bits<6> funct> {
422 let Inst{31-26} = op;
423 let Inst{25-21} = rs;
424 let Inst{20-16} = rt;
426 let Inst{5-0} = funct;
429 class EXT_FM<bits<6> funct> {
437 let Inst{31-26} = 0x1f;
438 let Inst{25-21} = rs;
439 let Inst{20-16} = rt;
440 let Inst{15-11} = size;
441 let Inst{10-6} = pos;
442 let Inst{5-0} = funct;
451 let Inst{31-26} = 0x1f;
453 let Inst{20-16} = rt;
454 let Inst{15-11} = rd;
456 let Inst{5-0} = 0x3b;
459 //===----------------------------------------------------------------------===//
461 // FLOATING POINT INSTRUCTION FORMATS
463 // opcode - operation code.
465 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
466 // fd - dst reg, only used on 3 regs instr.
467 // fmt - double or single precision.
468 // funct - combined with opcode field give us an operation code.
470 //===----------------------------------------------------------------------===//
472 //===----------------------------------------------------------------------===//
473 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
474 //===----------------------------------------------------------------------===//
476 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
477 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
485 let Inst{25-21} = base;
486 let Inst{20-16} = ft;
487 let Inst{15-0} = imm16;
490 class ADDS_FM<bits<6> funct, bits<5> fmt> {
497 let Inst{31-26} = 0x11;
498 let Inst{25-21} = fmt;
499 let Inst{20-16} = ft;
500 let Inst{15-11} = fs;
502 let Inst{5-0} = funct;
505 class ABSS_FM<bits<6> funct, bits<5> fmt> {
511 let Inst{31-26} = 0x11;
512 let Inst{25-21} = fmt;
514 let Inst{15-11} = fs;
516 let Inst{5-0} = funct;
519 class MFC1_FM<bits<5> funct> {
525 let Inst{31-26} = 0x11;
526 let Inst{25-21} = funct;
527 let Inst{20-16} = rt;
528 let Inst{15-11} = fs;
532 class LW_FM<bits<6> op> {
538 let Inst{31-26} = op;
539 let Inst{25-21} = addr{20-16};
540 let Inst{20-16} = rt;
541 let Inst{15-0} = addr{15-0};
544 class MADDS_FM<bits<3> funct, bits<3> fmt> {
552 let Inst{31-26} = 0x13;
553 let Inst{25-21} = fr;
554 let Inst{20-16} = ft;
555 let Inst{15-11} = fs;
557 let Inst{5-3} = funct;
561 class LWXC1_FM<bits<6> funct> {
568 let Inst{31-26} = 0x13;
569 let Inst{25-21} = base;
570 let Inst{20-16} = index;
573 let Inst{5-0} = funct;
576 class SWXC1_FM<bits<6> funct> {
583 let Inst{31-26} = 0x13;
584 let Inst{25-21} = base;
585 let Inst{20-16} = index;
586 let Inst{15-11} = fs;
588 let Inst{5-0} = funct;
591 class BC1F_FM<bit nd, bit tf> {
596 let Inst{31-26} = 0x11;
597 let Inst{25-21} = 0x8;
598 let Inst{20-18} = 0; // cc
601 let Inst{15-0} = offset;
604 class CEQS_FM<bits<5> fmt> {
611 let Inst{31-26} = 0x11;
612 let Inst{25-21} = fmt;
613 let Inst{20-16} = ft;
614 let Inst{15-11} = fs;
615 let Inst{10-8} = 0; // cc
617 let Inst{3-0} = cond;
620 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
627 let Inst{31-26} = 0x11;
628 let Inst{25-21} = fmt;
629 let Inst{20-16} = rt;
630 let Inst{15-11} = fs;
632 let Inst{5-0} = funct;
635 class CMov_F_I_FM<bit tf> {
642 let Inst{25-21} = rs;
643 let Inst{20-18} = 0; // cc
646 let Inst{15-11} = rd;
651 class CMov_F_F_FM<bits<5> fmt, bit tf> {
657 let Inst{31-26} = 0x11;
658 let Inst{25-21} = fmt;
659 let Inst{20-18} = 0; // cc
662 let Inst{15-11} = fs;
664 let Inst{5-0} = 0x11;