1 //===- MipsInstrFPU.td - Mips FPU Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Floating Point Instructions
16 // ------------------------
18 // - 32 64-bit registers (default mode)
19 // - 16 even 32-bit registers (32-bit compatible mode) for
20 // single and double access.
22 // - 16 even 32-bit registers - single and double (aliased)
23 // - 32 32-bit registers (within single-only mode)
24 //===----------------------------------------------------------------------===//
26 // Floating Point Compare and Branch
27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisSameAs<0, 2>, SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<0>,
31 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
33 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp>;
35 // Operand for printing out a condition code.
36 let PrintMethod = "printFCCOperand" in
37 def condcode : Operand<i32>;
39 //===----------------------------------------------------------------------===//
40 // Feature predicates.
41 //===----------------------------------------------------------------------===//
43 def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
44 def In64BitMode : Predicate<"Subtarget.isFP64bit()">;
45 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
46 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
48 //===----------------------------------------------------------------------===//
49 // Instruction Class Templates
51 // A set of multiclasses is used to address this in one shot.
52 // SO32 - single precision only, uses all 32 32-bit fp registers
53 // require FGR32 Register Class and IsSingleFloat
54 // AS32 - 16 even fp registers are used for single precision
55 // require AFGR32 Register Class and In32BitMode
56 // S64 - 32 64 bit registers are used to hold 32-bit single precision values.
57 // require FGR64 Register Class and In64BitMode
58 // D32 - 16 even fp registers are used for double precision
59 // require AFGR64 Register Class and In32BitMode
60 // D64 - 32 64 bit registers are used to hold 64-bit double precision values.
61 // require FGR64 Register Class and In64BitMode
63 // Only SO32, AS32 and D32 are supported right now.
65 //===----------------------------------------------------------------------===//
67 multiclass FFR1_1<bits<6> funct, string asmstr>
69 def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
70 !strconcat(asmstr, ".s $fd, $fs"), []>, Requires<[IsSingleFloat]>;
72 def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd), (ins AFGR32:$fs),
73 !strconcat(asmstr, ".s $fd, $fs"), []>, Requires<[In32BitMode]>;
75 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
76 !strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
79 multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
81 def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
82 !strconcat(asmstr, ".s $fd, $fs"),
83 [(set FGR32:$fd, (FOp FGR32:$fs))]>, Requires<[IsSingleFloat]>;
85 def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd), (ins AFGR32:$fs),
86 !strconcat(asmstr, ".s $fd, $fs"),
87 [(set AFGR32:$fd, (FOp AFGR32:$fs))]>, Requires<[In32BitMode]>;
89 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
90 !strconcat(asmstr, ".d $fd, $fs"),
91 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
94 class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
95 RegisterClass RcDst, string asmstr>:
96 FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
97 !strconcat(asmstr, " $fd, $fs"), []>;
100 multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
101 def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
102 (ins FGR32:$fs, FGR32:$ft),
103 !strconcat(asmstr, ".s $fd, $fs, $ft"),
104 [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>,
105 Requires<[IsSingleFloat]>;
107 def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd),
108 (ins AFGR32:$fs, AFGR32:$ft),
109 !strconcat(asmstr, ".s $fd, $fs, $ft"),
110 [(set AFGR32:$fd, (FOp AFGR32:$fs, AFGR32:$ft))]>,
111 Requires<[In32BitMode]>;
113 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
114 (ins AFGR64:$fs, AFGR64:$ft),
115 !strconcat(asmstr, ".d $fd, $fs, $ft"),
116 [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
117 Requires<[In32BitMode]>;
120 //===----------------------------------------------------------------------===//
121 // Floating Point Instructions
122 //===----------------------------------------------------------------------===//
125 defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
126 defm CEIL_W : FFR1_1<0b001110, "ceil.w">;
127 defm ROUND_W : FFR1_1<0b001100, "round.w">;
128 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
129 defm CVTW : FFR1_1<0b100100, "cvt.w">;
130 defm FMOV : FFR1_1<0b000110, "mov">;
132 defm FABS : FFR1_2<0b000101, "abs", fabs>;
133 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
134 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
136 let Predicates = [IsNotSingleFloat] in {
137 /// Ceil to long signed integer
138 def CEIL_LS : FFR1_3<0b001010, 0x0, AFGR32, AFGR32, "ceil.l">;
139 def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
141 /// Round to long signed integer
142 def ROUND_LS : FFR1_3<0b001000, 0x0, AFGR32, AFGR32, "round.l">;
143 def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
145 /// Floor to long signed integer
146 def FLOOR_LS : FFR1_3<0b001011, 0x0, AFGR32, AFGR32, "floor.l">;
147 def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
149 /// Trunc to long signed integer
150 def TRUNC_LS : FFR1_3<0b001001, 0x0, AFGR32, AFGR32, "trunc.l">;
151 def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
153 /// Convert to long signed integer
154 def CVTL_S : FFR1_3<0b100101, 0x0, AFGR32, AFGR32, "cvt.l">;
155 def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
157 /// Convert to Double Precison
158 def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
159 def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
160 def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
162 /// Convert to Single Precison
163 def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
164 def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
167 /// Convert to Single Precison
168 def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">,
169 Requires<[IsSingleFloat]>;
172 // The odd-numbered registers are only referenced when doing loads,
173 // stores, and moves between floating-point and integer registers.
174 // When defining instructions, we reference all 32-bit registers,
175 // regardless of register aliasing.
177 /// Move Control Registers From/To CPU Registers
178 ///def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins FGR32:$fs),
179 /// "cfc1 $rt, $fs", []>;
181 ///def CTC1 : FFR<0x11, 0x0, 0x6, (outs CPURegs:$rt), (ins FGR32:$fs),
182 /// "ctc1 $rt, $fs", []>;
184 ///def CFC1A : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins AFGR32:$fs),
185 /// "cfc1 $rt, $fs", []>;
187 ///def CTC1A : FFR<0x11, 0x0, 0x6, (outs CPURegs:$rt), (ins AFGR32:$fs),
188 /// "ctc1 $rt, $fs", []>;
190 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
191 "mfc1 $rt, $fs", []>;
193 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
194 "mtc1 $fs, $rt", []>;
196 def MFC1A : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins AFGR32:$fs),
197 "mfc1 $rt, $fs", []>;
199 def MTC1A : FFR<0x11, 0x00, 0x04, (outs AFGR32:$fs), (ins CPURegs:$rt),
200 "mtc1 $fs, $rt", []>;
203 /// Floating Point Memory Instructions
204 let Predicates = [IsNotSingleFloat] in {
205 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
206 "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
208 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
209 "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
212 // LWC1 and SWC1 can always be emited with odd registers.
213 def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
214 [(set FGR32:$ft, (load addr:$addr))]>;
215 def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
216 [(store FGR32:$ft, addr:$addr)]>;
218 def LWC1A : FFI<0b110001, (outs AFGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
219 [(set AFGR32:$ft, (load addr:$addr))]>;
220 def SWC1A : FFI<0b111001, (outs), (ins AFGR32:$ft, mem:$addr),
221 "swc1 $ft, $addr", [(store AFGR32:$ft, addr:$addr)]>;
223 /// Floating-point Aritmetic
224 defm FADD : FFR1_4<0x10, "add", fadd>;
225 defm FDIV : FFR1_4<0x03, "div", fdiv>;
226 defm FMUL : FFR1_4<0x02, "mul", fmul>;
227 defm FSUB : FFR1_4<0x01, "sub", fsub>;
229 //===----------------------------------------------------------------------===//
230 // Floating Point Branch Codes
231 //===----------------------------------------------------------------------===//
232 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
233 // They must be kept in synch.
234 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
235 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
236 def MIPS_BRANCH_FL : PatLeaf<(i32 2)>;
237 def MIPS_BRANCH_TL : PatLeaf<(i32 3)>;
239 /// Floating Point Branch of False/True (Likely)
240 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in {
241 class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (ops),
242 (ins brtarget:$dst), !strconcat(asmstr, " $dst"),
243 [(MipsFPBrcond op, bb:$dst, FCR31)]>;
245 def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
246 def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
247 def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
248 def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
250 //===----------------------------------------------------------------------===//
251 // Floating Point Flag Conditions
252 //===----------------------------------------------------------------------===//
253 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
254 // They must be kept in synch.
255 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
256 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
257 def MIPS_FCOND_EQ : PatLeaf<(i32 2)>;
258 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
259 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
260 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
261 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
262 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
263 def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
264 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
265 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
266 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
267 def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
268 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
269 def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
270 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
272 /// Floating Point Compare
273 let hasDelaySlot = 1, Defs=[FCR31] in {
275 //multiclass FCC1_1<RegisterClass RC>
277 def FCMP_SO32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
278 "c.$cc.s $fs $ft", [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc),
279 (implicit FCR31)]>, Requires<[IsSingleFloat]>;
281 def FCMP_AS32 : FCC<0x0, (outs), (ins AFGR32:$fs, AFGR32:$ft, condcode:$cc),
282 "c.$cc.s $fs $ft", [(MipsFPCmp AFGR32:$fs, AFGR32:$ft, imm:$cc),
283 (implicit FCR31)]>, Requires<[In32BitMode]>;
285 def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
286 "c.$cc.d $fs $ft", [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc),
287 (implicit FCR31)]>, Requires<[In32BitMode]>;
290 //===----------------------------------------------------------------------===//
291 // Floating Point Patterns
292 //===----------------------------------------------------------------------===//
293 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
294 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
295 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_SO32 FGR32:$src))>;
296 def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1 (TRUNC_W_AS32 AFGR32:$src))>;