1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/Target/TargetLowering.h"
30 // Start the numbering from where ISD NodeType finishes.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Jump and link (call)
39 // Get the Higher 16 bits from a 32-bit immediate
40 // No relation with Mips Hi register
43 // Get the Lower 16 bits from a 32-bit immediate
44 // No relation with Mips Lo register
47 // Handle gp_rel (small data/bss sections) relocation.
53 // Floating Point Branch Conditional
56 // Floating Point Compare
59 // Floating Point Conditional Moves
63 // FP-to-int truncation node.
71 // Node used to extract integer from accumulator.
75 // Node used to insert integers to accumulator.
106 // EXTR.W instrinsic nodes.
116 // DPA.W intrinsic nodes.
152 // DSP setcc and select_cc nodes.
156 // Vector comparisons.
157 // These take a vector and return a boolean.
163 // These take a vector and return a vector bitmask.
170 // Element-wise vector max/min.
176 // Vector Shuffle with mask as an operand
177 VSHF, // Generic shuffle
178 SHF, // 4-element set shuffle.
179 ILVEV, // Interleave even elements
180 ILVOD, // Interleave odd elements
181 ILVL, // Interleave left elements
182 ILVR, // Interleave right elements
183 PCKEV, // Pack even elements
184 PCKOD, // Pack odd elements
187 INSVE, // Copy element from one vector to another
189 // Combined (XOR (OR $a, $b), -1)
192 // Extended vector element extraction
196 // Load/Store Left/Right nodes.
197 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
208 //===--------------------------------------------------------------------===//
209 // TargetLowering Implementation
210 //===--------------------------------------------------------------------===//
211 class MipsFunctionInfo;
215 class MipsTargetLowering : public TargetLowering {
218 explicit MipsTargetLowering(const MipsTargetMachine &TM,
219 const MipsSubtarget &STI);
221 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
222 const MipsSubtarget &STI);
224 /// createFastISel - This method returns a target specific FastISel object,
225 /// or null if the target does not support "fast" ISel.
226 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
227 const TargetLibraryInfo *libInfo) const override;
229 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
231 void LowerOperationWrapper(SDNode *N,
232 SmallVectorImpl<SDValue> &Results,
233 SelectionDAG &DAG) const override;
235 /// LowerOperation - Provide custom lowering hooks for some operations.
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
238 /// ReplaceNodeResults - Replace the results of node with an illegal result
239 /// type with new values built out of custom code.
241 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
242 SelectionDAG &DAG) const override;
244 /// getTargetNodeName - This method returns the name of a target specific
246 const char *getTargetNodeName(unsigned Opcode) const override;
248 /// getSetCCResultType - get the ISD::SETCC result ValueType
249 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
251 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
254 EmitInstrWithCustomInserter(MachineInstr *MI,
255 MachineBasicBlock *MBB) const override;
258 bool operator()(const char *S1, const char *S2) const {
259 return strcmp(S1, S2) < 0;
263 void HandleByVal(CCState *, unsigned &, unsigned) const override;
266 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
268 // This method creates the following nodes, which are necessary for
269 // computing a local symbol's address:
271 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
272 template <class NodeTy>
273 SDValue getAddrLocal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
274 bool IsN32OrN64) const {
276 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
277 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
278 getTargetNode(N, Ty, DAG, GOTFlag));
279 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
280 MachinePointerInfo::getGOT(), false, false,
282 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
283 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
284 getTargetNode(N, Ty, DAG, LoFlag));
285 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
288 // This method creates the following nodes, which are necessary for
289 // computing a global symbol's address:
291 // (load (wrapper $gp, %got(sym)))
292 template<class NodeTy>
293 SDValue getAddrGlobal(NodeTy *N, EVT Ty, SelectionDAG &DAG,
294 unsigned Flag, SDValue Chain,
295 const MachinePointerInfo &PtrInfo) const {
297 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
298 getTargetNode(N, Ty, DAG, Flag));
299 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0);
302 // This method creates the following nodes, which are necessary for
303 // computing a global symbol's address in large-GOT mode:
305 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
306 template<class NodeTy>
307 SDValue getAddrGlobalLargeGOT(NodeTy *N, EVT Ty, SelectionDAG &DAG,
308 unsigned HiFlag, unsigned LoFlag,
310 const MachinePointerInfo &PtrInfo) const {
312 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty,
313 getTargetNode(N, Ty, DAG, HiFlag));
314 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
315 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
316 getTargetNode(N, Ty, DAG, LoFlag));
317 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false,
321 // This method creates the following nodes, which are necessary for
322 // computing a symbol's address in non-PIC mode:
324 // (add %hi(sym), %lo(sym))
325 template<class NodeTy>
326 SDValue getAddrNonPIC(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
328 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
329 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
330 return DAG.getNode(ISD::ADD, DL, Ty,
331 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
332 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
335 // This method creates the following nodes, which are necessary for
336 // computing a symbol's address using gp-relative addressing:
338 // (add $gp, %gp_rel(sym))
339 template<class NodeTy>
340 SDValue getAddrGPRel(NodeTy *N, EVT Ty, SelectionDAG &DAG) const {
342 assert(Ty == MVT::i32);
343 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
344 return DAG.getNode(ISD::ADD, DL, Ty,
345 DAG.getRegister(Mips::GP, Ty),
346 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
350 /// This function fills Ops, which is the list of operands that will later
351 /// be used when a function call node is created. It also generates
352 /// copyToReg nodes to set up argument registers.
354 getOpndList(SmallVectorImpl<SDValue> &Ops,
355 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
356 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
357 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
358 SDValue Chain) const;
360 /// MipsCC - This class provides methods used to analyze formal and call
361 /// arguments and inquire about calling convention information.
364 MipsCC(CallingConv::ID CallConv, const MipsSubtarget &Subtarget,
368 CallingConv::ID CallConv;
369 const MipsSubtarget &Subtarget;
372 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
373 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
376 const MipsSubtarget &Subtarget;
379 // Create a TargetGlobalAddress node.
380 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
381 unsigned Flag) const;
383 // Create a TargetExternalSymbol node.
384 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
385 unsigned Flag) const;
387 // Create a TargetBlockAddress node.
388 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
389 unsigned Flag) const;
391 // Create a TargetJumpTable node.
392 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
393 unsigned Flag) const;
395 // Create a TargetConstantPool node.
396 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
397 unsigned Flag) const;
399 // Lower Operand helpers
400 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
401 CallingConv::ID CallConv, bool isVarArg,
402 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
403 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
404 TargetLowering::CallLoweringInfo &CLI) const;
406 // Lower Operand specifics
407 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
408 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
409 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
410 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
411 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
412 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
413 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
414 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
415 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
416 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
417 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
418 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
419 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
420 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
421 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
422 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
423 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
424 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
425 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
426 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
428 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
429 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
431 /// isEligibleForTailCallOptimization - Check whether the call is eligible
432 /// for tail call optimization.
434 isEligibleForTailCallOptimization(const CCState &CCInfo,
435 unsigned NextStackOffset,
436 const MipsFunctionInfo &FI) const = 0;
438 /// copyByValArg - Copy argument registers which were used to pass a byval
439 /// argument to the stack. Create a stack frame object for the byval
441 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
442 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
443 SmallVectorImpl<SDValue> &InVals,
444 const Argument *FuncArg, const MipsCC &CC,
445 unsigned FirstReg, unsigned LastReg,
446 const CCValAssign &VA, MipsCCState &State) const;
448 /// passByValArg - Pass a byval argument in registers or on stack.
449 void passByValArg(SDValue Chain, SDLoc DL,
450 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
451 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
452 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
453 const MipsCC &CC, unsigned FirstReg, unsigned LastReg,
454 const ISD::ArgFlagsTy &Flags, bool isLittle,
455 const CCValAssign &VA) const;
457 /// writeVarArgRegs - Write variable function arguments passed in registers
458 /// to the stack. Also create a stack frame object for the first variable
460 void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
461 SDValue Chain, SDLoc DL, SelectionDAG &DAG,
462 CCState &State) const;
465 LowerFormalArguments(SDValue Chain,
466 CallingConv::ID CallConv, bool isVarArg,
467 const SmallVectorImpl<ISD::InputArg> &Ins,
468 SDLoc dl, SelectionDAG &DAG,
469 SmallVectorImpl<SDValue> &InVals) const override;
471 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
472 SDValue Arg, SDLoc DL, bool IsTailCall,
473 SelectionDAG &DAG) const;
475 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
476 SmallVectorImpl<SDValue> &InVals) const override;
478 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
480 const SmallVectorImpl<ISD::OutputArg> &Outs,
481 LLVMContext &Context) const override;
483 SDValue LowerReturn(SDValue Chain,
484 CallingConv::ID CallConv, bool isVarArg,
485 const SmallVectorImpl<ISD::OutputArg> &Outs,
486 const SmallVectorImpl<SDValue> &OutVals,
487 SDLoc dl, SelectionDAG &DAG) const override;
489 // Inline asm support
491 getConstraintType(const std::string &Constraint) const override;
493 /// Examine constraint string and operand type and determine a weight value.
494 /// The operand object must already have been set up with the operand type.
495 ConstraintWeight getSingleConstraintMatchWeight(
496 AsmOperandInfo &info, const char *constraint) const override;
498 /// This function parses registers that appear in inline-asm constraints.
499 /// It returns pair (0, 0) on failure.
500 std::pair<unsigned, const TargetRegisterClass *>
501 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
503 std::pair<unsigned, const TargetRegisterClass*>
504 getRegForInlineAsmConstraint(const std::string &Constraint,
505 MVT VT) const override;
507 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
508 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
509 /// true it means one of the asm constraint of the inline asm instruction
510 /// being processed is 'm'.
511 void LowerAsmOperandForConstraint(SDValue Op,
512 std::string &Constraint,
513 std::vector<SDValue> &Ops,
514 SelectionDAG &DAG) const override;
516 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
518 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
520 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
522 bool IsMemset, bool ZeroMemset,
524 MachineFunction &MF) const override;
526 /// isFPImmLegal - Returns true if the target can instruction select the
527 /// specified FP immediate natively. If false, the legalizer will
528 /// materialize the FP immediate as a load from a constant pool.
529 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
531 unsigned getJumpTableEncoding() const override;
533 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
534 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,
535 MachineBasicBlock *BB,
536 unsigned Size, unsigned DstReg,
537 unsigned SrcRec) const;
539 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
540 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
541 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
542 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
543 bool Nand = false) const;
544 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
545 MachineBasicBlock *BB, unsigned Size) const;
546 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
547 MachineBasicBlock *BB, unsigned Size) const;
548 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
551 /// Create MipsTargetLowering objects.
552 const MipsTargetLowering *
553 createMips16TargetLowering(const MipsTargetMachine &TM,
554 const MipsSubtarget &STI);
555 const MipsTargetLowering *
556 createMipsSETargetLowering(const MipsTargetMachine &TM,
557 const MipsSubtarget &STI);
560 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
561 const TargetLibraryInfo *libInfo);