1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef MipsISELLOWERING_H
16 #define MipsISELLOWERING_H
19 #include "MipsSubtarget.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetLowering.h"
27 // Start the numbering from where ISD NodeType finishes.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 // Jump and link (call)
36 // Get the Higher 16 bits from a 32-bit immediate
37 // No relation with Mips Hi register
40 // Get the Lower 16 bits from a 32-bit immediate
41 // No relation with Mips Lo register
44 // Handle gp_rel (small data/bss sections) relocation.
50 // Floating Point Branch Conditional
53 // Floating Point Compare
56 // Floating Point Conditional Moves
60 // Floating Point Rounding
88 // EXTR.W instrinsic nodes.
98 // DPA.W intrinsic nodes.
129 // Load/Store Left/Right nodes.
130 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
141 //===--------------------------------------------------------------------===//
142 // TargetLowering Implementation
143 //===--------------------------------------------------------------------===//
145 class MipsTargetLowering : public TargetLowering {
147 explicit MipsTargetLowering(MipsTargetMachine &TM);
149 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
151 virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
153 virtual void LowerOperationWrapper(SDNode *N,
154 SmallVectorImpl<SDValue> &Results,
155 SelectionDAG &DAG) const;
157 /// LowerOperation - Provide custom lowering hooks for some operations.
158 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
160 /// ReplaceNodeResults - Replace the results of node with an illegal result
161 /// type with new values built out of custom code.
163 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
164 SelectionDAG &DAG) const;
166 /// getTargetNodeName - This method returns the name of a target specific
168 virtual const char *getTargetNodeName(unsigned Opcode) const;
170 /// getSetCCResultType - get the ISD::SETCC result ValueType
171 EVT getSetCCResultType(EVT VT) const;
173 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
176 /// ByValArgInfo - Byval argument information.
177 struct ByValArgInfo {
178 unsigned FirstIdx; // Index of the first register used.
179 unsigned NumRegs; // Number of registers used for this argument.
180 unsigned Address; // Offset of the stack area used to pass this argument.
182 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
185 /// MipsCC - This class provides methods used to analyze formal and call
186 /// arguments and inquire about calling convention information.
189 MipsCC(CallingConv::ID CallConv, bool IsVarArg, bool IsO32,
192 void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
193 void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins);
194 void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
195 CCValAssign::LocInfo LocInfo,
196 ISD::ArgFlagsTy ArgFlags);
198 const CCState &getCCInfo() const { return CCInfo; }
200 /// hasByValArg - Returns true if function has byval arguments.
201 bool hasByValArg() const { return !ByValArgs.empty(); }
203 /// useRegsForByval - Returns true if the calling convention allows the
204 /// use of registers to pass byval arguments.
205 bool useRegsForByval() const { return UseRegsForByval; }
207 /// regSize - Size (in number of bits) of integer registers.
208 unsigned regSize() const { return RegSize; }
210 /// numIntArgRegs - Number of integer registers available for calls.
211 unsigned numIntArgRegs() const { return NumIntArgRegs; }
213 /// reservedArgArea - The size of the area the caller reserves for
214 /// register arguments. This is 16-byte if ABI is O32.
215 unsigned reservedArgArea() const { return ReservedArgArea; }
217 /// intArgRegs - Pointer to array of integer registers.
218 const uint16_t *intArgRegs() const { return IntArgRegs; }
220 typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
221 byval_iterator byval_begin() const { return ByValArgs.begin(); }
222 byval_iterator byval_end() const { return ByValArgs.end(); }
225 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
229 bool UseRegsForByval;
231 unsigned NumIntArgRegs;
232 unsigned ReservedArgArea;
233 const uint16_t *IntArgRegs, *ShadowRegs;
234 SmallVector<ByValArgInfo, 2> ByValArgs;
235 llvm::CCAssignFn *FixedFn, *VarFn;
239 const MipsSubtarget *Subtarget;
241 bool HasMips64, IsN64, IsO32;
243 // Lower Operand helpers
244 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
245 CallingConv::ID CallConv, bool isVarArg,
246 const SmallVectorImpl<ISD::InputArg> &Ins,
247 DebugLoc dl, SelectionDAG &DAG,
248 SmallVectorImpl<SDValue> &InVals) const;
250 // Lower Operand specifics
251 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
252 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
253 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
254 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
255 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
256 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
257 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
258 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
259 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
260 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
261 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
262 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
263 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
264 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
265 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
266 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
267 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
268 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
270 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
271 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
272 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
273 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
275 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
276 /// for tail call optimization.
277 bool IsEligibleForTailCallOptimization(CallingConv::ID CalleeCC,
278 unsigned NextStackOffset) const;
280 /// copyByValArg - Copy argument registers which were used to pass a byval
281 /// argument to the stack. Create a stack frame object for the byval
283 void copyByValRegs(SDValue Chain, DebugLoc DL,
284 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
285 const ISD::ArgFlagsTy &Flags,
286 SmallVectorImpl<SDValue> &InVals,
287 const Argument *FuncArg,
288 const MipsCC &CC, const ByValArgInfo &ByVal) const;
291 LowerFormalArguments(SDValue Chain,
292 CallingConv::ID CallConv, bool isVarArg,
293 const SmallVectorImpl<ISD::InputArg> &Ins,
294 DebugLoc dl, SelectionDAG &DAG,
295 SmallVectorImpl<SDValue> &InVals) const;
298 LowerCall(TargetLowering::CallLoweringInfo &CLI,
299 SmallVectorImpl<SDValue> &InVals) const;
302 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
304 const SmallVectorImpl<ISD::OutputArg> &Outs,
305 LLVMContext &Context) const;
308 LowerReturn(SDValue Chain,
309 CallingConv::ID CallConv, bool isVarArg,
310 const SmallVectorImpl<ISD::OutputArg> &Outs,
311 const SmallVectorImpl<SDValue> &OutVals,
312 DebugLoc dl, SelectionDAG &DAG) const;
314 virtual MachineBasicBlock *
315 EmitInstrWithCustomInserter(MachineInstr *MI,
316 MachineBasicBlock *MBB) const;
318 // Inline asm support
319 ConstraintType getConstraintType(const std::string &Constraint) const;
321 /// Examine constraint string and operand type and determine a weight value.
322 /// The operand object must already have been set up with the operand type.
323 ConstraintWeight getSingleConstraintMatchWeight(
324 AsmOperandInfo &info, const char *constraint) const;
326 std::pair<unsigned, const TargetRegisterClass*>
327 getRegForInlineAsmConstraint(const std::string &Constraint,
330 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
331 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
332 /// true it means one of the asm constraint of the inline asm instruction
333 /// being processed is 'm'.
334 virtual void LowerAsmOperandForConstraint(SDValue Op,
335 std::string &Constraint,
336 std::vector<SDValue> &Ops,
337 SelectionDAG &DAG) const;
339 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
341 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
342 unsigned SrcAlign, bool IsZeroVal,
344 MachineFunction &MF) const;
346 /// isFPImmLegal - Returns true if the target can instruction select the
347 /// specified FP immediate natively. If false, the legalizer will
348 /// materialize the FP immediate as a load from a constant pool.
349 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
351 virtual unsigned getJumpTableEncoding() const;
353 MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
354 MachineBasicBlock *BB) const;
355 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
356 unsigned Size, unsigned BinOpcode, bool Nand = false) const;
357 MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
358 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
359 bool Nand = false) const;
360 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
361 MachineBasicBlock *BB, unsigned Size) const;
362 MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
363 MachineBasicBlock *BB, unsigned Size) const;
367 #endif // MipsISELLOWERING_H