1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::SelectCC : return "MipsISD::SelectCC";
45 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
46 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
47 case MipsISD::FPCmp : return "MipsISD::FPCmp";
48 case MipsISD::FPRound : return "MipsISD::FPRound";
49 default : return NULL;
54 MipsTargetLowering(MipsTargetMachine &TM)
55 : TargetLowering(TM, new MipsTargetObjectFile()) {
56 Subtarget = &TM.getSubtarget<MipsSubtarget>();
58 // Mips does not have i1 type, so use i32 for
59 // setcc operations results (slt, sgt, ...).
60 setBooleanContents(ZeroOrOneBooleanContent);
62 // Set up the register classes
63 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
64 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
66 // When dealing with single precision only, use libcalls
67 if (!Subtarget->isSingleFloat())
68 if (!Subtarget->isFP64bit())
69 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
71 // Load extented operations for i1 types must be promoted
72 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
74 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
76 // MIPS doesn't have extending float->double load/store
77 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
78 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
80 // Used by legalize types to correctly generate the setcc result.
81 // Without this, every float setcc comes with a AND/OR with the result,
82 // we don't want this, since the fpcmp result goes to a flag register,
83 // which is used implicitly by brcond and select operations.
84 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
86 // Mips Custom Operations
87 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
88 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
89 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
90 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
91 setOperationAction(ISD::SELECT, MVT::f32, Custom);
92 setOperationAction(ISD::SELECT, MVT::f64, Custom);
93 setOperationAction(ISD::SELECT, MVT::i32, Custom);
94 setOperationAction(ISD::SETCC, MVT::f32, Custom);
95 setOperationAction(ISD::SETCC, MVT::f64, Custom);
96 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
97 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
98 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
99 setOperationAction(ISD::VASTART, MVT::Other, Custom);
102 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
103 // with operands comming from setcc fp comparions. This is necessary since
104 // the result from these setcc are in a flag registers (FCR31).
105 setOperationAction(ISD::AND, MVT::i32, Custom);
106 setOperationAction(ISD::OR, MVT::i32, Custom);
108 // Operations not directly supported by Mips.
109 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
110 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
111 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
113 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
115 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
116 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
117 setOperationAction(ISD::ROTL, MVT::i32, Expand);
119 if (!Subtarget->isMips32r2())
120 setOperationAction(ISD::ROTR, MVT::i32, Expand);
122 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
123 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
124 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
125 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
126 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
127 setOperationAction(ISD::FSIN, MVT::f32, Expand);
128 setOperationAction(ISD::FCOS, MVT::f32, Expand);
129 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
130 setOperationAction(ISD::FPOW, MVT::f32, Expand);
131 setOperationAction(ISD::FLOG, MVT::f32, Expand);
132 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
133 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
134 setOperationAction(ISD::FEXP, MVT::f32, Expand);
136 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
138 // Use the default for now
139 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
140 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
141 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
143 if (Subtarget->isSingleFloat())
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
146 if (!Subtarget->hasSEInReg()) {
147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
151 if (!Subtarget->hasBitCount())
152 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
154 if (!Subtarget->hasSwap())
155 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
157 setStackPointerRegisterToSaveRestore(Mips::SP);
158 computeRegisterProperties();
161 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
165 /// getFunctionAlignment - Return the Log2 alignment of this function.
166 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
170 SDValue MipsTargetLowering::
171 LowerOperation(SDValue Op, SelectionDAG &DAG) const
173 switch (Op.getOpcode())
175 case ISD::AND: return LowerANDOR(Op, DAG);
176 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
177 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
178 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
179 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
180 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
181 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
182 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
183 case ISD::OR: return LowerANDOR(Op, DAG);
184 case ISD::SELECT: return LowerSELECT(Op, DAG);
185 case ISD::SETCC: return LowerSETCC(Op, DAG);
186 case ISD::VASTART: return LowerVASTART(Op, DAG);
191 //===----------------------------------------------------------------------===//
192 // Lower helper functions
193 //===----------------------------------------------------------------------===//
195 // AddLiveIn - This helper function adds the specified physical register to the
196 // MachineFunction as a live in value. It also creates a corresponding
197 // virtual register for it.
199 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
201 assert(RC->contains(PReg) && "Not the correct regclass!");
202 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
203 MF.getRegInfo().addLiveIn(PReg, VReg);
207 // Get fp branch code (not opcode) from condition code.
208 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
209 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
210 return Mips::BRANCH_T;
212 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
213 return Mips::BRANCH_F;
215 return Mips::BRANCH_INVALID;
218 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
221 llvm_unreachable("Unknown branch code");
222 case Mips::BRANCH_T : return Mips::BC1T;
223 case Mips::BRANCH_F : return Mips::BC1F;
224 case Mips::BRANCH_TL : return Mips::BC1TL;
225 case Mips::BRANCH_FL : return Mips::BC1FL;
229 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
231 default: llvm_unreachable("Unknown fp condition code!");
233 case ISD::SETOEQ: return Mips::FCOND_EQ;
234 case ISD::SETUNE: return Mips::FCOND_OGL;
236 case ISD::SETOLT: return Mips::FCOND_OLT;
238 case ISD::SETOGT: return Mips::FCOND_OGT;
240 case ISD::SETOLE: return Mips::FCOND_OLE;
242 case ISD::SETOGE: return Mips::FCOND_OGE;
243 case ISD::SETULT: return Mips::FCOND_ULT;
244 case ISD::SETULE: return Mips::FCOND_ULE;
245 case ISD::SETUGT: return Mips::FCOND_UGT;
246 case ISD::SETUGE: return Mips::FCOND_UGE;
247 case ISD::SETUO: return Mips::FCOND_UN;
248 case ISD::SETO: return Mips::FCOND_OR;
250 case ISD::SETONE: return Mips::FCOND_NEQ;
251 case ISD::SETUEQ: return Mips::FCOND_UEQ;
256 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
257 MachineBasicBlock *BB) const {
258 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
259 bool isFPCmp = false;
260 DebugLoc dl = MI->getDebugLoc();
262 switch (MI->getOpcode()) {
263 default: assert(false && "Unexpected instr type to insert");
264 case Mips::Select_FCC:
265 case Mips::Select_FCC_S32:
266 case Mips::Select_FCC_D32:
267 isFPCmp = true; // FALL THROUGH
268 case Mips::Select_CC:
269 case Mips::Select_CC_S32:
270 case Mips::Select_CC_D32: {
271 // To "insert" a SELECT_CC instruction, we actually have to insert the
272 // diamond control-flow pattern. The incoming instruction knows the
273 // destination vreg to set, the condition code register to branch on, the
274 // true/false values to select between, and a branch opcode to use.
275 const BasicBlock *LLVM_BB = BB->getBasicBlock();
276 MachineFunction::iterator It = BB;
283 // bNE r1, r0, copy1MBB
284 // fallthrough --> copy0MBB
285 MachineBasicBlock *thisMBB = BB;
286 MachineFunction *F = BB->getParent();
287 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
288 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
289 F->insert(It, copy0MBB);
290 F->insert(It, sinkMBB);
292 // Transfer the remainder of BB and its successor edges to sinkMBB.
293 sinkMBB->splice(sinkMBB->begin(), BB,
294 llvm::next(MachineBasicBlock::iterator(MI)),
296 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
298 // Next, add the true and fallthrough blocks as its successors.
299 BB->addSuccessor(copy0MBB);
300 BB->addSuccessor(sinkMBB);
302 // Emit the right instruction according to the type of the operands compared
304 // Find the condiction code present in the setcc operation.
305 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
306 // Get the branch opcode from the branch code.
307 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
308 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
310 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
311 .addReg(Mips::ZERO).addMBB(sinkMBB);
315 // # fallthrough to sinkMBB
318 // Update machine-CFG edges
319 BB->addSuccessor(sinkMBB);
322 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
325 BuildMI(*BB, BB->begin(), dl,
326 TII->get(Mips::PHI), MI->getOperand(0).getReg())
327 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
328 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
330 MI->eraseFromParent(); // The pseudo instruction is gone now.
336 //===----------------------------------------------------------------------===//
337 // Misc Lower Operation implementation
338 //===----------------------------------------------------------------------===//
340 SDValue MipsTargetLowering::
341 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
343 if (!Subtarget->isMips1())
346 MachineFunction &MF = DAG.getMachineFunction();
347 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
349 SDValue Chain = DAG.getEntryNode();
350 DebugLoc dl = Op.getDebugLoc();
351 SDValue Src = Op.getOperand(0);
353 // Set the condition register
354 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
355 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
356 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
358 SDValue Cst = DAG.getConstant(3, MVT::i32);
359 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
360 Cst = DAG.getConstant(2, MVT::i32);
361 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
363 SDValue InFlag(0, 0);
364 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
366 // Emit the round instruction and bit convert to integer
367 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
368 Src, CondReg.getValue(1));
369 SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
373 SDValue MipsTargetLowering::
374 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
376 SDValue Chain = Op.getOperand(0);
377 SDValue Size = Op.getOperand(1);
378 DebugLoc dl = Op.getDebugLoc();
380 // Get a reference from Mips stack pointer
381 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
383 // Subtract the dynamic size from the actual stack size to
384 // obtain the new stack size.
385 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
387 // The Sub result contains the new stack start address, so it
388 // must be placed in the stack pointer register.
389 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
391 // This node always has two return values: a new stack pointer
393 SDValue Ops[2] = { Sub, Chain };
394 return DAG.getMergeValues(Ops, 2, dl);
397 SDValue MipsTargetLowering::
398 LowerANDOR(SDValue Op, SelectionDAG &DAG) const
400 SDValue LHS = Op.getOperand(0);
401 SDValue RHS = Op.getOperand(1);
402 DebugLoc dl = Op.getDebugLoc();
404 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
407 SDValue True = DAG.getConstant(1, MVT::i32);
408 SDValue False = DAG.getConstant(0, MVT::i32);
410 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
411 LHS, True, False, LHS.getOperand(2));
412 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
413 RHS, True, False, RHS.getOperand(2));
415 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
418 SDValue MipsTargetLowering::
419 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
421 // The first operand is the chain, the second is the condition, the third is
422 // the block to branch to if the condition is true.
423 SDValue Chain = Op.getOperand(0);
424 SDValue Dest = Op.getOperand(2);
425 DebugLoc dl = Op.getDebugLoc();
427 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
430 SDValue CondRes = Op.getOperand(1);
431 SDValue CCNode = CondRes.getOperand(2);
433 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
434 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
436 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
440 SDValue MipsTargetLowering::
441 LowerSETCC(SDValue Op, SelectionDAG &DAG) const
443 // The operands to this are the left and right operands to compare (ops #0,
444 // and #1) and the condition code to compare them with (op #2) as a
446 SDValue LHS = Op.getOperand(0);
447 SDValue RHS = Op.getOperand(1);
448 DebugLoc dl = Op.getDebugLoc();
450 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
452 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
453 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
456 SDValue MipsTargetLowering::
457 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
459 SDValue Cond = Op.getOperand(0);
460 SDValue True = Op.getOperand(1);
461 SDValue False = Op.getOperand(2);
462 DebugLoc dl = Op.getDebugLoc();
464 // if the incomming condition comes from a integer compare, the select
465 // operation must be SelectCC or a conditional move if the subtarget
467 if (Cond.getOpcode() != MipsISD::FPCmp) {
468 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
470 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
474 // if the incomming condition comes from fpcmp, the select
475 // operation must use FPSelectCC.
476 SDValue CCNode = Cond.getOperand(2);
477 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
478 Cond, True, False, CCNode);
481 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
482 SelectionDAG &DAG) const {
483 // FIXME there isn't actually debug info here
484 DebugLoc dl = Op.getDebugLoc();
485 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
487 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
488 SDVTList VTs = DAG.getVTList(MVT::i32);
490 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
492 // %gp_rel relocation
493 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
494 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
496 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
497 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
498 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
500 // %hi/%lo relocation
501 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
502 MipsII::MO_ABS_HILO);
503 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
504 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
505 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
508 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
510 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
511 DAG.getEntryNode(), GA, MachinePointerInfo(),
513 // On functions and global targets not internal linked only
514 // a load from got/GP is necessary for PIC to work.
515 if (!GV->hasLocalLinkage() || isa<Function>(GV))
517 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
518 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
521 llvm_unreachable("Dont know how to handle GlobalAddress");
525 SDValue MipsTargetLowering::
526 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
528 llvm_unreachable("TLS not implemented for MIPS.");
529 return SDValue(); // Not reached
532 SDValue MipsTargetLowering::
533 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
537 // FIXME there isn't actually debug info here
538 DebugLoc dl = Op.getDebugLoc();
539 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
540 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
542 EVT PtrVT = Op.getValueType();
543 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
545 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
548 SDValue Ops[] = { JTI };
549 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
550 } else // Emit Load from Global Pointer
551 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
552 MachinePointerInfo(),
555 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
556 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
561 SDValue MipsTargetLowering::
562 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
565 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
566 const Constant *C = N->getConstVal();
567 // FIXME there isn't actually debug info here
568 DebugLoc dl = Op.getDebugLoc();
571 // FIXME: we should reference the constant pool using small data sections,
572 // but the asm printer currently doens't support this feature without
573 // hacking it. This feature should come soon so we can uncomment the
575 //if (IsInSmallSection(C->getType())) {
576 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
577 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
578 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
580 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
581 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
582 N->getOffset(), MipsII::MO_ABS_HILO);
583 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
584 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
585 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
587 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
588 N->getOffset(), MipsII::MO_GOT);
589 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
590 CP, MachinePointerInfo::getConstantPool(),
592 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
593 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
599 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
600 MachineFunction &MF = DAG.getMachineFunction();
601 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
603 DebugLoc dl = Op.getDebugLoc();
604 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
607 // vastart just stores the address of the VarArgsFrameIndex slot into the
608 // memory location argument.
609 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
610 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
611 MachinePointerInfo(SV),
615 //===----------------------------------------------------------------------===//
616 // Calling Convention Implementation
617 //===----------------------------------------------------------------------===//
619 #include "MipsGenCallingConv.inc"
621 //===----------------------------------------------------------------------===//
622 // TODO: Implement a generic logic using tblgen that can support this.
623 // Mips O32 ABI rules:
625 // i32 - Passed in A0, A1, A2, A3 and stack
626 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
627 // an argument. Otherwise, passed in A1, A2, A3 and stack.
628 // f64 - Only passed in two aliased f32 registers if no int reg has been used
629 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
630 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
632 //===----------------------------------------------------------------------===//
634 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
635 MVT LocVT, CCValAssign::LocInfo LocInfo,
636 ISD::ArgFlagsTy ArgFlags, CCState &State) {
638 static const unsigned IntRegsSize=4, FloatRegsSize=2;
640 static const unsigned IntRegs[] = {
641 Mips::A0, Mips::A1, Mips::A2, Mips::A3
643 static const unsigned F32Regs[] = {
646 static const unsigned F64Regs[] = {
651 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
652 bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0)));
654 // Promote i8 and i16
655 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
657 if (ArgFlags.isSExt())
658 LocInfo = CCValAssign::SExt;
659 else if (ArgFlags.isZExt())
660 LocInfo = CCValAssign::ZExt;
662 LocInfo = CCValAssign::AExt;
665 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) {
666 Reg = State.AllocateReg(IntRegs, IntRegsSize);
671 if (ValVT.isFloatingPoint() && !IntRegUsed) {
672 if (ValVT == MVT::f32)
673 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
675 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
678 if (ValVT == MVT::f64 && IntRegUsed) {
679 if (UnallocIntReg != IntRegsSize) {
680 // If we hit register A3 as the first not allocated, we must
681 // mark it as allocated (shadow) and use the stack instead.
682 if (IntRegs[UnallocIntReg] != (unsigned (Mips::A3)))
684 for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg)
685 State.AllocateReg(UnallocIntReg);
691 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
692 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
693 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
695 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
697 return false; // CC must always match
700 static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT,
701 MVT LocVT, CCValAssign::LocInfo LocInfo,
702 ISD::ArgFlagsTy ArgFlags, CCState &State) {
704 static const unsigned IntRegsSize=4;
706 static const unsigned IntRegs[] = {
707 Mips::A0, Mips::A1, Mips::A2, Mips::A3
710 // Promote i8 and i16
711 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
713 if (ArgFlags.isSExt())
714 LocInfo = CCValAssign::SExt;
715 else if (ArgFlags.isZExt())
716 LocInfo = CCValAssign::ZExt;
718 LocInfo = CCValAssign::AExt;
721 if (ValVT == MVT::i32 || ValVT == MVT::f32) {
722 if (unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize)) {
723 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
726 unsigned Off = State.AllocateStack(4, 4);
727 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
731 unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
732 if (ValVT == MVT::f64) {
733 if (IntRegs[UnallocIntReg] == (unsigned (Mips::A1))) {
734 // A1 can't be used anymore, because 64 bit arguments
735 // must be aligned when copied back to the caller stack
736 State.AllocateReg(IntRegs, IntRegsSize);
740 if (IntRegs[UnallocIntReg] == (unsigned (Mips::A0)) ||
741 IntRegs[UnallocIntReg] == (unsigned (Mips::A2))) {
742 unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize);
743 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
744 // Shadow the next register so it can be used
745 // later to get the other 32bit part.
746 State.AllocateReg(IntRegs, IntRegsSize);
750 // Register is shadowed to preserve alignment, and the
751 // argument goes to a stack location.
752 if (UnallocIntReg != IntRegsSize)
753 State.AllocateReg(IntRegs, IntRegsSize);
755 unsigned Off = State.AllocateStack(8, 8);
756 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
760 return true; // CC didn't match
763 //===----------------------------------------------------------------------===//
764 // Call Calling Convention Implementation
765 //===----------------------------------------------------------------------===//
767 /// LowerCall - functions arguments are copied from virtual regs to
768 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
769 /// TODO: isTailCall.
771 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
772 CallingConv::ID CallConv, bool isVarArg,
774 const SmallVectorImpl<ISD::OutputArg> &Outs,
775 const SmallVectorImpl<SDValue> &OutVals,
776 const SmallVectorImpl<ISD::InputArg> &Ins,
777 DebugLoc dl, SelectionDAG &DAG,
778 SmallVectorImpl<SDValue> &InVals) const {
779 // MIPs target does not yet support tail call optimization.
782 MachineFunction &MF = DAG.getMachineFunction();
783 MachineFrameInfo *MFI = MF.getFrameInfo();
784 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
786 // Analyze operands of the call, assigning locations to each operand.
787 SmallVector<CCValAssign, 16> ArgLocs;
788 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
791 // To meet O32 ABI, Mips must always allocate 16 bytes on
792 // the stack (even if less than 4 are used as arguments)
793 if (Subtarget->isABI_O32()) {
794 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
795 MFI->CreateFixedObject(VTsize, (VTsize*3), true);
796 CCInfo.AnalyzeCallOperands(Outs,
797 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
799 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
801 // Get a count of how many bytes are to be pushed on the stack.
802 unsigned NumBytes = CCInfo.getNextStackOffset();
803 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
805 // With EABI is it possible to have 16 args on registers.
806 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
807 SmallVector<SDValue, 8> MemOpChains;
809 // First/LastArgStackLoc contains the first/last
810 // "at stack" argument location.
811 int LastArgStackLoc = 0;
812 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
814 // Walk the register/memloc assignments, inserting copies/loads.
815 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
816 SDValue Arg = OutVals[i];
817 CCValAssign &VA = ArgLocs[i];
819 // Promote the value if needed.
820 switch (VA.getLocInfo()) {
821 default: llvm_unreachable("Unknown loc info!");
822 case CCValAssign::Full:
823 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
824 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
825 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
826 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
827 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
828 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
829 DAG.getConstant(0, getPointerTy()));
830 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
831 DAG.getConstant(1, getPointerTy()));
832 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
833 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
838 case CCValAssign::SExt:
839 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
841 case CCValAssign::ZExt:
842 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
844 case CCValAssign::AExt:
845 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
849 // Arguments that can be passed on register must be kept at
852 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
856 // Register can't get to this point...
857 assert(VA.isMemLoc());
859 // Create the frame index object for this incoming parameter
860 // This guarantees that when allocating Local Area the firsts
861 // 16 bytes which are alwayes reserved won't be overwritten
862 // if O32 ABI is used. For EABI the first address is zero.
863 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
864 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
865 LastArgStackLoc, true);
867 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
869 // emit ISD::STORE whichs stores the
870 // parameter value to a stack Location
871 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
872 MachinePointerInfo(),
876 // Transform all store nodes into one single node because all store
877 // nodes are independent of each other.
878 if (!MemOpChains.empty())
879 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
880 &MemOpChains[0], MemOpChains.size());
882 // Build a sequence of copy-to-reg nodes chained together with token
883 // chain and flag operands which copy the outgoing args into registers.
884 // The InFlag in necessary since all emited instructions must be
887 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
888 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
889 RegsToPass[i].second, InFlag);
890 InFlag = Chain.getValue(1);
893 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
894 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
895 // node so that legalize doesn't hack it.
896 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
897 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
898 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
899 getPointerTy(), 0, OpFlag);
900 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
901 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
902 getPointerTy(), OpFlag);
904 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
905 // = Chain, Callee, Reg#1, Reg#2, ...
907 // Returns a chain & a flag for retval copy to use.
908 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
909 SmallVector<SDValue, 8> Ops;
910 Ops.push_back(Chain);
911 Ops.push_back(Callee);
913 // Add argument registers to the end of the list so that they are
914 // known live into the call.
915 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
916 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
917 RegsToPass[i].second.getValueType()));
919 if (InFlag.getNode())
920 Ops.push_back(InFlag);
922 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
923 InFlag = Chain.getValue(1);
925 // Create a stack location to hold GP when PIC is used. This stack
926 // location is used on function prologue to save GP and also after all
927 // emited CALL's to restore GP.
929 // Function can have an arbitrary number of calls, so
930 // hold the LastArgStackLoc with the biggest offset.
932 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
933 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
934 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
935 // Create the frame index only once. SPOffset here can be anything
936 // (this will be fixed on processFunctionBeforeFrameFinalized)
937 if (MipsFI->getGPStackOffset() == -1) {
938 FI = MFI->CreateFixedObject(4, 0, true);
941 MipsFI->setGPStackOffset(LastArgStackLoc);
945 FI = MipsFI->getGPFI();
946 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
947 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN,
948 MachinePointerInfo::getFixedStack(FI),
950 Chain = GPLoad.getValue(1);
951 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
952 GPLoad, SDValue(0,0));
953 InFlag = Chain.getValue(1);
956 // Create the CALLSEQ_END node.
957 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
958 DAG.getIntPtrConstant(0, true), InFlag);
959 InFlag = Chain.getValue(1);
961 // Handle result values, copying them out of physregs into vregs that we
963 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
964 Ins, dl, DAG, InVals);
967 /// LowerCallResult - Lower the result values of a call into the
968 /// appropriate copies out of appropriate physical registers.
970 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
971 CallingConv::ID CallConv, bool isVarArg,
972 const SmallVectorImpl<ISD::InputArg> &Ins,
973 DebugLoc dl, SelectionDAG &DAG,
974 SmallVectorImpl<SDValue> &InVals) const {
976 // Assign locations to each value returned by this call.
977 SmallVector<CCValAssign, 16> RVLocs;
978 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
979 RVLocs, *DAG.getContext());
981 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
983 // Copy all of the result registers out of their specified physreg.
984 for (unsigned i = 0; i != RVLocs.size(); ++i) {
985 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
986 RVLocs[i].getValVT(), InFlag).getValue(1);
987 InFlag = Chain.getValue(2);
988 InVals.push_back(Chain.getValue(0));
994 //===----------------------------------------------------------------------===//
995 // Formal Arguments Calling Convention Implementation
996 //===----------------------------------------------------------------------===//
998 /// LowerFormalArguments - transform physical registers into virtual registers
999 /// and generate load operations for arguments places on the stack.
1001 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
1002 CallingConv::ID CallConv, bool isVarArg,
1003 const SmallVectorImpl<ISD::InputArg>
1005 DebugLoc dl, SelectionDAG &DAG,
1006 SmallVectorImpl<SDValue> &InVals)
1009 MachineFunction &MF = DAG.getMachineFunction();
1010 MachineFrameInfo *MFI = MF.getFrameInfo();
1011 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1013 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
1014 MipsFI->setVarArgsFrameIndex(0);
1016 // Used with vargs to acumulate store chains.
1017 std::vector<SDValue> OutChains;
1019 // Keep track of the last register used for arguments
1020 unsigned ArgRegEnd = 0;
1022 // Assign locations to all of the incoming arguments.
1023 SmallVector<CCValAssign, 16> ArgLocs;
1024 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1025 ArgLocs, *DAG.getContext());
1027 if (Subtarget->isABI_O32())
1028 CCInfo.AnalyzeFormalArguments(Ins,
1029 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1031 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1035 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1037 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1038 CCValAssign &VA = ArgLocs[i];
1040 // Arguments stored on registers
1041 if (VA.isRegLoc()) {
1042 EVT RegVT = VA.getLocVT();
1043 ArgRegEnd = VA.getLocReg();
1044 TargetRegisterClass *RC = 0;
1046 if (RegVT == MVT::i32)
1047 RC = Mips::CPURegsRegisterClass;
1048 else if (RegVT == MVT::f32)
1049 RC = Mips::FGR32RegisterClass;
1050 else if (RegVT == MVT::f64) {
1051 if (!Subtarget->isSingleFloat())
1052 RC = Mips::AFGR64RegisterClass;
1054 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1056 // Transform the arguments stored on
1057 // physical registers into virtual ones
1058 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1059 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1061 // If this is an 8 or 16-bit value, it has been passed promoted
1062 // to 32 bits. Insert an assert[sz]ext to capture this, then
1063 // truncate to the right size.
1064 if (VA.getLocInfo() != CCValAssign::Full) {
1065 unsigned Opcode = 0;
1066 if (VA.getLocInfo() == CCValAssign::SExt)
1067 Opcode = ISD::AssertSext;
1068 else if (VA.getLocInfo() == CCValAssign::ZExt)
1069 Opcode = ISD::AssertZext;
1071 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1072 DAG.getValueType(VA.getValVT()));
1073 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1076 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1077 if (Subtarget->isABI_O32()) {
1078 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1079 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1080 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1081 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1082 VA.getLocReg()+1, RC);
1083 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1084 SDValue Hi = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1085 SDValue Lo = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue2);
1086 ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi);
1090 InVals.push_back(ArgValue);
1091 } else { // VA.isRegLoc()
1094 assert(VA.isMemLoc());
1096 // The last argument is not a register anymore
1099 // The stack pointer offset is relative to the caller stack frame.
1100 // Since the real stack size is unknown here, a negative SPOffset
1101 // is used so there's a way to adjust these offsets when the stack
1102 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1103 // used instead of a direct negative address (which is recorded to
1104 // be used on emitPrologue) to avoid mis-calc of the first stack
1105 // offset on PEI::calculateFrameObjectOffsets.
1106 // Arguments are always 32-bit.
1107 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1108 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
1109 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
1110 (FirstStackArgLoc + VA.getLocMemOffset())));
1112 // Create load nodes to retrieve arguments from the stack
1113 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1114 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1115 MachinePointerInfo::getFixedStack(FI),
1120 // The mips ABIs for returning structs by value requires that we copy
1121 // the sret argument into $v0 for the return. Save the argument into
1122 // a virtual register so that we can access it from the return points.
1123 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1124 unsigned Reg = MipsFI->getSRetReturnReg();
1126 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1127 MipsFI->setSRetReturnReg(Reg);
1129 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1130 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1133 // To meet ABI, when VARARGS are passed on registers, the registers
1134 // must have their values written to the caller stack frame. If the last
1135 // argument was placed in the stack, there's no need to save any register.
1136 if ((isVarArg) && (Subtarget->isABI_O32() && ArgRegEnd)) {
1137 if (StackPtr.getNode() == 0)
1138 StackPtr = DAG.getRegister(StackReg, getPointerTy());
1140 // The last register argument that must be saved is Mips::A3
1141 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1142 unsigned StackLoc = ArgLocs.size()-1;
1144 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd, ++StackLoc) {
1145 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1146 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1148 int FI = MFI->CreateFixedObject(4, 0, true);
1149 MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
1150 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1151 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
1152 MachinePointerInfo(),
1155 // Record the frame index of the first variable argument
1156 // which is a value necessary to VASTART.
1157 if (!MipsFI->getVarArgsFrameIndex())
1158 MipsFI->setVarArgsFrameIndex(FI);
1162 // All stores are grouped in one node to allow the matching between
1163 // the size of Ins and InVals. This only happens when on varg functions
1164 if (!OutChains.empty()) {
1165 OutChains.push_back(Chain);
1166 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1167 &OutChains[0], OutChains.size());
1173 //===----------------------------------------------------------------------===//
1174 // Return Value Calling Convention Implementation
1175 //===----------------------------------------------------------------------===//
1178 MipsTargetLowering::LowerReturn(SDValue Chain,
1179 CallingConv::ID CallConv, bool isVarArg,
1180 const SmallVectorImpl<ISD::OutputArg> &Outs,
1181 const SmallVectorImpl<SDValue> &OutVals,
1182 DebugLoc dl, SelectionDAG &DAG) const {
1184 // CCValAssign - represent the assignment of
1185 // the return value to a location
1186 SmallVector<CCValAssign, 16> RVLocs;
1188 // CCState - Info about the registers and stack slot.
1189 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1190 RVLocs, *DAG.getContext());
1192 // Analize return values.
1193 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1195 // If this is the first return lowered for this function, add
1196 // the regs to the liveout set for the function.
1197 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1198 for (unsigned i = 0; i != RVLocs.size(); ++i)
1199 if (RVLocs[i].isRegLoc())
1200 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1205 // Copy the result values into the output registers.
1206 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1207 CCValAssign &VA = RVLocs[i];
1208 assert(VA.isRegLoc() && "Can only return in registers!");
1210 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1213 // guarantee that all emitted copies are
1214 // stuck together, avoiding something bad
1215 Flag = Chain.getValue(1);
1218 // The mips ABIs for returning structs by value requires that we copy
1219 // the sret argument into $v0 for the return. We saved the argument into
1220 // a virtual register in the entry block, so now we copy the value out
1222 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1223 MachineFunction &MF = DAG.getMachineFunction();
1224 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1225 unsigned Reg = MipsFI->getSRetReturnReg();
1228 llvm_unreachable("sret virtual register not created in the entry block");
1229 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1231 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1232 Flag = Chain.getValue(1);
1235 // Return on Mips is always a "jr $ra"
1237 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1238 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1240 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1241 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1244 //===----------------------------------------------------------------------===//
1245 // Mips Inline Assembly Support
1246 //===----------------------------------------------------------------------===//
1248 /// getConstraintType - Given a constraint letter, return the type of
1249 /// constraint it is for this target.
1250 MipsTargetLowering::ConstraintType MipsTargetLowering::
1251 getConstraintType(const std::string &Constraint) const
1253 // Mips specific constrainy
1254 // GCC config/mips/constraints.md
1256 // 'd' : An address register. Equivalent to r
1257 // unless generating MIPS16 code.
1258 // 'y' : Equivalent to r; retained for
1259 // backwards compatibility.
1260 // 'f' : Floating Point registers.
1261 if (Constraint.size() == 1) {
1262 switch (Constraint[0]) {
1267 return C_RegisterClass;
1271 return TargetLowering::getConstraintType(Constraint);
1274 /// Examine constraint type and operand type and determine a weight value.
1275 /// This object must already have been set up with the operand type
1276 /// and the current alternative constraint selected.
1277 TargetLowering::ConstraintWeight
1278 MipsTargetLowering::getSingleConstraintMatchWeight(
1279 AsmOperandInfo &info, const char *constraint) const {
1280 ConstraintWeight weight = CW_Invalid;
1281 Value *CallOperandVal = info.CallOperandVal;
1282 // If we don't have a value, we can't do a match,
1283 // but allow it at the lowest weight.
1284 if (CallOperandVal == NULL)
1286 const Type *type = CallOperandVal->getType();
1287 // Look at the constraint type.
1288 switch (*constraint) {
1290 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1294 if (type->isIntegerTy())
1295 weight = CW_Register;
1298 if (type->isFloatTy())
1299 weight = CW_Register;
1305 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1306 /// return a list of registers that can be used to satisfy the constraint.
1307 /// This should only be used for C_RegisterClass constraints.
1308 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1309 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1311 if (Constraint.size() == 1) {
1312 switch (Constraint[0]) {
1314 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1317 return std::make_pair(0U, Mips::FGR32RegisterClass);
1319 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1320 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1323 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1326 /// Given a register class constraint, like 'r', if this corresponds directly
1327 /// to an LLVM register class, return a register of 0 and the register class
1329 std::vector<unsigned> MipsTargetLowering::
1330 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1333 if (Constraint.size() != 1)
1334 return std::vector<unsigned>();
1336 switch (Constraint[0]) {
1339 // GCC Mips Constraint Letters
1342 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1343 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1344 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1348 if (VT == MVT::f32) {
1349 if (Subtarget->isSingleFloat())
1350 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1351 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1352 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1353 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1354 Mips::F30, Mips::F31, 0);
1356 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1357 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1358 Mips::F28, Mips::F30, 0);
1362 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1363 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1364 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1365 Mips::D14, Mips::D15, 0);
1367 return std::vector<unsigned>();
1371 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1372 // The Mips target isn't yet aware of offsets.
1376 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1377 if (VT != MVT::f32 && VT != MVT::f64)
1379 return Imm.isZero();