1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "InstPrinter/MipsInstPrinter.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
38 // If I is a shifted mask, set the size (Size) and the first bit of the
39 // mask (Pos), and return true.
40 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
41 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
42 if (!isUInt<32>(I) || !isShiftedMask_32(I))
45 Size = CountPopulation_32(I);
46 Pos = CountTrailingZeros_32(I);
50 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
52 case MipsISD::JmpLink: return "MipsISD::JmpLink";
53 case MipsISD::Hi: return "MipsISD::Hi";
54 case MipsISD::Lo: return "MipsISD::Lo";
55 case MipsISD::GPRel: return "MipsISD::GPRel";
56 case MipsISD::TlsGd: return "MipsISD::TlsGd";
57 case MipsISD::TprelHi: return "MipsISD::TprelHi";
58 case MipsISD::TprelLo: return "MipsISD::TprelLo";
59 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
60 case MipsISD::Ret: return "MipsISD::Ret";
61 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
62 case MipsISD::FPCmp: return "MipsISD::FPCmp";
63 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
64 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
65 case MipsISD::FPRound: return "MipsISD::FPRound";
66 case MipsISD::MAdd: return "MipsISD::MAdd";
67 case MipsISD::MAddu: return "MipsISD::MAddu";
68 case MipsISD::MSub: return "MipsISD::MSub";
69 case MipsISD::MSubu: return "MipsISD::MSubu";
70 case MipsISD::DivRem: return "MipsISD::DivRem";
71 case MipsISD::DivRemU: return "MipsISD::DivRemU";
72 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
73 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
74 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC";
75 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
76 case MipsISD::Sync: return "MipsISD::Sync";
77 case MipsISD::Ext: return "MipsISD::Ext";
78 case MipsISD::Ins: return "MipsISD::Ins";
84 MipsTargetLowering(MipsTargetMachine &TM)
85 : TargetLowering(TM, new MipsTargetObjectFile()),
86 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
87 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
88 IsO32(Subtarget->isABI_O32()) {
90 // Mips does not have i1 type, so use i32 for
91 // setcc operations results (slt, sgt, ...).
92 setBooleanContents(ZeroOrOneBooleanContent);
93 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
95 // Set up the register classes
96 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
97 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
100 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
102 // When dealing with single precision only, use libcalls
103 if (!Subtarget->isSingleFloat()) {
105 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
107 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
110 // Load extented operations for i1 types must be promoted
111 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
112 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
113 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
115 // MIPS doesn't have extending float->double load/store
116 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
117 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
119 // Used by legalize types to correctly generate the setcc result.
120 // Without this, every float setcc comes with a AND/OR with the result,
121 // we don't want this, since the fpcmp result goes to a flag register,
122 // which is used implicitly by brcond and select operations.
123 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
125 // Mips Custom Operations
126 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
127 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
128 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
129 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
130 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
131 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
132 setOperationAction(ISD::SELECT, MVT::f32, Custom);
133 setOperationAction(ISD::SELECT, MVT::f64, Custom);
134 setOperationAction(ISD::SELECT, MVT::i32, Custom);
135 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
136 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
137 setOperationAction(ISD::VASTART, MVT::Other, Custom);
139 setOperationAction(ISD::SDIV, MVT::i32, Expand);
140 setOperationAction(ISD::SREM, MVT::i32, Expand);
141 setOperationAction(ISD::UDIV, MVT::i32, Expand);
142 setOperationAction(ISD::UREM, MVT::i32, Expand);
143 setOperationAction(ISD::SDIV, MVT::i64, Expand);
144 setOperationAction(ISD::SREM, MVT::i64, Expand);
145 setOperationAction(ISD::UDIV, MVT::i64, Expand);
146 setOperationAction(ISD::UREM, MVT::i64, Expand);
148 // Operations not directly supported by Mips.
149 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
150 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
151 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
153 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
155 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
156 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
157 setOperationAction(ISD::ROTL, MVT::i32, Expand);
158 setOperationAction(ISD::ROTL, MVT::i64, Expand);
160 if (!Subtarget->hasMips32r2())
161 setOperationAction(ISD::ROTR, MVT::i32, Expand);
163 if (!Subtarget->hasMips64r2())
164 setOperationAction(ISD::ROTR, MVT::i64, Expand);
166 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
167 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
168 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
169 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
170 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
171 setOperationAction(ISD::FSIN, MVT::f32, Expand);
172 setOperationAction(ISD::FSIN, MVT::f64, Expand);
173 setOperationAction(ISD::FCOS, MVT::f32, Expand);
174 setOperationAction(ISD::FCOS, MVT::f64, Expand);
175 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
176 setOperationAction(ISD::FPOW, MVT::f32, Expand);
177 setOperationAction(ISD::FPOW, MVT::f64, Expand);
178 setOperationAction(ISD::FLOG, MVT::f32, Expand);
179 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
180 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
181 setOperationAction(ISD::FEXP, MVT::f32, Expand);
182 setOperationAction(ISD::FMA, MVT::f32, Expand);
183 setOperationAction(ISD::FMA, MVT::f64, Expand);
185 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
186 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
188 setOperationAction(ISD::VAARG, MVT::Other, Expand);
189 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
190 setOperationAction(ISD::VAEND, MVT::Other, Expand);
192 // Use the default for now
193 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
194 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
196 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
197 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
199 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
200 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
202 setInsertFencesForAtomic(true);
204 if (Subtarget->isSingleFloat())
205 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
207 if (!Subtarget->hasSEInReg()) {
208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
212 if (!Subtarget->hasBitCount())
213 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
215 if (!Subtarget->hasSwap())
216 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
218 setTargetDAGCombine(ISD::ADDE);
219 setTargetDAGCombine(ISD::SUBE);
220 setTargetDAGCombine(ISD::SDIVREM);
221 setTargetDAGCombine(ISD::UDIVREM);
222 setTargetDAGCombine(ISD::SETCC);
223 setTargetDAGCombine(ISD::AND);
224 setTargetDAGCombine(ISD::OR);
226 setMinFunctionAlignment(2);
228 setStackPointerRegisterToSaveRestore(Mips::SP);
229 computeRegisterProperties();
231 setExceptionPointerRegister(Mips::A0);
232 setExceptionSelectorRegister(Mips::A1);
235 bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
236 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
237 return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16;
240 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
245 // Transforms a subgraph in CurDAG if the following pattern is found:
246 // (addc multLo, Lo0), (adde multHi, Hi0),
248 // multHi/Lo: product of multiplication
249 // Lo0: initial value of Lo register
250 // Hi0: initial value of Hi register
251 // Return true if pattern matching was successful.
252 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
253 // ADDENode's second operand must be a flag output of an ADDC node in order
254 // for the matching to be successful.
255 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
257 if (ADDCNode->getOpcode() != ISD::ADDC)
260 SDValue MultHi = ADDENode->getOperand(0);
261 SDValue MultLo = ADDCNode->getOperand(0);
262 SDNode* MultNode = MultHi.getNode();
263 unsigned MultOpc = MultHi.getOpcode();
265 // MultHi and MultLo must be generated by the same node,
266 if (MultLo.getNode() != MultNode)
269 // and it must be a multiplication.
270 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
273 // MultLo amd MultHi must be the first and second output of MultNode
275 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
278 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
279 // of the values of MultNode, in which case MultNode will be removed in later
281 // If there exist users other than ADDENode or ADDCNode, this function returns
282 // here, which will result in MultNode being mapped to a single MULT
283 // instruction node rather than a pair of MULT and MADD instructions being
285 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
288 SDValue Chain = CurDAG->getEntryNode();
289 DebugLoc dl = ADDENode->getDebugLoc();
291 // create MipsMAdd(u) node
292 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
294 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
296 MultNode->getOperand(0),// Factor 0
297 MultNode->getOperand(1),// Factor 1
298 ADDCNode->getOperand(1),// Lo0
299 ADDENode->getOperand(1));// Hi0
301 // create CopyFromReg nodes
302 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
304 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
306 CopyFromLo.getValue(2));
308 // replace uses of adde and addc here
309 if (!SDValue(ADDCNode, 0).use_empty())
310 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
312 if (!SDValue(ADDENode, 0).use_empty())
313 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
319 // Transforms a subgraph in CurDAG if the following pattern is found:
320 // (addc Lo0, multLo), (sube Hi0, multHi),
322 // multHi/Lo: product of multiplication
323 // Lo0: initial value of Lo register
324 // Hi0: initial value of Hi register
325 // Return true if pattern matching was successful.
326 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
327 // SUBENode's second operand must be a flag output of an SUBC node in order
328 // for the matching to be successful.
329 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
331 if (SUBCNode->getOpcode() != ISD::SUBC)
334 SDValue MultHi = SUBENode->getOperand(1);
335 SDValue MultLo = SUBCNode->getOperand(1);
336 SDNode* MultNode = MultHi.getNode();
337 unsigned MultOpc = MultHi.getOpcode();
339 // MultHi and MultLo must be generated by the same node,
340 if (MultLo.getNode() != MultNode)
343 // and it must be a multiplication.
344 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
347 // MultLo amd MultHi must be the first and second output of MultNode
349 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
352 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
353 // of the values of MultNode, in which case MultNode will be removed in later
355 // If there exist users other than SUBENode or SUBCNode, this function returns
356 // here, which will result in MultNode being mapped to a single MULT
357 // instruction node rather than a pair of MULT and MSUB instructions being
359 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
362 SDValue Chain = CurDAG->getEntryNode();
363 DebugLoc dl = SUBENode->getDebugLoc();
365 // create MipsSub(u) node
366 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
368 SDValue MSub = CurDAG->getNode(MultOpc, dl,
370 MultNode->getOperand(0),// Factor 0
371 MultNode->getOperand(1),// Factor 1
372 SUBCNode->getOperand(0),// Lo0
373 SUBENode->getOperand(0));// Hi0
375 // create CopyFromReg nodes
376 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
378 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
380 CopyFromLo.getValue(2));
382 // replace uses of sube and subc here
383 if (!SDValue(SUBCNode, 0).use_empty())
384 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
386 if (!SDValue(SUBENode, 0).use_empty())
387 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
392 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
393 TargetLowering::DAGCombinerInfo &DCI,
394 const MipsSubtarget* Subtarget) {
395 if (DCI.isBeforeLegalize())
398 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
400 return SDValue(N, 0);
405 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
406 TargetLowering::DAGCombinerInfo &DCI,
407 const MipsSubtarget* Subtarget) {
408 if (DCI.isBeforeLegalize())
411 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
413 return SDValue(N, 0);
418 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
419 TargetLowering::DAGCombinerInfo &DCI,
420 const MipsSubtarget* Subtarget) {
421 if (DCI.isBeforeLegalizeOps())
424 EVT Ty = N->getValueType(0);
425 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
426 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
427 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
429 DebugLoc dl = N->getDebugLoc();
431 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
432 N->getOperand(0), N->getOperand(1));
433 SDValue InChain = DAG.getEntryNode();
434 SDValue InGlue = DivRem;
437 if (N->hasAnyUseOfValue(0)) {
438 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
440 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
441 InChain = CopyFromLo.getValue(1);
442 InGlue = CopyFromLo.getValue(2);
446 if (N->hasAnyUseOfValue(1)) {
447 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
449 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
455 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
457 default: llvm_unreachable("Unknown fp condition code!");
459 case ISD::SETOEQ: return Mips::FCOND_OEQ;
460 case ISD::SETUNE: return Mips::FCOND_UNE;
462 case ISD::SETOLT: return Mips::FCOND_OLT;
464 case ISD::SETOGT: return Mips::FCOND_OGT;
466 case ISD::SETOLE: return Mips::FCOND_OLE;
468 case ISD::SETOGE: return Mips::FCOND_OGE;
469 case ISD::SETULT: return Mips::FCOND_ULT;
470 case ISD::SETULE: return Mips::FCOND_ULE;
471 case ISD::SETUGT: return Mips::FCOND_UGT;
472 case ISD::SETUGE: return Mips::FCOND_UGE;
473 case ISD::SETUO: return Mips::FCOND_UN;
474 case ISD::SETO: return Mips::FCOND_OR;
476 case ISD::SETONE: return Mips::FCOND_ONE;
477 case ISD::SETUEQ: return Mips::FCOND_UEQ;
482 // Returns true if condition code has to be inverted.
483 static bool InvertFPCondCode(Mips::CondCode CC) {
484 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
487 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
490 assert(false && "Illegal Condition Code");
494 // Creates and returns an FPCmp node from a setcc node.
495 // Returns Op if setcc is not a floating point comparison.
496 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
497 // must be a SETCC node
498 if (Op.getOpcode() != ISD::SETCC)
501 SDValue LHS = Op.getOperand(0);
503 if (!LHS.getValueType().isFloatingPoint())
506 SDValue RHS = Op.getOperand(1);
507 DebugLoc dl = Op.getDebugLoc();
509 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
510 // node if necessary.
511 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
513 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
514 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
517 // Creates and returns a CMovFPT/F node.
518 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
519 SDValue False, DebugLoc DL) {
520 bool invert = InvertFPCondCode((Mips::CondCode)
521 cast<ConstantSDNode>(Cond.getOperand(2))
524 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
525 True.getValueType(), True, False, Cond);
528 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
529 TargetLowering::DAGCombinerInfo &DCI,
530 const MipsSubtarget* Subtarget) {
531 if (DCI.isBeforeLegalizeOps())
534 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
536 if (Cond.getOpcode() != MipsISD::FPCmp)
539 SDValue True = DAG.getConstant(1, MVT::i32);
540 SDValue False = DAG.getConstant(0, MVT::i32);
542 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
545 static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
546 TargetLowering::DAGCombinerInfo &DCI,
547 const MipsSubtarget* Subtarget) {
548 // Pattern match EXT.
549 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
550 // => ext $dst, $src, size, pos
551 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
554 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
556 // Op's first operand must be a shift right.
557 if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL)
560 // The second operand of the shift must be an immediate.
563 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
566 Pos = CN->getZExtValue();
568 uint64_t SMPos, SMSize;
569 // Op's second operand must be a shifted mask.
570 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
571 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
574 // Return if the shifted mask does not start at bit 0 or the sum of its size
575 // and Pos exceeds the word's size.
576 if (SMPos != 0 || Pos + SMSize > 32)
579 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
580 ShiftRight.getOperand(0),
581 DAG.getConstant(Pos, MVT::i32),
582 DAG.getConstant(SMSize, MVT::i32));
585 static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
586 TargetLowering::DAGCombinerInfo &DCI,
587 const MipsSubtarget* Subtarget) {
588 // Pattern match INS.
589 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
590 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
591 // => ins $dst, $src, size, pos, $src1
592 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
595 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
596 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
599 // See if Op's first operand matches (and $src1 , mask0).
600 if (And0.getOpcode() != ISD::AND)
603 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
604 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
607 // See if Op's second operand matches (and (shl $src, pos), mask1).
608 if (And1.getOpcode() != ISD::AND)
611 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
612 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
615 // The shift masks must have the same position and size.
616 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
619 SDValue Shl = And1.getOperand(0);
620 if (Shl.getOpcode() != ISD::SHL)
623 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
626 unsigned Shamt = CN->getZExtValue();
628 // Return if the shift amount and the first bit position of mask are not the
633 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
635 DAG.getConstant(SMPos0, MVT::i32),
636 DAG.getConstant(SMSize0, MVT::i32),
640 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
642 SelectionDAG &DAG = DCI.DAG;
643 unsigned opc = N->getOpcode();
648 return PerformADDECombine(N, DAG, DCI, Subtarget);
650 return PerformSUBECombine(N, DAG, DCI, Subtarget);
653 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
655 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
657 return PerformANDCombine(N, DAG, DCI, Subtarget);
659 return PerformORCombine(N, DAG, DCI, Subtarget);
665 SDValue MipsTargetLowering::
666 LowerOperation(SDValue Op, SelectionDAG &DAG) const
668 switch (Op.getOpcode())
670 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
671 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
672 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
673 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
674 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
675 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
676 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
677 case ISD::SELECT: return LowerSELECT(Op, DAG);
678 case ISD::VASTART: return LowerVASTART(Op, DAG);
679 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
680 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
681 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
682 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
687 //===----------------------------------------------------------------------===//
688 // Lower helper functions
689 //===----------------------------------------------------------------------===//
691 // AddLiveIn - This helper function adds the specified physical register to the
692 // MachineFunction as a live in value. It also creates a corresponding
693 // virtual register for it.
695 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
697 assert(RC->contains(PReg) && "Not the correct regclass!");
698 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
699 MF.getRegInfo().addLiveIn(PReg, VReg);
703 // Get fp branch code (not opcode) from condition code.
704 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
705 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
706 return Mips::BRANCH_T;
708 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
709 return Mips::BRANCH_F;
711 return Mips::BRANCH_INVALID;
715 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
717 const MipsSubtarget* Subtarget,
718 const TargetInstrInfo *TII,
719 bool isFPCmp, unsigned Opc) {
720 // There is no need to expand CMov instructions if target has
721 // conditional moves.
722 if (Subtarget->hasCondMov())
725 // To "insert" a SELECT_CC instruction, we actually have to insert the
726 // diamond control-flow pattern. The incoming instruction knows the
727 // destination vreg to set, the condition code register to branch on, the
728 // true/false values to select between, and a branch opcode to use.
729 const BasicBlock *LLVM_BB = BB->getBasicBlock();
730 MachineFunction::iterator It = BB;
737 // bNE r1, r0, copy1MBB
738 // fallthrough --> copy0MBB
739 MachineBasicBlock *thisMBB = BB;
740 MachineFunction *F = BB->getParent();
741 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
742 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
743 F->insert(It, copy0MBB);
744 F->insert(It, sinkMBB);
746 // Transfer the remainder of BB and its successor edges to sinkMBB.
747 sinkMBB->splice(sinkMBB->begin(), BB,
748 llvm::next(MachineBasicBlock::iterator(MI)),
750 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
752 // Next, add the true and fallthrough blocks as its successors.
753 BB->addSuccessor(copy0MBB);
754 BB->addSuccessor(sinkMBB);
756 // Emit the right instruction according to the type of the operands compared
758 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
760 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
761 .addReg(Mips::ZERO).addMBB(sinkMBB);
765 // # fallthrough to sinkMBB
768 // Update machine-CFG edges
769 BB->addSuccessor(sinkMBB);
772 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
777 BuildMI(*BB, BB->begin(), dl,
778 TII->get(Mips::PHI), MI->getOperand(0).getReg())
779 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
780 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
782 BuildMI(*BB, BB->begin(), dl,
783 TII->get(Mips::PHI), MI->getOperand(0).getReg())
784 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
785 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
787 MI->eraseFromParent(); // The pseudo instruction is gone now.
792 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
793 MachineBasicBlock *BB) const {
794 switch (MI->getOpcode()) {
796 assert(false && "Unexpected instr type to insert");
798 case Mips::ATOMIC_LOAD_ADD_I8:
799 case Mips::ATOMIC_LOAD_ADD_I8_P8:
800 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
801 case Mips::ATOMIC_LOAD_ADD_I16:
802 case Mips::ATOMIC_LOAD_ADD_I16_P8:
803 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
804 case Mips::ATOMIC_LOAD_ADD_I32:
805 case Mips::ATOMIC_LOAD_ADD_I32_P8:
806 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
807 case Mips::ATOMIC_LOAD_ADD_I64:
808 case Mips::ATOMIC_LOAD_ADD_I64_P8:
809 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
811 case Mips::ATOMIC_LOAD_AND_I8:
812 case Mips::ATOMIC_LOAD_AND_I8_P8:
813 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
814 case Mips::ATOMIC_LOAD_AND_I16:
815 case Mips::ATOMIC_LOAD_AND_I16_P8:
816 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
817 case Mips::ATOMIC_LOAD_AND_I32:
818 case Mips::ATOMIC_LOAD_AND_I32_P8:
819 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
820 case Mips::ATOMIC_LOAD_AND_I64:
821 case Mips::ATOMIC_LOAD_AND_I64_P8:
822 return EmitAtomicBinary(MI, BB, 48, Mips::AND64);
824 case Mips::ATOMIC_LOAD_OR_I8:
825 case Mips::ATOMIC_LOAD_OR_I8_P8:
826 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
827 case Mips::ATOMIC_LOAD_OR_I16:
828 case Mips::ATOMIC_LOAD_OR_I16_P8:
829 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
830 case Mips::ATOMIC_LOAD_OR_I32:
831 case Mips::ATOMIC_LOAD_OR_I32_P8:
832 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
833 case Mips::ATOMIC_LOAD_OR_I64:
834 case Mips::ATOMIC_LOAD_OR_I64_P8:
835 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
837 case Mips::ATOMIC_LOAD_XOR_I8:
838 case Mips::ATOMIC_LOAD_XOR_I8_P8:
839 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
840 case Mips::ATOMIC_LOAD_XOR_I16:
841 case Mips::ATOMIC_LOAD_XOR_I16_P8:
842 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
843 case Mips::ATOMIC_LOAD_XOR_I32:
844 case Mips::ATOMIC_LOAD_XOR_I32_P8:
845 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
846 case Mips::ATOMIC_LOAD_XOR_I64:
847 case Mips::ATOMIC_LOAD_XOR_I64_P8:
848 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
850 case Mips::ATOMIC_LOAD_NAND_I8:
851 case Mips::ATOMIC_LOAD_NAND_I8_P8:
852 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
853 case Mips::ATOMIC_LOAD_NAND_I16:
854 case Mips::ATOMIC_LOAD_NAND_I16_P8:
855 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
856 case Mips::ATOMIC_LOAD_NAND_I32:
857 case Mips::ATOMIC_LOAD_NAND_I32_P8:
858 return EmitAtomicBinary(MI, BB, 4, 0, true);
859 case Mips::ATOMIC_LOAD_NAND_I64:
860 case Mips::ATOMIC_LOAD_NAND_I64_P8:
861 return EmitAtomicBinary(MI, BB, 8, 0, true);
863 case Mips::ATOMIC_LOAD_SUB_I8:
864 case Mips::ATOMIC_LOAD_SUB_I8_P8:
865 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
866 case Mips::ATOMIC_LOAD_SUB_I16:
867 case Mips::ATOMIC_LOAD_SUB_I16_P8:
868 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
869 case Mips::ATOMIC_LOAD_SUB_I32:
870 case Mips::ATOMIC_LOAD_SUB_I32_P8:
871 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
872 case Mips::ATOMIC_LOAD_SUB_I64:
873 case Mips::ATOMIC_LOAD_SUB_I64_P8:
874 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
876 case Mips::ATOMIC_SWAP_I8:
877 case Mips::ATOMIC_SWAP_I8_P8:
878 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
879 case Mips::ATOMIC_SWAP_I16:
880 case Mips::ATOMIC_SWAP_I16_P8:
881 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
882 case Mips::ATOMIC_SWAP_I32:
883 case Mips::ATOMIC_SWAP_I32_P8:
884 return EmitAtomicBinary(MI, BB, 4, 0);
885 case Mips::ATOMIC_SWAP_I64:
886 case Mips::ATOMIC_SWAP_I64_P8:
887 return EmitAtomicBinary(MI, BB, 8, 0);
889 case Mips::ATOMIC_CMP_SWAP_I8:
890 case Mips::ATOMIC_CMP_SWAP_I8_P8:
891 return EmitAtomicCmpSwapPartword(MI, BB, 1);
892 case Mips::ATOMIC_CMP_SWAP_I16:
893 case Mips::ATOMIC_CMP_SWAP_I16_P8:
894 return EmitAtomicCmpSwapPartword(MI, BB, 2);
895 case Mips::ATOMIC_CMP_SWAP_I32:
896 case Mips::ATOMIC_CMP_SWAP_I32_P8:
897 return EmitAtomicCmpSwap(MI, BB, 4);
898 case Mips::ATOMIC_CMP_SWAP_I64:
899 case Mips::ATOMIC_CMP_SWAP_I64_P8:
900 return EmitAtomicCmpSwap(MI, BB, 8);
904 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
905 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
907 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
908 unsigned Size, unsigned BinOpcode,
910 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
912 MachineFunction *MF = BB->getParent();
913 MachineRegisterInfo &RegInfo = MF->getRegInfo();
914 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
915 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
916 DebugLoc dl = MI->getDebugLoc();
917 unsigned LL, SC, AND, NOR, ZERO, BEQ;
920 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
921 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
928 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
929 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
932 ZERO = Mips::ZERO_64;
936 unsigned OldVal = MI->getOperand(0).getReg();
937 unsigned Ptr = MI->getOperand(1).getReg();
938 unsigned Incr = MI->getOperand(2).getReg();
940 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
941 unsigned AndRes = RegInfo.createVirtualRegister(RC);
942 unsigned Success = RegInfo.createVirtualRegister(RC);
944 // insert new blocks after the current block
945 const BasicBlock *LLVM_BB = BB->getBasicBlock();
946 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
947 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
948 MachineFunction::iterator It = BB;
950 MF->insert(It, loopMBB);
951 MF->insert(It, exitMBB);
953 // Transfer the remainder of BB and its successor edges to exitMBB.
954 exitMBB->splice(exitMBB->begin(), BB,
955 llvm::next(MachineBasicBlock::iterator(MI)),
957 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
961 // fallthrough --> loopMBB
962 BB->addSuccessor(loopMBB);
963 loopMBB->addSuccessor(loopMBB);
964 loopMBB->addSuccessor(exitMBB);
968 // <binop> storeval, oldval, incr
969 // sc success, storeval, 0(ptr)
970 // beq success, $0, loopMBB
972 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
974 // and andres, oldval, incr
975 // nor storeval, $0, andres
976 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
977 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
978 } else if (BinOpcode) {
979 // <binop> storeval, oldval, incr
980 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
984 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
985 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
987 MI->eraseFromParent(); // The instruction is gone now.
993 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
994 MachineBasicBlock *BB,
995 unsigned Size, unsigned BinOpcode,
997 assert((Size == 1 || Size == 2) &&
998 "Unsupported size for EmitAtomicBinaryPartial.");
1000 MachineFunction *MF = BB->getParent();
1001 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1002 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1003 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1004 DebugLoc dl = MI->getDebugLoc();
1005 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1006 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1008 unsigned Dest = MI->getOperand(0).getReg();
1009 unsigned Ptr = MI->getOperand(1).getReg();
1010 unsigned Incr = MI->getOperand(2).getReg();
1012 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1013 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1014 unsigned Mask = RegInfo.createVirtualRegister(RC);
1015 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1016 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1017 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1018 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1019 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1020 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1021 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1022 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1023 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1024 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1025 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1026 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1027 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1028 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1029 unsigned Success = RegInfo.createVirtualRegister(RC);
1031 // insert new blocks after the current block
1032 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1033 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1034 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1035 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1036 MachineFunction::iterator It = BB;
1038 MF->insert(It, loopMBB);
1039 MF->insert(It, sinkMBB);
1040 MF->insert(It, exitMBB);
1042 // Transfer the remainder of BB and its successor edges to exitMBB.
1043 exitMBB->splice(exitMBB->begin(), BB,
1044 llvm::next(MachineBasicBlock::iterator(MI)),
1046 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1048 BB->addSuccessor(loopMBB);
1049 loopMBB->addSuccessor(loopMBB);
1050 loopMBB->addSuccessor(sinkMBB);
1051 sinkMBB->addSuccessor(exitMBB);
1054 // addiu masklsb2,$0,-4 # 0xfffffffc
1055 // and alignedaddr,ptr,masklsb2
1056 // andi ptrlsb2,ptr,3
1057 // sll shiftamt,ptrlsb2,3
1058 // ori maskupper,$0,255 # 0xff
1059 // sll mask,maskupper,shiftamt
1060 // nor mask2,$0,mask
1061 // sll incr2,incr,shiftamt
1063 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1064 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1065 .addReg(Mips::ZERO).addImm(-4);
1066 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1067 .addReg(Ptr).addReg(MaskLSB2);
1068 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1069 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1070 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1071 .addReg(Mips::ZERO).addImm(MaskImm);
1072 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1073 .addReg(ShiftAmt).addReg(MaskUpper);
1074 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1075 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1078 // atomic.load.binop
1080 // ll oldval,0(alignedaddr)
1081 // binop binopres,oldval,incr2
1082 // and newval,binopres,mask
1083 // and maskedoldval0,oldval,mask2
1084 // or storeval,maskedoldval0,newval
1085 // sc success,storeval,0(alignedaddr)
1086 // beq success,$0,loopMBB
1090 // ll oldval,0(alignedaddr)
1091 // and newval,incr2,mask
1092 // and maskedoldval0,oldval,mask2
1093 // or storeval,maskedoldval0,newval
1094 // sc success,storeval,0(alignedaddr)
1095 // beq success,$0,loopMBB
1098 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1100 // and andres, oldval, incr2
1101 // nor binopres, $0, andres
1102 // and newval, binopres, mask
1103 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1104 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1105 .addReg(Mips::ZERO).addReg(AndRes);
1106 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1107 } else if (BinOpcode) {
1108 // <binop> binopres, oldval, incr2
1109 // and newval, binopres, mask
1110 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1111 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1112 } else {// atomic.swap
1113 // and newval, incr2, mask
1114 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1117 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1118 .addReg(OldVal).addReg(Mask2);
1119 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1120 .addReg(MaskedOldVal0).addReg(NewVal);
1121 BuildMI(BB, dl, TII->get(SC), Success)
1122 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1123 BuildMI(BB, dl, TII->get(Mips::BEQ))
1124 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1127 // and maskedoldval1,oldval,mask
1128 // srl srlres,maskedoldval1,shiftamt
1129 // sll sllres,srlres,24
1130 // sra dest,sllres,24
1132 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1134 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1135 .addReg(OldVal).addReg(Mask);
1136 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1137 .addReg(ShiftAmt).addReg(MaskedOldVal1);
1138 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1139 .addReg(SrlRes).addImm(ShiftImm);
1140 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1141 .addReg(SllRes).addImm(ShiftImm);
1143 MI->eraseFromParent(); // The instruction is gone now.
1149 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1150 MachineBasicBlock *BB,
1151 unsigned Size) const {
1152 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1154 MachineFunction *MF = BB->getParent();
1155 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1156 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1157 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1158 DebugLoc dl = MI->getDebugLoc();
1159 unsigned LL, SC, ZERO, BNE, BEQ;
1162 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1163 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1169 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1170 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1171 ZERO = Mips::ZERO_64;
1176 unsigned Dest = MI->getOperand(0).getReg();
1177 unsigned Ptr = MI->getOperand(1).getReg();
1178 unsigned OldVal = MI->getOperand(2).getReg();
1179 unsigned NewVal = MI->getOperand(3).getReg();
1181 unsigned Success = RegInfo.createVirtualRegister(RC);
1183 // insert new blocks after the current block
1184 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1185 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1186 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1187 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1188 MachineFunction::iterator It = BB;
1190 MF->insert(It, loop1MBB);
1191 MF->insert(It, loop2MBB);
1192 MF->insert(It, exitMBB);
1194 // Transfer the remainder of BB and its successor edges to exitMBB.
1195 exitMBB->splice(exitMBB->begin(), BB,
1196 llvm::next(MachineBasicBlock::iterator(MI)),
1198 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1202 // fallthrough --> loop1MBB
1203 BB->addSuccessor(loop1MBB);
1204 loop1MBB->addSuccessor(exitMBB);
1205 loop1MBB->addSuccessor(loop2MBB);
1206 loop2MBB->addSuccessor(loop1MBB);
1207 loop2MBB->addSuccessor(exitMBB);
1211 // bne dest, oldval, exitMBB
1213 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1214 BuildMI(BB, dl, TII->get(BNE))
1215 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1218 // sc success, newval, 0(ptr)
1219 // beq success, $0, loop1MBB
1221 BuildMI(BB, dl, TII->get(SC), Success)
1222 .addReg(NewVal).addReg(Ptr).addImm(0);
1223 BuildMI(BB, dl, TII->get(BEQ))
1224 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1226 MI->eraseFromParent(); // The instruction is gone now.
1232 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1233 MachineBasicBlock *BB,
1234 unsigned Size) const {
1235 assert((Size == 1 || Size == 2) &&
1236 "Unsupported size for EmitAtomicCmpSwapPartial.");
1238 MachineFunction *MF = BB->getParent();
1239 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1240 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1241 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1242 DebugLoc dl = MI->getDebugLoc();
1243 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1244 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1246 unsigned Dest = MI->getOperand(0).getReg();
1247 unsigned Ptr = MI->getOperand(1).getReg();
1248 unsigned CmpVal = MI->getOperand(2).getReg();
1249 unsigned NewVal = MI->getOperand(3).getReg();
1251 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1252 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1253 unsigned Mask = RegInfo.createVirtualRegister(RC);
1254 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1255 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1256 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1257 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1258 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1259 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1260 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1261 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1262 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1263 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1264 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1265 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1266 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1267 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1268 unsigned Success = RegInfo.createVirtualRegister(RC);
1270 // insert new blocks after the current block
1271 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1272 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1273 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1274 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1275 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1276 MachineFunction::iterator It = BB;
1278 MF->insert(It, loop1MBB);
1279 MF->insert(It, loop2MBB);
1280 MF->insert(It, sinkMBB);
1281 MF->insert(It, exitMBB);
1283 // Transfer the remainder of BB and its successor edges to exitMBB.
1284 exitMBB->splice(exitMBB->begin(), BB,
1285 llvm::next(MachineBasicBlock::iterator(MI)),
1287 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1289 BB->addSuccessor(loop1MBB);
1290 loop1MBB->addSuccessor(sinkMBB);
1291 loop1MBB->addSuccessor(loop2MBB);
1292 loop2MBB->addSuccessor(loop1MBB);
1293 loop2MBB->addSuccessor(sinkMBB);
1294 sinkMBB->addSuccessor(exitMBB);
1296 // FIXME: computation of newval2 can be moved to loop2MBB.
1298 // addiu masklsb2,$0,-4 # 0xfffffffc
1299 // and alignedaddr,ptr,masklsb2
1300 // andi ptrlsb2,ptr,3
1301 // sll shiftamt,ptrlsb2,3
1302 // ori maskupper,$0,255 # 0xff
1303 // sll mask,maskupper,shiftamt
1304 // nor mask2,$0,mask
1305 // andi maskedcmpval,cmpval,255
1306 // sll shiftedcmpval,maskedcmpval,shiftamt
1307 // andi maskednewval,newval,255
1308 // sll shiftednewval,maskednewval,shiftamt
1309 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1310 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1311 .addReg(Mips::ZERO).addImm(-4);
1312 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1313 .addReg(Ptr).addReg(MaskLSB2);
1314 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1315 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1316 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1317 .addReg(Mips::ZERO).addImm(MaskImm);
1318 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1319 .addReg(ShiftAmt).addReg(MaskUpper);
1320 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1321 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1322 .addReg(CmpVal).addImm(MaskImm);
1323 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1324 .addReg(ShiftAmt).addReg(MaskedCmpVal);
1325 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1326 .addReg(NewVal).addImm(MaskImm);
1327 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1328 .addReg(ShiftAmt).addReg(MaskedNewVal);
1331 // ll oldval,0(alginedaddr)
1332 // and maskedoldval0,oldval,mask
1333 // bne maskedoldval0,shiftedcmpval,sinkMBB
1335 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1336 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1337 .addReg(OldVal).addReg(Mask);
1338 BuildMI(BB, dl, TII->get(Mips::BNE))
1339 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1342 // and maskedoldval1,oldval,mask2
1343 // or storeval,maskedoldval1,shiftednewval
1344 // sc success,storeval,0(alignedaddr)
1345 // beq success,$0,loop1MBB
1347 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1348 .addReg(OldVal).addReg(Mask2);
1349 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1350 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1351 BuildMI(BB, dl, TII->get(SC), Success)
1352 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1353 BuildMI(BB, dl, TII->get(Mips::BEQ))
1354 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1357 // srl srlres,maskedoldval0,shiftamt
1358 // sll sllres,srlres,24
1359 // sra dest,sllres,24
1361 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1363 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1364 .addReg(ShiftAmt).addReg(MaskedOldVal0);
1365 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1366 .addReg(SrlRes).addImm(ShiftImm);
1367 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1368 .addReg(SllRes).addImm(ShiftImm);
1370 MI->eraseFromParent(); // The instruction is gone now.
1375 //===----------------------------------------------------------------------===//
1376 // Misc Lower Operation implementation
1377 //===----------------------------------------------------------------------===//
1378 SDValue MipsTargetLowering::
1379 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
1381 MachineFunction &MF = DAG.getMachineFunction();
1382 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1383 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP;
1385 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
1386 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1387 "Cannot lower if the alignment of the allocated space is larger than \
1388 that of the stack.");
1390 SDValue Chain = Op.getOperand(0);
1391 SDValue Size = Op.getOperand(1);
1392 DebugLoc dl = Op.getDebugLoc();
1394 // Get a reference from Mips stack pointer
1395 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy());
1397 // Subtract the dynamic size from the actual stack size to
1398 // obtain the new stack size.
1399 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size);
1401 // The Sub result contains the new stack start address, so it
1402 // must be placed in the stack pointer register.
1403 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue());
1405 // This node always has two return values: a new stack pointer
1406 // value and a chain
1407 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other);
1408 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1409 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1411 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
1414 SDValue MipsTargetLowering::
1415 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1417 // The first operand is the chain, the second is the condition, the third is
1418 // the block to branch to if the condition is true.
1419 SDValue Chain = Op.getOperand(0);
1420 SDValue Dest = Op.getOperand(2);
1421 DebugLoc dl = Op.getDebugLoc();
1423 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1425 // Return if flag is not set by a floating point comparison.
1426 if (CondRes.getOpcode() != MipsISD::FPCmp)
1429 SDValue CCNode = CondRes.getOperand(2);
1431 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1432 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
1434 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
1438 SDValue MipsTargetLowering::
1439 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
1441 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
1443 // Return if flag is not set by a floating point comparison.
1444 if (Cond.getOpcode() != MipsISD::FPCmp)
1447 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1451 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1452 SelectionDAG &DAG) const {
1453 // FIXME there isn't actually debug info here
1454 DebugLoc dl = Op.getDebugLoc();
1455 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1457 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1458 SDVTList VTs = DAG.getVTList(MVT::i32);
1460 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
1462 // %gp_rel relocation
1463 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1464 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1466 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1467 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1468 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
1470 // %hi/%lo relocation
1471 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1473 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1475 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1476 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1477 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1480 EVT ValTy = Op.getValueType();
1481 bool HasGotOfst = (GV->hasInternalLinkage() ||
1482 (GV->hasLocalLinkage() && !isa<Function>(GV)));
1483 unsigned GotFlag = IsN64 ?
1484 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
1486 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
1487 GA = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, GA);
1488 SDValue ResNode = DAG.getLoad(ValTy, dl,
1489 DAG.getEntryNode(), GA, MachinePointerInfo(),
1490 false, false, false, 0);
1491 // On functions and global targets not internal linked only
1492 // a load from got/GP is necessary for PIC to work.
1495 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
1496 IsN64 ? MipsII::MO_GOT_OFST :
1498 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1499 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
1502 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1503 SelectionDAG &DAG) const {
1504 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1505 // FIXME there isn't actually debug info here
1506 DebugLoc dl = Op.getDebugLoc();
1508 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1509 // %hi/%lo relocation
1510 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
1512 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
1514 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1515 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1516 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1519 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1521 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset);
1522 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
1524 SDValue Load = DAG.getLoad(MVT::i32, dl,
1525 DAG.getEntryNode(), BAGOTOffset,
1526 MachinePointerInfo(), false, false, false, 0);
1527 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
1528 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1531 SDValue MipsTargetLowering::
1532 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1534 // If the relocation model is PIC, use the General Dynamic TLS Model,
1535 // otherwise use the Initial Exec or Local Exec TLS Model.
1536 // TODO: implement Local Dynamic TLS model
1538 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1539 DebugLoc dl = GA->getDebugLoc();
1540 const GlobalValue *GV = GA->getGlobal();
1541 EVT PtrVT = getPointerTy();
1543 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1544 // General Dynamic TLS Model
1545 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
1546 0, MipsII::MO_TLSGD);
1547 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
1548 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
1549 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
1553 Entry.Node = Argument;
1554 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
1555 Args.push_back(Entry);
1556 std::pair<SDValue, SDValue> CallResult =
1557 LowerCallTo(DAG.getEntryNode(),
1558 (Type *) Type::getInt32Ty(*DAG.getContext()),
1559 false, false, false, false, 0, CallingConv::C, false, true,
1560 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
1563 return CallResult.first;
1567 if (GV->isDeclaration()) {
1568 // Initial Exec TLS Model
1569 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1570 MipsII::MO_GOTTPREL);
1571 Offset = DAG.getLoad(MVT::i32, dl,
1572 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1573 false, false, false, 0);
1575 // Local Exec TLS Model
1576 SDVTList VTs = DAG.getVTList(MVT::i32);
1577 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1578 MipsII::MO_TPREL_HI);
1579 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1580 MipsII::MO_TPREL_LO);
1581 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
1582 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
1583 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1586 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1587 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1590 SDValue MipsTargetLowering::
1591 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1595 // FIXME there isn't actually debug info here
1596 DebugLoc dl = Op.getDebugLoc();
1597 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1598 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
1600 EVT PtrVT = Op.getValueType();
1601 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1603 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
1606 SDValue Ops[] = { JTI };
1607 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
1608 } else {// Emit Load from Global Pointer
1609 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI);
1610 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
1611 MachinePointerInfo(),
1612 false, false, false, 0);
1615 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1617 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
1618 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1623 SDValue MipsTargetLowering::
1624 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1627 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1628 const Constant *C = N->getConstVal();
1629 // FIXME there isn't actually debug info here
1630 DebugLoc dl = Op.getDebugLoc();
1632 // gp_rel relocation
1633 // FIXME: we should reference the constant pool using small data sections,
1634 // but the asm printer currently doesn't support this feature without
1635 // hacking it. This feature should come soon so we can uncomment the
1637 //if (IsInSmallSection(C->getType())) {
1638 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1639 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1640 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1642 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
1643 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1644 N->getOffset(), MipsII::MO_ABS_HI);
1645 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1646 N->getOffset(), MipsII::MO_ABS_LO);
1647 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1648 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1649 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1651 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1652 N->getOffset(), MipsII::MO_GOT);
1653 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP);
1654 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
1655 CP, MachinePointerInfo::getConstantPool(),
1656 false, false, false, 0);
1657 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1658 N->getOffset(), MipsII::MO_ABS_LO);
1659 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1660 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
1666 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1667 MachineFunction &MF = DAG.getMachineFunction();
1668 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1670 DebugLoc dl = Op.getDebugLoc();
1671 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1674 // vastart just stores the address of the VarArgsFrameIndex slot into the
1675 // memory location argument.
1676 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1677 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1678 MachinePointerInfo(SV),
1682 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) {
1683 // FIXME: Use ext/ins instructions if target architecture is Mips32r2.
1684 DebugLoc dl = Op.getDebugLoc();
1685 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0));
1686 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1));
1687 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0,
1688 DAG.getConstant(0x7fffffff, MVT::i32));
1689 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1,
1690 DAG.getConstant(0x80000000, MVT::i32));
1691 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1692 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result);
1695 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) {
1697 // Use ext/ins instructions if target architecture is Mips32r2.
1698 // Eliminate redundant mfc1 and mtc1 instructions.
1699 unsigned LoIdx = 0, HiIdx = 1;
1702 std::swap(LoIdx, HiIdx);
1704 DebugLoc dl = Op.getDebugLoc();
1705 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1707 DAG.getConstant(LoIdx, MVT::i32));
1708 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1709 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32));
1710 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1711 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32));
1712 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0,
1713 DAG.getConstant(0x7fffffff, MVT::i32));
1714 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1,
1715 DAG.getConstant(0x80000000, MVT::i32));
1716 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1);
1719 std::swap(Word0, Word1);
1721 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1);
1724 SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
1726 EVT Ty = Op.getValueType();
1728 assert(Ty == MVT::f32 || Ty == MVT::f64);
1731 return LowerFCOPYSIGN32(Op, DAG);
1733 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle());
1736 SDValue MipsTargetLowering::
1737 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1739 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1740 "Frame address can only be determined for current frame.");
1742 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1743 MFI->setFrameAddressIsTaken(true);
1744 EVT VT = Op.getValueType();
1745 DebugLoc dl = Op.getDebugLoc();
1746 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1747 IsN64 ? Mips::FP_64 : Mips::FP, VT);
1751 // TODO: set SType according to the desired memory barrier behavior.
1752 SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op,
1753 SelectionDAG& DAG) const {
1755 DebugLoc dl = Op.getDebugLoc();
1756 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1757 DAG.getConstant(SType, MVT::i32));
1760 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1761 SelectionDAG& DAG) const {
1762 // FIXME: Need pseudo-fence for 'singlethread' fences
1763 // FIXME: Set SType for weaker fences where supported/appropriate.
1765 DebugLoc dl = Op.getDebugLoc();
1766 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1767 DAG.getConstant(SType, MVT::i32));
1770 //===----------------------------------------------------------------------===//
1771 // Calling Convention Implementation
1772 //===----------------------------------------------------------------------===//
1774 #include "MipsGenCallingConv.inc"
1776 //===----------------------------------------------------------------------===//
1777 // TODO: Implement a generic logic using tblgen that can support this.
1778 // Mips O32 ABI rules:
1780 // i32 - Passed in A0, A1, A2, A3 and stack
1781 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
1782 // an argument. Otherwise, passed in A1, A2, A3 and stack.
1783 // f64 - Only passed in two aliased f32 registers if no int reg has been used
1784 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
1785 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
1788 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
1789 //===----------------------------------------------------------------------===//
1791 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
1792 MVT LocVT, CCValAssign::LocInfo LocInfo,
1793 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1795 static const unsigned IntRegsSize=4, FloatRegsSize=2;
1797 static const unsigned IntRegs[] = {
1798 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1800 static const unsigned F32Regs[] = {
1801 Mips::F12, Mips::F14
1803 static const unsigned F64Regs[] = {
1808 if (ArgFlags.isByVal()) {
1809 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
1810 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
1811 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
1812 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
1813 r < std::min(IntRegsSize, NextReg); ++r)
1814 State.AllocateReg(IntRegs[r]);
1818 // Promote i8 and i16
1819 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1821 if (ArgFlags.isSExt())
1822 LocInfo = CCValAssign::SExt;
1823 else if (ArgFlags.isZExt())
1824 LocInfo = CCValAssign::ZExt;
1826 LocInfo = CCValAssign::AExt;
1831 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
1832 // is true: function is vararg, argument is 3rd or higher, there is previous
1833 // argument which is not f32 or f64.
1834 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
1835 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
1836 unsigned OrigAlign = ArgFlags.getOrigAlign();
1837 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
1839 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
1840 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1841 // If this is the first part of an i64 arg,
1842 // the allocated register must be either A0 or A2.
1843 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
1844 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1846 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
1847 // Allocate int register and shadow next int register. If first
1848 // available register is Mips::A1 or Mips::A3, shadow it too.
1849 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1850 if (Reg == Mips::A1 || Reg == Mips::A3)
1851 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1852 State.AllocateReg(IntRegs, IntRegsSize);
1854 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
1855 // we are guaranteed to find an available float register
1856 if (ValVT == MVT::f32) {
1857 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
1858 // Shadow int register
1859 State.AllocateReg(IntRegs, IntRegsSize);
1861 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
1862 // Shadow int registers
1863 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
1864 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
1865 State.AllocateReg(IntRegs, IntRegsSize);
1866 State.AllocateReg(IntRegs, IntRegsSize);
1869 llvm_unreachable("Cannot handle this ValVT.");
1871 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1872 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
1875 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1877 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1879 return false; // CC must always match
1882 //===----------------------------------------------------------------------===//
1883 // Call Calling Convention Implementation
1884 //===----------------------------------------------------------------------===//
1886 static const unsigned O32IntRegsSize = 4;
1888 static const unsigned O32IntRegs[] = {
1889 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1892 // Return next O32 integer argument register.
1893 static unsigned getNextIntArgReg(unsigned Reg) {
1894 assert((Reg == Mips::A0) || (Reg == Mips::A2));
1895 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
1898 // Write ByVal Arg to arg registers and stack.
1900 WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
1901 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
1902 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
1903 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
1904 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
1905 MVT PtrType, bool isLittle) {
1906 unsigned LocMemOffset = VA.getLocMemOffset();
1907 unsigned Offset = 0;
1908 uint32_t RemainingSize = Flags.getByValSize();
1909 unsigned ByValAlign = Flags.getByValAlign();
1911 // Copy the first 4 words of byval arg to registers A0 - A3.
1912 // FIXME: Use a stricter alignment if it enables better optimization in passes
1914 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
1915 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
1916 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1917 DAG.getConstant(Offset, MVT::i32));
1918 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
1919 MachinePointerInfo(),
1920 false, false, false, std::min(ByValAlign,
1922 MemOpChains.push_back(LoadVal.getValue(1));
1923 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
1924 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1927 if (RemainingSize == 0)
1930 // If there still is a register available for argument passing, write the
1931 // remaining part of the structure to it using subword loads and shifts.
1932 if (LocMemOffset < 4 * 4) {
1933 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
1934 "There must be one to three bytes remaining.");
1935 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
1936 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1937 DAG.getConstant(Offset, MVT::i32));
1938 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
1939 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
1940 LoadPtr, MachinePointerInfo(),
1941 MVT::getIntegerVT(LoadSize * 8), false,
1943 MemOpChains.push_back(LoadVal.getValue(1));
1945 // If target is big endian, shift it to the most significant half-word or
1948 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
1949 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
1952 RemainingSize -= LoadSize;
1954 // Read second subword if necessary.
1955 if (RemainingSize != 0) {
1956 assert(RemainingSize == 1 && "There must be one byte remaining.");
1957 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1958 DAG.getConstant(Offset, MVT::i32));
1959 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
1960 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
1961 LoadPtr, MachinePointerInfo(),
1962 MVT::i8, false, false, Alignment);
1963 MemOpChains.push_back(Subword.getValue(1));
1964 // Insert the loaded byte to LoadVal.
1965 // FIXME: Use INS if supported by target.
1966 unsigned ShiftAmt = isLittle ? 16 : 8;
1967 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
1968 DAG.getConstant(ShiftAmt, MVT::i32));
1969 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
1972 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
1973 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
1977 // Create a fixed object on stack at offset LocMemOffset and copy
1978 // remaining part of byval arg to it using memcpy.
1979 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
1980 DAG.getConstant(Offset, MVT::i32));
1981 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true);
1982 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
1983 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
1984 DAG.getConstant(RemainingSize, MVT::i32),
1985 std::min(ByValAlign, (unsigned)4),
1986 /*isVolatile=*/false, /*AlwaysInline=*/false,
1987 MachinePointerInfo(0), MachinePointerInfo(0));
1990 /// LowerCall - functions arguments are copied from virtual regs to
1991 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1992 /// TODO: isTailCall.
1994 MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
1995 CallingConv::ID CallConv, bool isVarArg,
1997 const SmallVectorImpl<ISD::OutputArg> &Outs,
1998 const SmallVectorImpl<SDValue> &OutVals,
1999 const SmallVectorImpl<ISD::InputArg> &Ins,
2000 DebugLoc dl, SelectionDAG &DAG,
2001 SmallVectorImpl<SDValue> &InVals) const {
2002 // MIPs target does not yet support tail call optimization.
2005 MachineFunction &MF = DAG.getMachineFunction();
2006 MachineFrameInfo *MFI = MF.getFrameInfo();
2007 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2008 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2009 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2011 // Analyze operands of the call, assigning locations to each operand.
2012 SmallVector<CCValAssign, 16> ArgLocs;
2013 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2014 getTargetMachine(), ArgLocs, *DAG.getContext());
2017 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
2019 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
2021 // Get a count of how many bytes are to be pushed on the stack.
2022 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2024 // Chain is the output chain of the last Load/Store or CopyToReg node.
2025 // ByValChain is the output chain of the last Memcpy node created for copying
2026 // byval arguments to the stack.
2027 SDValue Chain, CallSeqStart, ByValChain;
2028 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2029 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal);
2030 ByValChain = InChain;
2032 // If this is the first call, create a stack frame object that points to
2033 // a location to which .cprestore saves $gp.
2034 if (IsO32 && IsPIC && !MipsFI->getGPFI())
2035 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
2037 // Get the frame index of the stack frame object that points to the location
2038 // of dynamically allocated area on the stack.
2039 int DynAllocFI = MipsFI->getDynAllocFI();
2041 // Update size of the maximum argument space.
2042 // For O32, a minimum of four words (16 bytes) of argument space is
2045 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
2047 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
2049 if (MaxCallFrameSize < NextStackOffset) {
2050 MipsFI->setMaxCallFrameSize(NextStackOffset);
2052 // Set the offsets relative to $sp of the $gp restore slot and dynamically
2053 // allocated stack space. These offsets must be aligned to a boundary
2054 // determined by the stack alignment of the ABI.
2055 unsigned StackAlignment = TFL->getStackAlignment();
2056 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
2057 StackAlignment * StackAlignment;
2059 if (MipsFI->needGPSaveRestore())
2060 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
2062 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
2065 // With EABI is it possible to have 16 args on registers.
2066 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2067 SmallVector<SDValue, 8> MemOpChains;
2069 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
2071 // Walk the register/memloc assignments, inserting copies/loads.
2072 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2073 SDValue Arg = OutVals[i];
2074 CCValAssign &VA = ArgLocs[i];
2075 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2077 // Promote the value if needed.
2078 switch (VA.getLocInfo()) {
2079 default: llvm_unreachable("Unknown loc info!");
2080 case CCValAssign::Full:
2081 if (VA.isRegLoc()) {
2082 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2083 (ValVT == MVT::f64 && LocVT == MVT::i64))
2084 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2085 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2086 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2087 Arg, DAG.getConstant(0, MVT::i32));
2088 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2089 Arg, DAG.getConstant(1, MVT::i32));
2090 if (!Subtarget->isLittle())
2092 unsigned LocRegLo = VA.getLocReg();
2093 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2094 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2095 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2100 case CCValAssign::SExt:
2101 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
2103 case CCValAssign::ZExt:
2104 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
2106 case CCValAssign::AExt:
2107 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
2111 // Arguments that can be passed on register must be kept at
2112 // RegsToPass vector
2113 if (VA.isRegLoc()) {
2114 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2118 // Register can't get to this point...
2119 assert(VA.isMemLoc());
2122 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2123 if (Flags.isByVal()) {
2125 "No support for ByVal args by ABIs other than O32 yet.");
2126 assert(Flags.getByValSize() &&
2127 "ByVal args of size 0 should have been ignored by front-end.");
2128 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI,
2129 DAG, Arg, VA, Flags, getPointerTy(), Subtarget->isLittle());
2133 // Create the frame index object for this incoming parameter
2134 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2135 VA.getLocMemOffset(), true);
2136 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2138 // emit ISD::STORE whichs stores the
2139 // parameter value to a stack Location
2140 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2141 MachinePointerInfo(),
2145 // Extend range of indices of frame objects for outgoing arguments that were
2146 // created during this function call. Skip this step if no such objects were
2149 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
2151 // If a memcpy has been created to copy a byval arg to a stack, replace the
2152 // chain input of CallSeqStart with ByValChain.
2153 if (InChain != ByValChain)
2154 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain,
2155 NextStackOffsetVal);
2157 // Transform all store nodes into one single node because all store
2158 // nodes are independent of each other.
2159 if (!MemOpChains.empty())
2160 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2161 &MemOpChains[0], MemOpChains.size());
2163 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2164 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2165 // node so that legalize doesn't hack it.
2166 unsigned char OpFlag;
2167 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2168 bool LoadSymAddr = false;
2171 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2172 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2173 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2174 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2175 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2177 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
2180 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
2181 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2182 getPointerTy(), 0, OpFlag);
2187 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2188 if (IsN64 || (!IsO32 && IsPIC))
2189 OpFlag = MipsII::MO_GOT_DISP;
2190 else if (!IsPIC) // !N64 && static
2191 OpFlag = MipsII::MO_NO_FLAG;
2193 OpFlag = MipsII::MO_GOT_CALL;
2194 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
2195 getPointerTy(), OpFlag);
2201 // Create nodes that load address of callee and copy it to T9
2204 // Load callee address
2205 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, getPointerTy(), Callee);
2206 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2207 Callee, MachinePointerInfo::getGOT(),
2208 false, false, false, 0);
2210 // Use GOT+LO if callee has internal linkage.
2211 if (CalleeLo.getNode()) {
2212 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2213 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
2219 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2220 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
2221 InFlag = Chain.getValue(1);
2222 Callee = DAG.getRegister(T9Reg, getPointerTy());
2225 // Build a sequence of copy-to-reg nodes chained together with token
2226 // chain and flag operands which copy the outgoing args into registers.
2227 // The InFlag in necessary since all emitted instructions must be
2229 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2230 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2231 RegsToPass[i].second, InFlag);
2232 InFlag = Chain.getValue(1);
2235 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
2236 // = Chain, Callee, Reg#1, Reg#2, ...
2238 // Returns a chain & a flag for retval copy to use.
2239 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2240 SmallVector<SDValue, 8> Ops;
2241 Ops.push_back(Chain);
2242 Ops.push_back(Callee);
2244 // Add argument registers to the end of the list so that they are
2245 // known live into the call.
2246 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2247 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2248 RegsToPass[i].second.getValueType()));
2250 if (InFlag.getNode())
2251 Ops.push_back(InFlag);
2253 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
2254 InFlag = Chain.getValue(1);
2256 // Create the CALLSEQ_END node.
2257 Chain = DAG.getCALLSEQ_END(Chain,
2258 DAG.getIntPtrConstant(NextStackOffset, true),
2259 DAG.getIntPtrConstant(0, true), InFlag);
2260 InFlag = Chain.getValue(1);
2262 // Handle result values, copying them out of physregs into vregs that we
2264 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2265 Ins, dl, DAG, InVals);
2268 /// LowerCallResult - Lower the result values of a call into the
2269 /// appropriate copies out of appropriate physical registers.
2271 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2272 CallingConv::ID CallConv, bool isVarArg,
2273 const SmallVectorImpl<ISD::InputArg> &Ins,
2274 DebugLoc dl, SelectionDAG &DAG,
2275 SmallVectorImpl<SDValue> &InVals) const {
2276 // Assign locations to each value returned by this call.
2277 SmallVector<CCValAssign, 16> RVLocs;
2278 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2279 getTargetMachine(), RVLocs, *DAG.getContext());
2281 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
2283 // Copy all of the result registers out of their specified physreg.
2284 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2285 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
2286 RVLocs[i].getValVT(), InFlag).getValue(1);
2287 InFlag = Chain.getValue(2);
2288 InVals.push_back(Chain.getValue(0));
2294 //===----------------------------------------------------------------------===//
2295 // Formal Arguments Calling Convention Implementation
2296 //===----------------------------------------------------------------------===//
2297 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2298 std::vector<SDValue>& OutChains,
2299 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
2300 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) {
2301 unsigned LocMem = VA.getLocMemOffset();
2302 unsigned FirstWord = LocMem / 4;
2304 // copy register A0 - A3 to frame object
2305 for (unsigned i = 0; i < NumWords; ++i) {
2306 unsigned CurWord = FirstWord + i;
2307 if (CurWord >= O32IntRegsSize)
2310 unsigned SrcReg = O32IntRegs[CurWord];
2311 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass);
2312 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2313 DAG.getConstant(i * 4, MVT::i32));
2314 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
2315 StorePtr, MachinePointerInfo(), false,
2317 OutChains.push_back(Store);
2321 /// LowerFormalArguments - transform physical registers into virtual registers
2322 /// and generate load operations for arguments places on the stack.
2324 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2325 CallingConv::ID CallConv,
2327 const SmallVectorImpl<ISD::InputArg>
2329 DebugLoc dl, SelectionDAG &DAG,
2330 SmallVectorImpl<SDValue> &InVals)
2332 MachineFunction &MF = DAG.getMachineFunction();
2333 MachineFrameInfo *MFI = MF.getFrameInfo();
2334 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2336 MipsFI->setVarArgsFrameIndex(0);
2338 // Used with vargs to acumulate store chains.
2339 std::vector<SDValue> OutChains;
2341 // Assign locations to all of the incoming arguments.
2342 SmallVector<CCValAssign, 16> ArgLocs;
2343 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2344 getTargetMachine(), ArgLocs, *DAG.getContext());
2347 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
2349 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
2351 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
2353 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2354 CCValAssign &VA = ArgLocs[i];
2355 EVT ValVT = VA.getValVT();
2357 // Arguments stored on registers
2358 if (VA.isRegLoc()) {
2359 EVT RegVT = VA.getLocVT();
2360 unsigned ArgReg = VA.getLocReg();
2361 TargetRegisterClass *RC = 0;
2363 if (RegVT == MVT::i32)
2364 RC = Mips::CPURegsRegisterClass;
2365 else if (RegVT == MVT::i64)
2366 RC = Mips::CPU64RegsRegisterClass;
2367 else if (RegVT == MVT::f32)
2368 RC = Mips::FGR32RegisterClass;
2369 else if (RegVT == MVT::f64)
2370 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass;
2372 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2374 // Transform the arguments stored on
2375 // physical registers into virtual ones
2376 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2377 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2379 // If this is an 8 or 16-bit value, it has been passed promoted
2380 // to 32 bits. Insert an assert[sz]ext to capture this, then
2381 // truncate to the right size.
2382 if (VA.getLocInfo() != CCValAssign::Full) {
2383 unsigned Opcode = 0;
2384 if (VA.getLocInfo() == CCValAssign::SExt)
2385 Opcode = ISD::AssertSext;
2386 else if (VA.getLocInfo() == CCValAssign::ZExt)
2387 Opcode = ISD::AssertZext;
2389 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
2390 DAG.getValueType(ValVT));
2391 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
2394 // Handle floating point arguments passed in integer registers.
2395 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2396 (RegVT == MVT::i64 && ValVT == MVT::f64))
2397 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
2398 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2399 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
2400 getNextIntArgReg(ArgReg), RC);
2401 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
2402 if (!Subtarget->isLittle())
2403 std::swap(ArgValue, ArgValue2);
2404 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
2405 ArgValue, ArgValue2);
2408 InVals.push_back(ArgValue);
2409 } else { // VA.isRegLoc()
2412 assert(VA.isMemLoc());
2414 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2416 if (Flags.isByVal()) {
2418 "No support for ByVal args by ABIs other than O32 yet.");
2419 assert(Flags.getByValSize() &&
2420 "ByVal args of size 0 should have been ignored by front-end.");
2421 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
2422 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
2424 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2425 InVals.push_back(FIN);
2426 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags);
2431 // The stack pointer offset is relative to the caller stack frame.
2432 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2433 VA.getLocMemOffset(), true);
2435 // Create load nodes to retrieve arguments from the stack
2436 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2437 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
2438 MachinePointerInfo::getFixedStack(LastFI),
2439 false, false, false, 0));
2443 // The mips ABIs for returning structs by value requires that we copy
2444 // the sret argument into $v0 for the return. Save the argument into
2445 // a virtual register so that we can access it from the return points.
2446 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2447 unsigned Reg = MipsFI->getSRetReturnReg();
2449 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
2450 MipsFI->setSRetReturnReg(Reg);
2452 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2453 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2456 if (isVarArg && IsO32) {
2457 // Record the frame index of the first variable argument
2458 // which is a value necessary to VASTART.
2459 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2460 assert(NextStackOffset % 4 == 0 &&
2461 "NextStackOffset must be aligned to 4-byte boundaries.");
2462 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2463 MipsFI->setVarArgsFrameIndex(LastFI);
2465 // If NextStackOffset is smaller than o32's 16-byte reserved argument area,
2466 // copy the integer registers that have not been used for argument passing
2467 // to the caller's stack frame.
2468 for (; NextStackOffset < 16; NextStackOffset += 4) {
2469 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
2470 unsigned Idx = NextStackOffset / 4;
2471 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC);
2472 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
2473 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
2474 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2475 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
2476 MachinePointerInfo(),
2481 MipsFI->setLastInArgFI(LastFI);
2483 // All stores are grouped in one node to allow the matching between
2484 // the size of Ins and InVals. This only happens when on varg functions
2485 if (!OutChains.empty()) {
2486 OutChains.push_back(Chain);
2487 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2488 &OutChains[0], OutChains.size());
2494 //===----------------------------------------------------------------------===//
2495 // Return Value Calling Convention Implementation
2496 //===----------------------------------------------------------------------===//
2499 MipsTargetLowering::LowerReturn(SDValue Chain,
2500 CallingConv::ID CallConv, bool isVarArg,
2501 const SmallVectorImpl<ISD::OutputArg> &Outs,
2502 const SmallVectorImpl<SDValue> &OutVals,
2503 DebugLoc dl, SelectionDAG &DAG) const {
2505 // CCValAssign - represent the assignment of
2506 // the return value to a location
2507 SmallVector<CCValAssign, 16> RVLocs;
2509 // CCState - Info about the registers and stack slot.
2510 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2511 getTargetMachine(), RVLocs, *DAG.getContext());
2513 // Analize return values.
2514 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
2516 // If this is the first return lowered for this function, add
2517 // the regs to the liveout set for the function.
2518 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2519 for (unsigned i = 0; i != RVLocs.size(); ++i)
2520 if (RVLocs[i].isRegLoc())
2521 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2526 // Copy the result values into the output registers.
2527 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2528 CCValAssign &VA = RVLocs[i];
2529 assert(VA.isRegLoc() && "Can only return in registers!");
2531 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2534 // guarantee that all emitted copies are
2535 // stuck together, avoiding something bad
2536 Flag = Chain.getValue(1);
2539 // The mips ABIs for returning structs by value requires that we copy
2540 // the sret argument into $v0 for the return. We saved the argument into
2541 // a virtual register in the entry block, so now we copy the value out
2543 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2544 MachineFunction &MF = DAG.getMachineFunction();
2545 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2546 unsigned Reg = MipsFI->getSRetReturnReg();
2549 llvm_unreachable("sret virtual register not created in the entry block");
2550 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2552 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
2553 Flag = Chain.getValue(1);
2556 // Return on Mips is always a "jr $ra"
2558 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
2559 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
2561 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
2562 Chain, DAG.getRegister(Mips::RA, MVT::i32));
2565 //===----------------------------------------------------------------------===//
2566 // Mips Inline Assembly Support
2567 //===----------------------------------------------------------------------===//
2569 /// getConstraintType - Given a constraint letter, return the type of
2570 /// constraint it is for this target.
2571 MipsTargetLowering::ConstraintType MipsTargetLowering::
2572 getConstraintType(const std::string &Constraint) const
2574 // Mips specific constrainy
2575 // GCC config/mips/constraints.md
2577 // 'd' : An address register. Equivalent to r
2578 // unless generating MIPS16 code.
2579 // 'y' : Equivalent to r; retained for
2580 // backwards compatibility.
2581 // 'f' : Floating Point registers.
2582 if (Constraint.size() == 1) {
2583 switch (Constraint[0]) {
2588 return C_RegisterClass;
2592 return TargetLowering::getConstraintType(Constraint);
2595 /// Examine constraint type and operand type and determine a weight value.
2596 /// This object must already have been set up with the operand type
2597 /// and the current alternative constraint selected.
2598 TargetLowering::ConstraintWeight
2599 MipsTargetLowering::getSingleConstraintMatchWeight(
2600 AsmOperandInfo &info, const char *constraint) const {
2601 ConstraintWeight weight = CW_Invalid;
2602 Value *CallOperandVal = info.CallOperandVal;
2603 // If we don't have a value, we can't do a match,
2604 // but allow it at the lowest weight.
2605 if (CallOperandVal == NULL)
2607 Type *type = CallOperandVal->getType();
2608 // Look at the constraint type.
2609 switch (*constraint) {
2611 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2615 if (type->isIntegerTy())
2616 weight = CW_Register;
2619 if (type->isFloatTy())
2620 weight = CW_Register;
2626 /// Given a register class constraint, like 'r', if this corresponds directly
2627 /// to an LLVM register class, return a register of 0 and the register class
2629 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2630 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
2632 if (Constraint.size() == 1) {
2633 switch (Constraint[0]) {
2634 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2635 case 'y': // Same as 'r'. Exists for compatibility.
2637 return std::make_pair(0U, Mips::CPURegsRegisterClass);
2640 return std::make_pair(0U, Mips::FGR32RegisterClass);
2642 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
2643 return std::make_pair(0U, Mips::AFGR64RegisterClass);
2647 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2651 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2652 // The Mips target isn't yet aware of offsets.
2656 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2657 if (VT != MVT::f32 && VT != MVT::f64)
2659 if (Imm.isNegZero())
2661 return Imm.isZero();