1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::SelectCC : return "MipsISD::SelectCC";
50 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
51 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
52 case MipsISD::FPCmp : return "MipsISD::FPCmp";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setSetCCResultContents(ZeroOrOneSetCCResult);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat()) {
74 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
81 addLegalFPImmediate(APFloat(+0.0f));
83 // Load extented operations for i1 types must be promoted
84 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
85 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
86 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 // Used by legalize types to correctly generate the setcc result.
89 // Without this, every float setcc comes with a AND/OR with the result,
90 // we don't want this, since the fpcmp result goes to a flag register,
91 // which is used implicitly by brcond and select operations.
92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
94 // Mips Custom Operations
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
97 setOperationAction(ISD::RET, MVT::Other, Custom);
98 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
99 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
100 setOperationAction(ISD::SELECT, MVT::f32, Custom);
101 setOperationAction(ISD::SELECT, MVT::i32, Custom);
102 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
103 setOperationAction(ISD::SETCC, MVT::f32, Custom);
104 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
105 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
107 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
108 // with operands comming from setcc fp comparions. This is necessary since
109 // the result from these setcc are in a flag registers (FCR31).
110 setOperationAction(ISD::AND, MVT::i32, Custom);
111 setOperationAction(ISD::OR, MVT::i32, Custom);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
123 setOperationAction(ISD::ROTL, MVT::i32, Expand);
124 setOperationAction(ISD::ROTR, MVT::i32, Expand);
125 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
126 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
127 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
129 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
131 // We don't have line number support yet.
132 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
133 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
134 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
135 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
137 // Use the default for now
138 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
139 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
140 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
142 if (Subtarget->isSingleFloat())
143 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
145 if (!Subtarget->hasSEInReg()) {
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
150 setStackPointerRegisterToSaveRestore(Mips::SP);
151 computeRegisterProperties();
155 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
160 SDValue MipsTargetLowering::
161 LowerOperation(SDValue Op, SelectionDAG &DAG)
163 switch (Op.getOpcode())
165 case ISD::AND: return LowerANDOR(Op, DAG);
166 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
167 case ISD::CALL: return LowerCALL(Op, DAG);
168 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
169 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
170 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
171 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
172 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
173 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
174 case ISD::OR: return LowerANDOR(Op, DAG);
175 case ISD::RET: return LowerRET(Op, DAG);
176 case ISD::SELECT: return LowerSELECT(Op, DAG);
177 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
178 case ISD::SETCC: return LowerSETCC(Op, DAG);
183 //===----------------------------------------------------------------------===//
184 // Lower helper functions
185 //===----------------------------------------------------------------------===//
187 // AddLiveIn - This helper function adds the specified physical register to the
188 // MachineFunction as a live in value. It also creates a corresponding
189 // virtual register for it.
191 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
193 assert(RC->contains(PReg) && "Not the correct regclass!");
194 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
195 MF.getRegInfo().addLiveIn(PReg, VReg);
199 // A address must be loaded from a small section if its size is less than the
200 // small section size threshold. Data in this section must be addressed using
202 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
203 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
206 // Discover if this global address can be placed into small data/bss section.
207 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
209 const TargetData *TD = getTargetData();
210 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
215 const Type *Ty = GV->getType()->getElementType();
216 unsigned Size = TD->getABITypeSize(Ty);
218 // if this is a internal constant string, there is a special
219 // section for it, but not in small data/bss.
220 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
221 Constant *C = GVA->getInitializer();
222 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
223 if (CVA && CVA->isCString())
227 return IsInSmallSection(Size);
230 // Get fp branch code (not opcode) from condition code.
231 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
232 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
233 return Mips::BRANCH_T;
235 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
236 return Mips::BRANCH_F;
238 return Mips::BRANCH_INVALID;
241 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
244 assert(0 && "Unknown branch code");
245 case Mips::BRANCH_T : return Mips::BC1T;
246 case Mips::BRANCH_F : return Mips::BC1F;
247 case Mips::BRANCH_TL : return Mips::BC1TL;
248 case Mips::BRANCH_FL : return Mips::BC1FL;
252 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
254 default: assert(0 && "Unknown fp condition code!");
256 case ISD::SETOEQ: return Mips::FCOND_EQ;
257 case ISD::SETUNE: return Mips::FCOND_OGL;
259 case ISD::SETOLT: return Mips::FCOND_OLT;
261 case ISD::SETOGT: return Mips::FCOND_OGT;
263 case ISD::SETOLE: return Mips::FCOND_OLE;
265 case ISD::SETOGE: return Mips::FCOND_OGE;
266 case ISD::SETULT: return Mips::FCOND_ULT;
267 case ISD::SETULE: return Mips::FCOND_ULE;
268 case ISD::SETUGT: return Mips::FCOND_UGT;
269 case ISD::SETUGE: return Mips::FCOND_UGE;
270 case ISD::SETUO: return Mips::FCOND_UN;
271 case ISD::SETO: return Mips::FCOND_OR;
273 case ISD::SETONE: return Mips::FCOND_NEQ;
274 case ISD::SETUEQ: return Mips::FCOND_UEQ;
279 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
280 MachineBasicBlock *BB)
282 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
283 bool isFPCmp = false;
285 switch (MI->getOpcode()) {
286 default: assert(false && "Unexpected instr type to insert");
287 case Mips::Select_FCC:
288 case Mips::Select_FCC_SO32:
289 case Mips::Select_FCC_AS32:
290 case Mips::Select_FCC_D32:
291 isFPCmp = true; // FALL THROUGH
292 case Mips::Select_CC:
293 case Mips::Select_CC_SO32:
294 case Mips::Select_CC_AS32:
295 case Mips::Select_CC_D32: {
296 // To "insert" a SELECT_CC instruction, we actually have to insert the
297 // diamond control-flow pattern. The incoming instruction knows the
298 // destination vreg to set, the condition code register to branch on, the
299 // true/false values to select between, and a branch opcode to use.
300 const BasicBlock *LLVM_BB = BB->getBasicBlock();
301 MachineFunction::iterator It = BB;
308 // bNE r1, r0, copy1MBB
309 // fallthrough --> copy0MBB
310 MachineBasicBlock *thisMBB = BB;
311 MachineFunction *F = BB->getParent();
312 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
313 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
315 // Emit the right instruction according to the type of the operands compared
317 // Find the condiction code present in the setcc operation.
318 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
319 // Get the branch opcode from the branch code.
320 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
321 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
323 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
324 .addReg(Mips::ZERO).addMBB(sinkMBB);
326 F->insert(It, copy0MBB);
327 F->insert(It, sinkMBB);
328 // Update machine-CFG edges by first adding all successors of the current
329 // block to the new block which will contain the Phi node for the select.
330 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
331 e = BB->succ_end(); i != e; ++i)
332 sinkMBB->addSuccessor(*i);
333 // Next, remove all successors of the current block, and add the true
334 // and fallthrough blocks as its successors.
335 while(!BB->succ_empty())
336 BB->removeSuccessor(BB->succ_begin());
337 BB->addSuccessor(copy0MBB);
338 BB->addSuccessor(sinkMBB);
342 // # fallthrough to sinkMBB
345 // Update machine-CFG edges
346 BB->addSuccessor(sinkMBB);
349 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
352 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
353 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
354 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
356 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
362 //===----------------------------------------------------------------------===//
363 // Misc Lower Operation implementation
364 //===----------------------------------------------------------------------===//
366 SDValue MipsTargetLowering::
367 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
369 SDValue Chain = Op.getOperand(0);
370 SDValue Size = Op.getOperand(1);
372 // Get a reference from Mips stack pointer
373 SDValue StackPointer = DAG.getCopyFromReg(Chain, Mips::SP, MVT::i32);
375 // Subtract the dynamic size from the actual stack size to
376 // obtain the new stack size.
377 SDValue Sub = DAG.getNode(ISD::SUB, MVT::i32, StackPointer, Size);
379 // The Sub result contains the new stack start address, so it
380 // must be placed in the stack pointer register.
381 Chain = DAG.getCopyToReg(StackPointer.getValue(1), Mips::SP, Sub);
383 // This node always has two return values: a new stack pointer
385 SDValue Ops[2] = { Sub, Chain };
386 return DAG.getMergeValues(Ops, 2);
389 SDValue MipsTargetLowering::
390 LowerANDOR(SDValue Op, SelectionDAG &DAG)
392 SDValue LHS = Op.getOperand(0);
393 SDValue RHS = Op.getOperand(1);
395 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
398 SDValue True = DAG.getConstant(1, MVT::i32);
399 SDValue False = DAG.getConstant(0, MVT::i32);
401 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
402 LHS, True, False, LHS.getOperand(2));
403 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
404 RHS, True, False, RHS.getOperand(2));
406 return DAG.getNode(Op.getOpcode(), MVT::i32, LSEL, RSEL);
409 SDValue MipsTargetLowering::
410 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
412 // The first operand is the chain, the second is the condition, the third is
413 // the block to branch to if the condition is true.
414 SDValue Chain = Op.getOperand(0);
415 SDValue Dest = Op.getOperand(2);
417 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
420 SDValue CondRes = Op.getOperand(1);
421 SDValue CCNode = CondRes.getOperand(2);
422 Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue();
423 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
425 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
429 SDValue MipsTargetLowering::
430 LowerSETCC(SDValue Op, SelectionDAG &DAG)
432 // The operands to this are the left and right operands to compare (ops #0,
433 // and #1) and the condition code to compare them with (op #2) as a
435 SDValue LHS = Op.getOperand(0);
436 SDValue RHS = Op.getOperand(1);
438 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
440 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
441 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
444 SDValue MipsTargetLowering::
445 LowerSELECT(SDValue Op, SelectionDAG &DAG)
447 SDValue Cond = Op.getOperand(0);
448 SDValue True = Op.getOperand(1);
449 SDValue False = Op.getOperand(2);
451 // if the incomming condition comes from fpcmp, the select
452 // operation must use FPSelectCC, otherwise SelectCC.
453 if (Cond.getOpcode() != MipsISD::FPCmp)
454 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
457 SDValue CCNode = Cond.getOperand(2);
458 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
459 Cond, True, False, CCNode);
462 SDValue MipsTargetLowering::
463 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
465 SDValue LHS = Op.getOperand(0);
466 SDValue RHS = Op.getOperand(1);
467 SDValue True = Op.getOperand(2);
468 SDValue False = Op.getOperand(3);
469 SDValue CC = Op.getOperand(4);
471 SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC);
472 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
473 SetCCRes, True, False);
476 SDValue MipsTargetLowering::
477 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
479 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
480 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
482 if (!Subtarget->hasABICall()) {
483 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
484 SDValue Ops[] = { GA };
485 // %gp_rel relocation
486 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
487 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
488 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
489 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
491 // %hi/%lo relocation
492 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
493 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
494 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
496 } else { // Abicall relocations, TODO: make this cleaner.
497 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
498 // On functions and global targets not internal linked only
499 // a load from got/GP is necessary for PIC to work.
500 if (!GV->hasInternalLinkage() || isa<Function>(GV))
502 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
503 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
506 assert(0 && "Dont know how to handle GlobalAddress");
510 SDValue MipsTargetLowering::
511 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
513 assert(0 && "TLS not implemented for MIPS.");
514 return SDValue(); // Not reached
517 SDValue MipsTargetLowering::
518 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
523 MVT PtrVT = Op.getValueType();
524 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
525 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
527 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
528 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
529 SDValue Ops[] = { JTI };
530 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
531 } else // Emit Load from Global Pointer
532 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
534 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
535 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
540 SDValue MipsTargetLowering::
541 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
544 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
545 Constant *C = N->getConstVal();
546 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
549 // FIXME: we should reference the constant pool using small data sections,
550 // but the asm printer currently doens't support this feature without
551 // hacking it. This feature should come soon so we can uncomment the
553 //if (!Subtarget->hasABICall() &&
554 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
555 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
556 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
557 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
558 //} else { // %hi/%lo relocation
559 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
560 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
561 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
567 //===----------------------------------------------------------------------===//
568 // Calling Convention Implementation
570 // The lower operations present on calling convention works on this order:
571 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
572 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
573 // LowerRET (virt regs --> phys regs)
574 // LowerCALL (phys regs --> virt regs)
576 //===----------------------------------------------------------------------===//
578 #include "MipsGenCallingConv.inc"
580 //===----------------------------------------------------------------------===//
581 // CALL Calling Convention Implementation
582 //===----------------------------------------------------------------------===//
584 /// LowerCCCCallTo - functions arguments are copied from virtual
585 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
586 /// CALLSEQ_END are emitted.
587 /// TODO: isVarArg, isTailCall.
588 SDValue MipsTargetLowering::
589 LowerCALL(SDValue Op, SelectionDAG &DAG)
591 MachineFunction &MF = DAG.getMachineFunction();
593 SDValue Chain = Op.getOperand(0);
594 SDValue Callee = Op.getOperand(4);
595 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
596 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
598 MachineFrameInfo *MFI = MF.getFrameInfo();
600 // Analyze operands of the call, assigning locations to each operand.
601 SmallVector<CCValAssign, 16> ArgLocs;
602 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
604 // To meet O32 ABI, Mips must always allocate 16 bytes on
605 // the stack (even if less than 4 are used as arguments)
606 if (Subtarget->isABI_O32()) {
607 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
608 MFI->CreateFixedObject(VTsize, (VTsize*3));
611 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
613 // Get a count of how many bytes are to be pushed on the stack.
614 unsigned NumBytes = CCInfo.getNextStackOffset();
615 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
618 // With EABI is it possible to have 16 args on registers.
619 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
620 SmallVector<SDValue, 8> MemOpChains;
622 // First/LastArgStackLoc contains the first/last
623 // "at stack" argument location.
624 int LastArgStackLoc = 0;
625 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
627 // Walk the register/memloc assignments, inserting copies/loads.
628 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
629 CCValAssign &VA = ArgLocs[i];
631 // Arguments start after the 5 first operands of ISD::CALL
632 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
634 // Promote the value if needed.
635 switch (VA.getLocInfo()) {
636 default: assert(0 && "Unknown loc info!");
637 case CCValAssign::Full: break;
638 case CCValAssign::SExt:
639 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
641 case CCValAssign::ZExt:
642 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
644 case CCValAssign::AExt:
645 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
649 // Arguments that can be passed on register must be kept at
652 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
656 // Register cant get to this point...
657 assert(VA.isMemLoc());
659 // Create the frame index object for this incoming parameter
660 // This guarantees that when allocating Local Area the firsts
661 // 16 bytes which are alwayes reserved won't be overwritten
662 // if O32 ABI is used. For EABI the first address is zero.
663 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
664 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
667 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
669 // emit ISD::STORE whichs stores the
670 // parameter value to a stack Location
671 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
674 // Transform all store nodes into one single node because all store
675 // nodes are independent of each other.
676 if (!MemOpChains.empty())
677 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
678 &MemOpChains[0], MemOpChains.size());
680 // Build a sequence of copy-to-reg nodes chained together with token
681 // chain and flag operands which copy the outgoing args into registers.
682 // The InFlag in necessary since all emited instructions must be
685 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
686 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
687 RegsToPass[i].second, InFlag);
688 InFlag = Chain.getValue(1);
691 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
692 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
693 // node so that legalize doesn't hack it.
694 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
695 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
696 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
697 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
700 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
701 // = Chain, Callee, Reg#1, Reg#2, ...
703 // Returns a chain & a flag for retval copy to use.
704 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
705 SmallVector<SDValue, 8> Ops;
706 Ops.push_back(Chain);
707 Ops.push_back(Callee);
709 // Add argument registers to the end of the list so that they are
710 // known live into the call.
711 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
712 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
713 RegsToPass[i].second.getValueType()));
716 Ops.push_back(InFlag);
718 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
719 InFlag = Chain.getValue(1);
721 // Create the CALLSEQ_END node.
722 Chain = DAG.getCALLSEQ_END(Chain,
723 DAG.getConstant(NumBytes, getPointerTy()),
724 DAG.getConstant(0, getPointerTy()),
726 InFlag = Chain.getValue(1);
728 // Create a stack location to hold GP when PIC is used. This stack
729 // location is used on function prologue to save GP and also after all
730 // emited CALL's to restore GP.
731 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
732 // Function can have an arbitrary number of calls, so
733 // hold the LastArgStackLoc with the biggest offset.
735 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
736 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
737 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
738 // Create the frame index only once. SPOffset here can be anything
739 // (this will be fixed on processFunctionBeforeFrameFinalized)
740 if (MipsFI->getGPStackOffset() == -1) {
741 FI = MFI->CreateFixedObject(4, 0);
744 MipsFI->setGPStackOffset(LastArgStackLoc);
748 FI = MipsFI->getGPFI();
749 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
750 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
751 Chain = GPLoad.getValue(1);
752 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
753 GPLoad, SDValue(0,0));
754 InFlag = Chain.getValue(1);
757 // Handle result values, copying them out of physregs into vregs that we
759 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
762 /// LowerCallResult - Lower the result values of an ISD::CALL into the
763 /// appropriate copies out of appropriate physical registers. This assumes that
764 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
765 /// being lowered. Returns a SDNode with the same number of values as the
767 SDNode *MipsTargetLowering::
768 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
769 unsigned CallingConv, SelectionDAG &DAG) {
771 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
773 // Assign locations to each value returned by this call.
774 SmallVector<CCValAssign, 16> RVLocs;
775 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
777 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
778 SmallVector<SDValue, 8> ResultVals;
780 // Copy all of the result registers out of their specified physreg.
781 for (unsigned i = 0; i != RVLocs.size(); ++i) {
782 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
783 RVLocs[i].getValVT(), InFlag).getValue(1);
784 InFlag = Chain.getValue(2);
785 ResultVals.push_back(Chain.getValue(0));
788 ResultVals.push_back(Chain);
790 // Merge everything together with a MERGE_VALUES node.
791 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
792 ResultVals.size()).Val;
795 //===----------------------------------------------------------------------===//
796 // FORMAL_ARGUMENTS Calling Convention Implementation
797 //===----------------------------------------------------------------------===//
799 /// LowerFORMAL_ARGUMENTS - transform physical registers into
800 /// virtual registers and generate load operations for
801 /// arguments places on the stack.
803 SDValue MipsTargetLowering::
804 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
806 SDValue Root = Op.getOperand(0);
807 MachineFunction &MF = DAG.getMachineFunction();
808 MachineFrameInfo *MFI = MF.getFrameInfo();
809 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
811 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
812 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
814 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
816 // GP must be live into PIC and non-PIC call target.
817 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
819 // Assign locations to all of the incoming arguments.
820 SmallVector<CCValAssign, 16> ArgLocs;
821 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
823 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
824 SmallVector<SDValue, 16> ArgValues;
827 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
831 CCValAssign &VA = ArgLocs[i];
833 // Arguments stored on registers
835 MVT RegVT = VA.getLocVT();
836 TargetRegisterClass *RC = 0;
838 if (RegVT == MVT::i32)
839 RC = Mips::CPURegsRegisterClass;
840 else if (RegVT == MVT::f32) {
841 if (Subtarget->isSingleFloat())
842 RC = Mips::FGR32RegisterClass;
844 RC = Mips::AFGR32RegisterClass;
845 } else if (RegVT == MVT::f64) {
846 if (!Subtarget->isSingleFloat())
847 RC = Mips::AFGR64RegisterClass;
849 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
851 // Transform the arguments stored on
852 // physical registers into virtual ones
853 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
854 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
856 // If this is an 8 or 16-bit value, it is really passed promoted
857 // to 32 bits. Insert an assert[sz]ext to capture this, then
858 // truncate to the right size.
859 if (VA.getLocInfo() == CCValAssign::SExt)
860 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
861 DAG.getValueType(VA.getValVT()));
862 else if (VA.getLocInfo() == CCValAssign::ZExt)
863 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
864 DAG.getValueType(VA.getValVT()));
866 if (VA.getLocInfo() != CCValAssign::Full)
867 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
869 ArgValues.push_back(ArgValue);
871 // To meet ABI, when VARARGS are passed on registers, the registers
872 // must have their values written to the caller stack frame.
873 if ((isVarArg) && (Subtarget->isABI_O32())) {
874 if (StackPtr.Val == 0)
875 StackPtr = DAG.getRegister(StackReg, getPointerTy());
877 // The stack pointer offset is relative to the caller stack frame.
878 // Since the real stack size is unknown here, a negative SPOffset
879 // is used so there's a way to adjust these offsets when the stack
880 // size get known (on EliminateFrameIndex). A dummy SPOffset is
881 // used instead of a direct negative address (which is recorded to
882 // be used on emitPrologue) to avoid mis-calc of the first stack
883 // offset on PEI::calculateFrameObjectOffsets.
884 // Arguments are always 32-bit.
885 int FI = MFI->CreateFixedObject(4, 0);
886 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
887 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
889 // emit ISD::STORE whichs stores the
890 // parameter value to a stack Location
891 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
894 } else { // VA.isRegLoc()
897 assert(VA.isMemLoc());
899 // The stack pointer offset is relative to the caller stack frame.
900 // Since the real stack size is unknown here, a negative SPOffset
901 // is used so there's a way to adjust these offsets when the stack
902 // size get known (on EliminateFrameIndex). A dummy SPOffset is
903 // used instead of a direct negative address (which is recorded to
904 // be used on emitPrologue) to avoid mis-calc of the first stack
905 // offset on PEI::calculateFrameObjectOffsets.
906 // Arguments are always 32-bit.
907 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
908 int FI = MFI->CreateFixedObject(ArgSize, 0);
909 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
910 (FirstStackArgLoc + VA.getLocMemOffset())));
912 // Create load nodes to retrieve arguments from the stack
913 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
914 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
918 // The mips ABIs for returning structs by value requires that we copy
919 // the sret argument into $v0 for the return. Save the argument into
920 // a virtual register so that we can access it from the return points.
921 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
922 unsigned Reg = MipsFI->getSRetReturnReg();
924 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
925 MipsFI->setSRetReturnReg(Reg);
927 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
928 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
931 ArgValues.push_back(Root);
933 // Return the new list of results.
934 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
935 ArgValues.size()).getValue(Op.ResNo);
938 //===----------------------------------------------------------------------===//
939 // Return Value Calling Convention Implementation
940 //===----------------------------------------------------------------------===//
942 SDValue MipsTargetLowering::
943 LowerRET(SDValue Op, SelectionDAG &DAG)
945 // CCValAssign - represent the assignment of
946 // the return value to a location
947 SmallVector<CCValAssign, 16> RVLocs;
948 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
949 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
951 // CCState - Info about the registers and stack slot.
952 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
954 // Analize return values of ISD::RET
955 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
957 // If this is the first return lowered for this function, add
958 // the regs to the liveout set for the function.
959 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
960 for (unsigned i = 0; i != RVLocs.size(); ++i)
961 if (RVLocs[i].isRegLoc())
962 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
965 // The chain is always operand #0
966 SDValue Chain = Op.getOperand(0);
969 // Copy the result values into the output registers.
970 for (unsigned i = 0; i != RVLocs.size(); ++i) {
971 CCValAssign &VA = RVLocs[i];
972 assert(VA.isRegLoc() && "Can only return in registers!");
974 // ISD::RET => ret chain, (regnum1,val1), ...
975 // So i*2+1 index only the regnums
976 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
978 // guarantee that all emitted copies are
979 // stuck together, avoiding something bad
980 Flag = Chain.getValue(1);
983 // The mips ABIs for returning structs by value requires that we copy
984 // the sret argument into $v0 for the return. We saved the argument into
985 // a virtual register in the entry block, so now we copy the value out
987 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
988 MachineFunction &MF = DAG.getMachineFunction();
989 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
990 unsigned Reg = MipsFI->getSRetReturnReg();
993 assert(0 && "sret virtual register not created in the entry block");
994 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
996 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
997 Flag = Chain.getValue(1);
1000 // Return on Mips is always a "jr $ra"
1002 return DAG.getNode(MipsISD::Ret, MVT::Other,
1003 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1005 return DAG.getNode(MipsISD::Ret, MVT::Other,
1006 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1009 //===----------------------------------------------------------------------===//
1010 // Mips Inline Assembly Support
1011 //===----------------------------------------------------------------------===//
1013 /// getConstraintType - Given a constraint letter, return the type of
1014 /// constraint it is for this target.
1015 MipsTargetLowering::ConstraintType MipsTargetLowering::
1016 getConstraintType(const std::string &Constraint) const
1018 // Mips specific constrainy
1019 // GCC config/mips/constraints.md
1021 // 'd' : An address register. Equivalent to r
1022 // unless generating MIPS16 code.
1023 // 'y' : Equivalent to r; retained for
1024 // backwards compatibility.
1025 // 'f' : Floating Point registers.
1026 if (Constraint.size() == 1) {
1027 switch (Constraint[0]) {
1032 return C_RegisterClass;
1036 return TargetLowering::getConstraintType(Constraint);
1039 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1040 /// return a list of registers that can be used to satisfy the constraint.
1041 /// This should only be used for C_RegisterClass constraints.
1042 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1043 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1045 if (Constraint.size() == 1) {
1046 switch (Constraint[0]) {
1048 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1050 if (VT == MVT::f32) {
1051 if (Subtarget->isSingleFloat())
1052 return std::make_pair(0U, Mips::FGR32RegisterClass);
1054 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1057 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1058 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1061 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1064 /// Given a register class constraint, like 'r', if this corresponds directly
1065 /// to an LLVM register class, return a register of 0 and the register class
1067 std::vector<unsigned> MipsTargetLowering::
1068 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1071 if (Constraint.size() != 1)
1072 return std::vector<unsigned>();
1074 switch (Constraint[0]) {
1077 // GCC Mips Constraint Letters
1080 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1081 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1082 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1086 if (VT == MVT::f32) {
1087 if (Subtarget->isSingleFloat())
1088 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1089 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1090 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1091 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1092 Mips::F30, Mips::F31, 0);
1094 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1095 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1096 Mips::F28, Mips::F30, 0);
1100 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1101 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1102 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1103 Mips::D14, Mips::D15, 0);
1105 return std::vector<unsigned>();