1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "InstPrinter/MipsInstPrinter.h"
22 #include "MCTargetDesc/MipsBaseInfo.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAGISel.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
43 STATISTIC(NumTailCalls, "Number of tail calls");
46 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
47 cl::desc("MIPS: Enable tail calls."), cl::init(false));
49 static const uint16_t O32IntRegs[4] = {
50 Mips::A0, Mips::A1, Mips::A2, Mips::A3
53 static const uint16_t Mips64IntRegs[8] = {
54 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
55 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
58 static const uint16_t Mips64DPRegs[8] = {
59 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
60 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
63 // If I is a shifted mask, set the size (Size) and the first bit of the
64 // mask (Pos), and return true.
65 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
66 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
67 if (!isShiftedMask_64(I))
70 Size = CountPopulation_64(I);
71 Pos = CountTrailingZeros_64(I);
75 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
76 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
77 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
80 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
82 case MipsISD::JmpLink: return "MipsISD::JmpLink";
83 case MipsISD::TailCall: return "MipsISD::TailCall";
84 case MipsISD::Hi: return "MipsISD::Hi";
85 case MipsISD::Lo: return "MipsISD::Lo";
86 case MipsISD::GPRel: return "MipsISD::GPRel";
87 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
88 case MipsISD::Ret: return "MipsISD::Ret";
89 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
90 case MipsISD::FPCmp: return "MipsISD::FPCmp";
91 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
92 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
93 case MipsISD::FPRound: return "MipsISD::FPRound";
94 case MipsISD::MAdd: return "MipsISD::MAdd";
95 case MipsISD::MAddu: return "MipsISD::MAddu";
96 case MipsISD::MSub: return "MipsISD::MSub";
97 case MipsISD::MSubu: return "MipsISD::MSubu";
98 case MipsISD::DivRem: return "MipsISD::DivRem";
99 case MipsISD::DivRemU: return "MipsISD::DivRemU";
100 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
101 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
102 case MipsISD::Wrapper: return "MipsISD::Wrapper";
103 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
104 case MipsISD::Sync: return "MipsISD::Sync";
105 case MipsISD::Ext: return "MipsISD::Ext";
106 case MipsISD::Ins: return "MipsISD::Ins";
107 case MipsISD::LWL: return "MipsISD::LWL";
108 case MipsISD::LWR: return "MipsISD::LWR";
109 case MipsISD::SWL: return "MipsISD::SWL";
110 case MipsISD::SWR: return "MipsISD::SWR";
111 case MipsISD::LDL: return "MipsISD::LDL";
112 case MipsISD::LDR: return "MipsISD::LDR";
113 case MipsISD::SDL: return "MipsISD::SDL";
114 case MipsISD::SDR: return "MipsISD::SDR";
115 case MipsISD::EXTP: return "MipsISD::EXTP";
116 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
117 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
118 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
119 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
120 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
121 case MipsISD::SHILO: return "MipsISD::SHILO";
122 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
123 case MipsISD::MULT: return "MipsISD::MULT";
124 case MipsISD::MULTU: return "MipsISD::MULTU";
125 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSPDSP";
126 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
127 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
128 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
129 default: return NULL;
134 MipsTargetLowering(MipsTargetMachine &TM)
135 : TargetLowering(TM, new MipsTargetObjectFile()),
136 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
137 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
138 IsO32(Subtarget->isABI_O32()) {
140 // Mips does not have i1 type, so use i32 for
141 // setcc operations results (slt, sgt, ...).
142 setBooleanContents(ZeroOrOneBooleanContent);
143 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
145 // Set up the register classes
146 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
149 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
151 if (Subtarget->inMips16Mode()) {
152 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
155 if (Subtarget->hasDSP()) {
156 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
158 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
159 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
161 // Expand all builtin opcodes.
162 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
163 setOperationAction(Opc, VecTys[i], Expand);
165 setOperationAction(ISD::LOAD, VecTys[i], Legal);
166 setOperationAction(ISD::STORE, VecTys[i], Legal);
167 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
171 if (!TM.Options.UseSoftFloat) {
172 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
174 // When dealing with single precision only, use libcalls
175 if (!Subtarget->isSingleFloat()) {
177 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
179 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
183 // Load extented operations for i1 types must be promoted
184 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
185 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
186 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
188 // MIPS doesn't have extending float->double load/store
189 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
190 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
192 // Used by legalize types to correctly generate the setcc result.
193 // Without this, every float setcc comes with a AND/OR with the result,
194 // we don't want this, since the fpcmp result goes to a flag register,
195 // which is used implicitly by brcond and select operations.
196 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
198 // Mips Custom Operations
199 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
200 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
201 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
202 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
203 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
204 setOperationAction(ISD::SELECT, MVT::f32, Custom);
205 setOperationAction(ISD::SELECT, MVT::f64, Custom);
206 setOperationAction(ISD::SELECT, MVT::i32, Custom);
207 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
208 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
209 setOperationAction(ISD::SETCC, MVT::f32, Custom);
210 setOperationAction(ISD::SETCC, MVT::f64, Custom);
211 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
212 setOperationAction(ISD::VASTART, MVT::Other, Custom);
213 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
214 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
215 if (Subtarget->inMips16Mode()) {
216 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
217 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
220 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
221 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
223 if (!Subtarget->inMips16Mode()) {
224 setOperationAction(ISD::LOAD, MVT::i32, Custom);
225 setOperationAction(ISD::STORE, MVT::i32, Custom);
228 if (!TM.Options.NoNaNsFPMath) {
229 setOperationAction(ISD::FABS, MVT::f32, Custom);
230 setOperationAction(ISD::FABS, MVT::f64, Custom);
234 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
235 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
236 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
237 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
238 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
239 setOperationAction(ISD::SELECT, MVT::i64, Custom);
240 setOperationAction(ISD::LOAD, MVT::i64, Custom);
241 setOperationAction(ISD::STORE, MVT::i64, Custom);
245 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
246 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
247 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
250 setOperationAction(ISD::SDIV, MVT::i32, Expand);
251 setOperationAction(ISD::SREM, MVT::i32, Expand);
252 setOperationAction(ISD::UDIV, MVT::i32, Expand);
253 setOperationAction(ISD::UREM, MVT::i32, Expand);
254 setOperationAction(ISD::SDIV, MVT::i64, Expand);
255 setOperationAction(ISD::SREM, MVT::i64, Expand);
256 setOperationAction(ISD::UDIV, MVT::i64, Expand);
257 setOperationAction(ISD::UREM, MVT::i64, Expand);
259 // Operations not directly supported by Mips.
260 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
261 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
262 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
263 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
264 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
266 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
267 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
269 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
270 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
271 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
272 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
273 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
274 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
275 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
276 setOperationAction(ISD::ROTL, MVT::i32, Expand);
277 setOperationAction(ISD::ROTL, MVT::i64, Expand);
278 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
279 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
281 if (!Subtarget->hasMips32r2())
282 setOperationAction(ISD::ROTR, MVT::i32, Expand);
284 if (!Subtarget->hasMips64r2())
285 setOperationAction(ISD::ROTR, MVT::i64, Expand);
287 setOperationAction(ISD::FSIN, MVT::f32, Expand);
288 setOperationAction(ISD::FSIN, MVT::f64, Expand);
289 setOperationAction(ISD::FCOS, MVT::f32, Expand);
290 setOperationAction(ISD::FCOS, MVT::f64, Expand);
291 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
292 setOperationAction(ISD::FPOW, MVT::f32, Expand);
293 setOperationAction(ISD::FPOW, MVT::f64, Expand);
294 setOperationAction(ISD::FLOG, MVT::f32, Expand);
295 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
296 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
297 setOperationAction(ISD::FEXP, MVT::f32, Expand);
298 setOperationAction(ISD::FMA, MVT::f32, Expand);
299 setOperationAction(ISD::FMA, MVT::f64, Expand);
300 setOperationAction(ISD::FREM, MVT::f32, Expand);
301 setOperationAction(ISD::FREM, MVT::f64, Expand);
303 if (!TM.Options.NoNaNsFPMath) {
304 setOperationAction(ISD::FNEG, MVT::f32, Expand);
305 setOperationAction(ISD::FNEG, MVT::f64, Expand);
308 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
309 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
310 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
311 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
313 setOperationAction(ISD::VAARG, MVT::Other, Expand);
314 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
315 setOperationAction(ISD::VAEND, MVT::Other, Expand);
317 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
318 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
320 // Use the default for now
321 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
322 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
324 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
325 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
326 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
327 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
329 if (Subtarget->inMips16Mode()) {
330 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
331 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
332 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
333 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
334 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
335 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
336 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
337 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
338 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
339 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
340 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
341 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
344 setInsertFencesForAtomic(true);
346 if (!Subtarget->hasSEInReg()) {
347 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
348 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
351 if (!Subtarget->hasBitCount()) {
352 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
353 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
356 if (!Subtarget->hasSwap()) {
357 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
358 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
362 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
363 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
364 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
365 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
368 setTargetDAGCombine(ISD::ADDE);
369 setTargetDAGCombine(ISD::SUBE);
370 setTargetDAGCombine(ISD::SDIVREM);
371 setTargetDAGCombine(ISD::UDIVREM);
372 setTargetDAGCombine(ISD::SELECT);
373 setTargetDAGCombine(ISD::AND);
374 setTargetDAGCombine(ISD::OR);
375 setTargetDAGCombine(ISD::ADD);
377 setMinFunctionAlignment(HasMips64 ? 3 : 2);
379 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
380 computeRegisterProperties();
382 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
383 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
385 maxStoresPerMemcpy = 16;
388 bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
389 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
391 if (Subtarget->inMips16Mode())
403 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
408 // Transforms a subgraph in CurDAG if the following pattern is found:
409 // (addc multLo, Lo0), (adde multHi, Hi0),
411 // multHi/Lo: product of multiplication
412 // Lo0: initial value of Lo register
413 // Hi0: initial value of Hi register
414 // Return true if pattern matching was successful.
415 static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
416 // ADDENode's second operand must be a flag output of an ADDC node in order
417 // for the matching to be successful.
418 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
420 if (ADDCNode->getOpcode() != ISD::ADDC)
423 SDValue MultHi = ADDENode->getOperand(0);
424 SDValue MultLo = ADDCNode->getOperand(0);
425 SDNode *MultNode = MultHi.getNode();
426 unsigned MultOpc = MultHi.getOpcode();
428 // MultHi and MultLo must be generated by the same node,
429 if (MultLo.getNode() != MultNode)
432 // and it must be a multiplication.
433 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
436 // MultLo amd MultHi must be the first and second output of MultNode
438 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
441 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
442 // of the values of MultNode, in which case MultNode will be removed in later
444 // If there exist users other than ADDENode or ADDCNode, this function returns
445 // here, which will result in MultNode being mapped to a single MULT
446 // instruction node rather than a pair of MULT and MADD instructions being
448 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
451 SDValue Chain = CurDAG->getEntryNode();
452 DebugLoc dl = ADDENode->getDebugLoc();
454 // create MipsMAdd(u) node
455 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
457 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
458 MultNode->getOperand(0),// Factor 0
459 MultNode->getOperand(1),// Factor 1
460 ADDCNode->getOperand(1),// Lo0
461 ADDENode->getOperand(1));// Hi0
463 // create CopyFromReg nodes
464 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
466 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
468 CopyFromLo.getValue(2));
470 // replace uses of adde and addc here
471 if (!SDValue(ADDCNode, 0).use_empty())
472 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
474 if (!SDValue(ADDENode, 0).use_empty())
475 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
481 // Transforms a subgraph in CurDAG if the following pattern is found:
482 // (addc Lo0, multLo), (sube Hi0, multHi),
484 // multHi/Lo: product of multiplication
485 // Lo0: initial value of Lo register
486 // Hi0: initial value of Hi register
487 // Return true if pattern matching was successful.
488 static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
489 // SUBENode's second operand must be a flag output of an SUBC node in order
490 // for the matching to be successful.
491 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
493 if (SUBCNode->getOpcode() != ISD::SUBC)
496 SDValue MultHi = SUBENode->getOperand(1);
497 SDValue MultLo = SUBCNode->getOperand(1);
498 SDNode *MultNode = MultHi.getNode();
499 unsigned MultOpc = MultHi.getOpcode();
501 // MultHi and MultLo must be generated by the same node,
502 if (MultLo.getNode() != MultNode)
505 // and it must be a multiplication.
506 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
509 // MultLo amd MultHi must be the first and second output of MultNode
511 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
514 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
515 // of the values of MultNode, in which case MultNode will be removed in later
517 // If there exist users other than SUBENode or SUBCNode, this function returns
518 // here, which will result in MultNode being mapped to a single MULT
519 // instruction node rather than a pair of MULT and MSUB instructions being
521 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
524 SDValue Chain = CurDAG->getEntryNode();
525 DebugLoc dl = SUBENode->getDebugLoc();
527 // create MipsSub(u) node
528 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
530 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
531 MultNode->getOperand(0),// Factor 0
532 MultNode->getOperand(1),// Factor 1
533 SUBCNode->getOperand(0),// Lo0
534 SUBENode->getOperand(0));// Hi0
536 // create CopyFromReg nodes
537 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
539 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
541 CopyFromLo.getValue(2));
543 // replace uses of sube and subc here
544 if (!SDValue(SUBCNode, 0).use_empty())
545 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
547 if (!SDValue(SUBENode, 0).use_empty())
548 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
553 static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
554 TargetLowering::DAGCombinerInfo &DCI,
555 const MipsSubtarget *Subtarget) {
556 if (DCI.isBeforeLegalize())
559 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
561 return SDValue(N, 0);
566 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
567 TargetLowering::DAGCombinerInfo &DCI,
568 const MipsSubtarget *Subtarget) {
569 if (DCI.isBeforeLegalize())
572 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
574 return SDValue(N, 0);
579 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
580 TargetLowering::DAGCombinerInfo &DCI,
581 const MipsSubtarget *Subtarget) {
582 if (DCI.isBeforeLegalizeOps())
585 EVT Ty = N->getValueType(0);
586 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
587 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
588 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
590 DebugLoc dl = N->getDebugLoc();
592 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
593 N->getOperand(0), N->getOperand(1));
594 SDValue InChain = DAG.getEntryNode();
595 SDValue InGlue = DivRem;
598 if (N->hasAnyUseOfValue(0)) {
599 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
601 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
602 InChain = CopyFromLo.getValue(1);
603 InGlue = CopyFromLo.getValue(2);
607 if (N->hasAnyUseOfValue(1)) {
608 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
610 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
616 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
618 default: llvm_unreachable("Unknown fp condition code!");
620 case ISD::SETOEQ: return Mips::FCOND_OEQ;
621 case ISD::SETUNE: return Mips::FCOND_UNE;
623 case ISD::SETOLT: return Mips::FCOND_OLT;
625 case ISD::SETOGT: return Mips::FCOND_OGT;
627 case ISD::SETOLE: return Mips::FCOND_OLE;
629 case ISD::SETOGE: return Mips::FCOND_OGE;
630 case ISD::SETULT: return Mips::FCOND_ULT;
631 case ISD::SETULE: return Mips::FCOND_ULE;
632 case ISD::SETUGT: return Mips::FCOND_UGT;
633 case ISD::SETUGE: return Mips::FCOND_UGE;
634 case ISD::SETUO: return Mips::FCOND_UN;
635 case ISD::SETO: return Mips::FCOND_OR;
637 case ISD::SETONE: return Mips::FCOND_ONE;
638 case ISD::SETUEQ: return Mips::FCOND_UEQ;
643 // Returns true if condition code has to be inverted.
644 static bool InvertFPCondCode(Mips::CondCode CC) {
645 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
648 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
649 "Illegal Condition Code");
654 // Creates and returns an FPCmp node from a setcc node.
655 // Returns Op if setcc is not a floating point comparison.
656 static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
657 // must be a SETCC node
658 if (Op.getOpcode() != ISD::SETCC)
661 SDValue LHS = Op.getOperand(0);
663 if (!LHS.getValueType().isFloatingPoint())
666 SDValue RHS = Op.getOperand(1);
667 DebugLoc dl = Op.getDebugLoc();
669 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
670 // node if necessary.
671 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
673 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
674 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
677 // Creates and returns a CMovFPT/F node.
678 static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
679 SDValue False, DebugLoc DL) {
680 bool invert = InvertFPCondCode((Mips::CondCode)
681 cast<ConstantSDNode>(Cond.getOperand(2))
684 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
685 True.getValueType(), True, False, Cond);
688 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
689 TargetLowering::DAGCombinerInfo &DCI,
690 const MipsSubtarget *Subtarget) {
691 if (DCI.isBeforeLegalizeOps())
694 SDValue SetCC = N->getOperand(0);
696 if ((SetCC.getOpcode() != ISD::SETCC) ||
697 !SetCC.getOperand(0).getValueType().isInteger())
700 SDValue False = N->getOperand(2);
701 EVT FalseTy = False.getValueType();
703 if (!FalseTy.isInteger())
706 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
708 if (!CN || CN->getZExtValue())
711 const DebugLoc DL = N->getDebugLoc();
712 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
713 SDValue True = N->getOperand(1);
715 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
716 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
718 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
721 static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
722 TargetLowering::DAGCombinerInfo &DCI,
723 const MipsSubtarget *Subtarget) {
724 // Pattern match EXT.
725 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
726 // => ext $dst, $src, size, pos
727 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
730 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
731 unsigned ShiftRightOpc = ShiftRight.getOpcode();
733 // Op's first operand must be a shift right.
734 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
737 // The second operand of the shift must be an immediate.
739 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
742 uint64_t Pos = CN->getZExtValue();
743 uint64_t SMPos, SMSize;
745 // Op's second operand must be a shifted mask.
746 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
747 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
750 // Return if the shifted mask does not start at bit 0 or the sum of its size
751 // and Pos exceeds the word's size.
752 EVT ValTy = N->getValueType(0);
753 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
756 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
757 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
758 DAG.getConstant(SMSize, MVT::i32));
761 static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
762 TargetLowering::DAGCombinerInfo &DCI,
763 const MipsSubtarget *Subtarget) {
764 // Pattern match INS.
765 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
766 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
767 // => ins $dst, $src, size, pos, $src1
768 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
771 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
772 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
775 // See if Op's first operand matches (and $src1 , mask0).
776 if (And0.getOpcode() != ISD::AND)
779 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
780 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
783 // See if Op's second operand matches (and (shl $src, pos), mask1).
784 if (And1.getOpcode() != ISD::AND)
787 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
788 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
791 // The shift masks must have the same position and size.
792 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
795 SDValue Shl = And1.getOperand(0);
796 if (Shl.getOpcode() != ISD::SHL)
799 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
802 unsigned Shamt = CN->getZExtValue();
804 // Return if the shift amount and the first bit position of mask are not the
806 EVT ValTy = N->getValueType(0);
807 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
810 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
811 DAG.getConstant(SMPos0, MVT::i32),
812 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
815 static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
816 TargetLowering::DAGCombinerInfo &DCI,
817 const MipsSubtarget *Subtarget) {
818 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
820 if (DCI.isBeforeLegalizeOps())
823 SDValue Add = N->getOperand(1);
825 if (Add.getOpcode() != ISD::ADD)
828 SDValue Lo = Add.getOperand(1);
830 if ((Lo.getOpcode() != MipsISD::Lo) ||
831 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
834 EVT ValTy = N->getValueType(0);
835 DebugLoc DL = N->getDebugLoc();
837 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
839 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
842 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
844 SelectionDAG &DAG = DCI.DAG;
845 unsigned opc = N->getOpcode();
850 return PerformADDECombine(N, DAG, DCI, Subtarget);
852 return PerformSUBECombine(N, DAG, DCI, Subtarget);
855 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
857 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
859 return PerformANDCombine(N, DAG, DCI, Subtarget);
861 return PerformORCombine(N, DAG, DCI, Subtarget);
863 return PerformADDCombine(N, DAG, DCI, Subtarget);
870 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
871 SmallVectorImpl<SDValue> &Results,
872 SelectionDAG &DAG) const {
873 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
875 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
876 Results.push_back(Res.getValue(I));
880 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
881 SmallVectorImpl<SDValue> &Results,
882 SelectionDAG &DAG) const {
883 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
885 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
886 Results.push_back(Res.getValue(I));
889 SDValue MipsTargetLowering::
890 LowerOperation(SDValue Op, SelectionDAG &DAG) const
892 switch (Op.getOpcode())
894 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
895 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
896 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
897 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
898 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
899 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
900 case ISD::SELECT: return LowerSELECT(Op, DAG);
901 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
902 case ISD::SETCC: return LowerSETCC(Op, DAG);
903 case ISD::VASTART: return LowerVASTART(Op, DAG);
904 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
905 case ISD::FABS: return LowerFABS(Op, DAG);
906 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
907 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
908 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
909 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
910 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
911 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
912 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
913 case ISD::LOAD: return LowerLOAD(Op, DAG);
914 case ISD::STORE: return LowerSTORE(Op, DAG);
915 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
916 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
921 //===----------------------------------------------------------------------===//
922 // Lower helper functions
923 //===----------------------------------------------------------------------===//
925 // AddLiveIn - This helper function adds the specified physical register to the
926 // MachineFunction as a live in value. It also creates a corresponding
927 // virtual register for it.
929 AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
931 assert(RC->contains(PReg) && "Not the correct regclass!");
932 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
933 MF.getRegInfo().addLiveIn(PReg, VReg);
937 // Get fp branch code (not opcode) from condition code.
938 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
939 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
940 return Mips::BRANCH_T;
942 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
943 "Invalid CondCode.");
945 return Mips::BRANCH_F;
949 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
951 const MipsSubtarget *Subtarget,
952 const TargetInstrInfo *TII,
953 bool isFPCmp, unsigned Opc) {
954 // There is no need to expand CMov instructions if target has
955 // conditional moves.
956 if (Subtarget->hasCondMov())
959 // To "insert" a SELECT_CC instruction, we actually have to insert the
960 // diamond control-flow pattern. The incoming instruction knows the
961 // destination vreg to set, the condition code register to branch on, the
962 // true/false values to select between, and a branch opcode to use.
963 const BasicBlock *LLVM_BB = BB->getBasicBlock();
964 MachineFunction::iterator It = BB;
971 // bNE r1, r0, copy1MBB
972 // fallthrough --> copy0MBB
973 MachineBasicBlock *thisMBB = BB;
974 MachineFunction *F = BB->getParent();
975 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
976 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
977 F->insert(It, copy0MBB);
978 F->insert(It, sinkMBB);
980 // Transfer the remainder of BB and its successor edges to sinkMBB.
981 sinkMBB->splice(sinkMBB->begin(), BB,
982 llvm::next(MachineBasicBlock::iterator(MI)),
984 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
986 // Next, add the true and fallthrough blocks as its successors.
987 BB->addSuccessor(copy0MBB);
988 BB->addSuccessor(sinkMBB);
990 // Emit the right instruction according to the type of the operands compared
992 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
994 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
995 .addReg(Mips::ZERO).addMBB(sinkMBB);
999 // # fallthrough to sinkMBB
1002 // Update machine-CFG edges
1003 BB->addSuccessor(sinkMBB);
1006 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
1011 BuildMI(*BB, BB->begin(), dl,
1012 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1013 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
1014 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1016 BuildMI(*BB, BB->begin(), dl,
1017 TII->get(Mips::PHI), MI->getOperand(0).getReg())
1018 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
1019 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
1021 MI->eraseFromParent(); // The pseudo instruction is gone now.
1027 MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
1029 // bposge32_pseudo $vr0
1039 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
1041 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
1042 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1043 const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
1044 DebugLoc DL = MI->getDebugLoc();
1045 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1046 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
1047 MachineFunction *F = BB->getParent();
1048 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
1049 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
1050 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
1053 F->insert(It, Sink);
1055 // Transfer the remainder of BB and its successor edges to Sink.
1056 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
1058 Sink->transferSuccessorsAndUpdatePHIs(BB);
1061 BB->addSuccessor(FBB);
1062 BB->addSuccessor(TBB);
1063 FBB->addSuccessor(Sink);
1064 TBB->addSuccessor(Sink);
1066 // Insert the real bposge32 instruction to $BB.
1067 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
1070 unsigned VR2 = RegInfo.createVirtualRegister(RC);
1071 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
1072 .addReg(Mips::ZERO).addImm(0);
1073 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
1076 unsigned VR1 = RegInfo.createVirtualRegister(RC);
1077 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
1078 .addReg(Mips::ZERO).addImm(1);
1080 // Insert phi function to $Sink.
1081 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
1082 MI->getOperand(0).getReg())
1083 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
1085 MI->eraseFromParent(); // The pseudo instruction is gone now.
1090 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1091 MachineBasicBlock *BB) const {
1092 switch (MI->getOpcode()) {
1093 default: llvm_unreachable("Unexpected instr type to insert");
1094 case Mips::ATOMIC_LOAD_ADD_I8:
1095 case Mips::ATOMIC_LOAD_ADD_I8_P8:
1096 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1097 case Mips::ATOMIC_LOAD_ADD_I16:
1098 case Mips::ATOMIC_LOAD_ADD_I16_P8:
1099 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1100 case Mips::ATOMIC_LOAD_ADD_I32:
1101 case Mips::ATOMIC_LOAD_ADD_I32_P8:
1102 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
1103 case Mips::ATOMIC_LOAD_ADD_I64:
1104 case Mips::ATOMIC_LOAD_ADD_I64_P8:
1105 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
1107 case Mips::ATOMIC_LOAD_AND_I8:
1108 case Mips::ATOMIC_LOAD_AND_I8_P8:
1109 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1110 case Mips::ATOMIC_LOAD_AND_I16:
1111 case Mips::ATOMIC_LOAD_AND_I16_P8:
1112 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1113 case Mips::ATOMIC_LOAD_AND_I32:
1114 case Mips::ATOMIC_LOAD_AND_I32_P8:
1115 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
1116 case Mips::ATOMIC_LOAD_AND_I64:
1117 case Mips::ATOMIC_LOAD_AND_I64_P8:
1118 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
1120 case Mips::ATOMIC_LOAD_OR_I8:
1121 case Mips::ATOMIC_LOAD_OR_I8_P8:
1122 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1123 case Mips::ATOMIC_LOAD_OR_I16:
1124 case Mips::ATOMIC_LOAD_OR_I16_P8:
1125 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1126 case Mips::ATOMIC_LOAD_OR_I32:
1127 case Mips::ATOMIC_LOAD_OR_I32_P8:
1128 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
1129 case Mips::ATOMIC_LOAD_OR_I64:
1130 case Mips::ATOMIC_LOAD_OR_I64_P8:
1131 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
1133 case Mips::ATOMIC_LOAD_XOR_I8:
1134 case Mips::ATOMIC_LOAD_XOR_I8_P8:
1135 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1136 case Mips::ATOMIC_LOAD_XOR_I16:
1137 case Mips::ATOMIC_LOAD_XOR_I16_P8:
1138 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1139 case Mips::ATOMIC_LOAD_XOR_I32:
1140 case Mips::ATOMIC_LOAD_XOR_I32_P8:
1141 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
1142 case Mips::ATOMIC_LOAD_XOR_I64:
1143 case Mips::ATOMIC_LOAD_XOR_I64_P8:
1144 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
1146 case Mips::ATOMIC_LOAD_NAND_I8:
1147 case Mips::ATOMIC_LOAD_NAND_I8_P8:
1148 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
1149 case Mips::ATOMIC_LOAD_NAND_I16:
1150 case Mips::ATOMIC_LOAD_NAND_I16_P8:
1151 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
1152 case Mips::ATOMIC_LOAD_NAND_I32:
1153 case Mips::ATOMIC_LOAD_NAND_I32_P8:
1154 return EmitAtomicBinary(MI, BB, 4, 0, true);
1155 case Mips::ATOMIC_LOAD_NAND_I64:
1156 case Mips::ATOMIC_LOAD_NAND_I64_P8:
1157 return EmitAtomicBinary(MI, BB, 8, 0, true);
1159 case Mips::ATOMIC_LOAD_SUB_I8:
1160 case Mips::ATOMIC_LOAD_SUB_I8_P8:
1161 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1162 case Mips::ATOMIC_LOAD_SUB_I16:
1163 case Mips::ATOMIC_LOAD_SUB_I16_P8:
1164 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1165 case Mips::ATOMIC_LOAD_SUB_I32:
1166 case Mips::ATOMIC_LOAD_SUB_I32_P8:
1167 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
1168 case Mips::ATOMIC_LOAD_SUB_I64:
1169 case Mips::ATOMIC_LOAD_SUB_I64_P8:
1170 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1172 case Mips::ATOMIC_SWAP_I8:
1173 case Mips::ATOMIC_SWAP_I8_P8:
1174 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
1175 case Mips::ATOMIC_SWAP_I16:
1176 case Mips::ATOMIC_SWAP_I16_P8:
1177 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
1178 case Mips::ATOMIC_SWAP_I32:
1179 case Mips::ATOMIC_SWAP_I32_P8:
1180 return EmitAtomicBinary(MI, BB, 4, 0);
1181 case Mips::ATOMIC_SWAP_I64:
1182 case Mips::ATOMIC_SWAP_I64_P8:
1183 return EmitAtomicBinary(MI, BB, 8, 0);
1185 case Mips::ATOMIC_CMP_SWAP_I8:
1186 case Mips::ATOMIC_CMP_SWAP_I8_P8:
1187 return EmitAtomicCmpSwapPartword(MI, BB, 1);
1188 case Mips::ATOMIC_CMP_SWAP_I16:
1189 case Mips::ATOMIC_CMP_SWAP_I16_P8:
1190 return EmitAtomicCmpSwapPartword(MI, BB, 2);
1191 case Mips::ATOMIC_CMP_SWAP_I32:
1192 case Mips::ATOMIC_CMP_SWAP_I32_P8:
1193 return EmitAtomicCmpSwap(MI, BB, 4);
1194 case Mips::ATOMIC_CMP_SWAP_I64:
1195 case Mips::ATOMIC_CMP_SWAP_I64_P8:
1196 return EmitAtomicCmpSwap(MI, BB, 8);
1197 case Mips::BPOSGE32_PSEUDO:
1198 return EmitBPOSGE32(MI, BB);
1202 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1203 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1205 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1206 unsigned Size, unsigned BinOpcode,
1208 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1210 MachineFunction *MF = BB->getParent();
1211 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1212 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1213 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1214 DebugLoc dl = MI->getDebugLoc();
1215 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1218 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1219 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1226 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1227 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1230 ZERO = Mips::ZERO_64;
1234 unsigned OldVal = MI->getOperand(0).getReg();
1235 unsigned Ptr = MI->getOperand(1).getReg();
1236 unsigned Incr = MI->getOperand(2).getReg();
1238 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1239 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1240 unsigned Success = RegInfo.createVirtualRegister(RC);
1242 // insert new blocks after the current block
1243 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1244 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1245 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1246 MachineFunction::iterator It = BB;
1248 MF->insert(It, loopMBB);
1249 MF->insert(It, exitMBB);
1251 // Transfer the remainder of BB and its successor edges to exitMBB.
1252 exitMBB->splice(exitMBB->begin(), BB,
1253 llvm::next(MachineBasicBlock::iterator(MI)),
1255 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1259 // fallthrough --> loopMBB
1260 BB->addSuccessor(loopMBB);
1261 loopMBB->addSuccessor(loopMBB);
1262 loopMBB->addSuccessor(exitMBB);
1265 // ll oldval, 0(ptr)
1266 // <binop> storeval, oldval, incr
1267 // sc success, storeval, 0(ptr)
1268 // beq success, $0, loopMBB
1270 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1272 // and andres, oldval, incr
1273 // nor storeval, $0, andres
1274 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1275 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1276 } else if (BinOpcode) {
1277 // <binop> storeval, oldval, incr
1278 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1282 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1283 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1285 MI->eraseFromParent(); // The instruction is gone now.
1291 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
1292 MachineBasicBlock *BB,
1293 unsigned Size, unsigned BinOpcode,
1295 assert((Size == 1 || Size == 2) &&
1296 "Unsupported size for EmitAtomicBinaryPartial.");
1298 MachineFunction *MF = BB->getParent();
1299 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1300 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1301 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1302 DebugLoc dl = MI->getDebugLoc();
1303 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1304 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1306 unsigned Dest = MI->getOperand(0).getReg();
1307 unsigned Ptr = MI->getOperand(1).getReg();
1308 unsigned Incr = MI->getOperand(2).getReg();
1310 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1311 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1312 unsigned Mask = RegInfo.createVirtualRegister(RC);
1313 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1314 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1315 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1316 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1317 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1318 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1319 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1320 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1321 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1322 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1323 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1324 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1325 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1326 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1327 unsigned Success = RegInfo.createVirtualRegister(RC);
1329 // insert new blocks after the current block
1330 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1331 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1332 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1333 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1334 MachineFunction::iterator It = BB;
1336 MF->insert(It, loopMBB);
1337 MF->insert(It, sinkMBB);
1338 MF->insert(It, exitMBB);
1340 // Transfer the remainder of BB and its successor edges to exitMBB.
1341 exitMBB->splice(exitMBB->begin(), BB,
1342 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1343 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1345 BB->addSuccessor(loopMBB);
1346 loopMBB->addSuccessor(loopMBB);
1347 loopMBB->addSuccessor(sinkMBB);
1348 sinkMBB->addSuccessor(exitMBB);
1351 // addiu masklsb2,$0,-4 # 0xfffffffc
1352 // and alignedaddr,ptr,masklsb2
1353 // andi ptrlsb2,ptr,3
1354 // sll shiftamt,ptrlsb2,3
1355 // ori maskupper,$0,255 # 0xff
1356 // sll mask,maskupper,shiftamt
1357 // nor mask2,$0,mask
1358 // sll incr2,incr,shiftamt
1360 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1361 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1362 .addReg(Mips::ZERO).addImm(-4);
1363 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1364 .addReg(Ptr).addReg(MaskLSB2);
1365 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1366 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1367 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1368 .addReg(Mips::ZERO).addImm(MaskImm);
1369 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1370 .addReg(ShiftAmt).addReg(MaskUpper);
1371 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1372 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
1374 // atomic.load.binop
1376 // ll oldval,0(alignedaddr)
1377 // binop binopres,oldval,incr2
1378 // and newval,binopres,mask
1379 // and maskedoldval0,oldval,mask2
1380 // or storeval,maskedoldval0,newval
1381 // sc success,storeval,0(alignedaddr)
1382 // beq success,$0,loopMBB
1386 // ll oldval,0(alignedaddr)
1387 // and newval,incr2,mask
1388 // and maskedoldval0,oldval,mask2
1389 // or storeval,maskedoldval0,newval
1390 // sc success,storeval,0(alignedaddr)
1391 // beq success,$0,loopMBB
1394 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1396 // and andres, oldval, incr2
1397 // nor binopres, $0, andres
1398 // and newval, binopres, mask
1399 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1400 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1401 .addReg(Mips::ZERO).addReg(AndRes);
1402 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1403 } else if (BinOpcode) {
1404 // <binop> binopres, oldval, incr2
1405 // and newval, binopres, mask
1406 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1407 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1408 } else {// atomic.swap
1409 // and newval, incr2, mask
1410 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1413 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1414 .addReg(OldVal).addReg(Mask2);
1415 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1416 .addReg(MaskedOldVal0).addReg(NewVal);
1417 BuildMI(BB, dl, TII->get(SC), Success)
1418 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1419 BuildMI(BB, dl, TII->get(Mips::BEQ))
1420 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1423 // and maskedoldval1,oldval,mask
1424 // srl srlres,maskedoldval1,shiftamt
1425 // sll sllres,srlres,24
1426 // sra dest,sllres,24
1428 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1430 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1431 .addReg(OldVal).addReg(Mask);
1432 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1433 .addReg(ShiftAmt).addReg(MaskedOldVal1);
1434 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1435 .addReg(SrlRes).addImm(ShiftImm);
1436 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1437 .addReg(SllRes).addImm(ShiftImm);
1439 MI->eraseFromParent(); // The instruction is gone now.
1445 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
1446 MachineBasicBlock *BB,
1447 unsigned Size) const {
1448 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1450 MachineFunction *MF = BB->getParent();
1451 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1452 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1453 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1454 DebugLoc dl = MI->getDebugLoc();
1455 unsigned LL, SC, ZERO, BNE, BEQ;
1458 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1459 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1465 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1466 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1467 ZERO = Mips::ZERO_64;
1472 unsigned Dest = MI->getOperand(0).getReg();
1473 unsigned Ptr = MI->getOperand(1).getReg();
1474 unsigned OldVal = MI->getOperand(2).getReg();
1475 unsigned NewVal = MI->getOperand(3).getReg();
1477 unsigned Success = RegInfo.createVirtualRegister(RC);
1479 // insert new blocks after the current block
1480 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1481 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1482 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1483 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1484 MachineFunction::iterator It = BB;
1486 MF->insert(It, loop1MBB);
1487 MF->insert(It, loop2MBB);
1488 MF->insert(It, exitMBB);
1490 // Transfer the remainder of BB and its successor edges to exitMBB.
1491 exitMBB->splice(exitMBB->begin(), BB,
1492 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1493 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1497 // fallthrough --> loop1MBB
1498 BB->addSuccessor(loop1MBB);
1499 loop1MBB->addSuccessor(exitMBB);
1500 loop1MBB->addSuccessor(loop2MBB);
1501 loop2MBB->addSuccessor(loop1MBB);
1502 loop2MBB->addSuccessor(exitMBB);
1506 // bne dest, oldval, exitMBB
1508 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1509 BuildMI(BB, dl, TII->get(BNE))
1510 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1513 // sc success, newval, 0(ptr)
1514 // beq success, $0, loop1MBB
1516 BuildMI(BB, dl, TII->get(SC), Success)
1517 .addReg(NewVal).addReg(Ptr).addImm(0);
1518 BuildMI(BB, dl, TII->get(BEQ))
1519 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1521 MI->eraseFromParent(); // The instruction is gone now.
1527 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
1528 MachineBasicBlock *BB,
1529 unsigned Size) const {
1530 assert((Size == 1 || Size == 2) &&
1531 "Unsupported size for EmitAtomicCmpSwapPartial.");
1533 MachineFunction *MF = BB->getParent();
1534 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1535 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1536 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1537 DebugLoc dl = MI->getDebugLoc();
1538 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1539 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1541 unsigned Dest = MI->getOperand(0).getReg();
1542 unsigned Ptr = MI->getOperand(1).getReg();
1543 unsigned CmpVal = MI->getOperand(2).getReg();
1544 unsigned NewVal = MI->getOperand(3).getReg();
1546 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1547 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1548 unsigned Mask = RegInfo.createVirtualRegister(RC);
1549 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1550 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1551 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1552 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1553 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1554 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1555 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1556 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1557 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1558 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1559 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1560 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1561 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1562 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1563 unsigned Success = RegInfo.createVirtualRegister(RC);
1565 // insert new blocks after the current block
1566 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1567 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1568 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1569 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1570 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1571 MachineFunction::iterator It = BB;
1573 MF->insert(It, loop1MBB);
1574 MF->insert(It, loop2MBB);
1575 MF->insert(It, sinkMBB);
1576 MF->insert(It, exitMBB);
1578 // Transfer the remainder of BB and its successor edges to exitMBB.
1579 exitMBB->splice(exitMBB->begin(), BB,
1580 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1581 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1583 BB->addSuccessor(loop1MBB);
1584 loop1MBB->addSuccessor(sinkMBB);
1585 loop1MBB->addSuccessor(loop2MBB);
1586 loop2MBB->addSuccessor(loop1MBB);
1587 loop2MBB->addSuccessor(sinkMBB);
1588 sinkMBB->addSuccessor(exitMBB);
1590 // FIXME: computation of newval2 can be moved to loop2MBB.
1592 // addiu masklsb2,$0,-4 # 0xfffffffc
1593 // and alignedaddr,ptr,masklsb2
1594 // andi ptrlsb2,ptr,3
1595 // sll shiftamt,ptrlsb2,3
1596 // ori maskupper,$0,255 # 0xff
1597 // sll mask,maskupper,shiftamt
1598 // nor mask2,$0,mask
1599 // andi maskedcmpval,cmpval,255
1600 // sll shiftedcmpval,maskedcmpval,shiftamt
1601 // andi maskednewval,newval,255
1602 // sll shiftednewval,maskednewval,shiftamt
1603 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1604 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1605 .addReg(Mips::ZERO).addImm(-4);
1606 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1607 .addReg(Ptr).addReg(MaskLSB2);
1608 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1609 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1610 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1611 .addReg(Mips::ZERO).addImm(MaskImm);
1612 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1613 .addReg(ShiftAmt).addReg(MaskUpper);
1614 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1615 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1616 .addReg(CmpVal).addImm(MaskImm);
1617 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1618 .addReg(ShiftAmt).addReg(MaskedCmpVal);
1619 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1620 .addReg(NewVal).addImm(MaskImm);
1621 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1622 .addReg(ShiftAmt).addReg(MaskedNewVal);
1625 // ll oldval,0(alginedaddr)
1626 // and maskedoldval0,oldval,mask
1627 // bne maskedoldval0,shiftedcmpval,sinkMBB
1629 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1630 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1631 .addReg(OldVal).addReg(Mask);
1632 BuildMI(BB, dl, TII->get(Mips::BNE))
1633 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1636 // and maskedoldval1,oldval,mask2
1637 // or storeval,maskedoldval1,shiftednewval
1638 // sc success,storeval,0(alignedaddr)
1639 // beq success,$0,loop1MBB
1641 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1642 .addReg(OldVal).addReg(Mask2);
1643 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1644 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1645 BuildMI(BB, dl, TII->get(SC), Success)
1646 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1647 BuildMI(BB, dl, TII->get(Mips::BEQ))
1648 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1651 // srl srlres,maskedoldval0,shiftamt
1652 // sll sllres,srlres,24
1653 // sra dest,sllres,24
1655 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1657 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1658 .addReg(ShiftAmt).addReg(MaskedOldVal0);
1659 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1660 .addReg(SrlRes).addImm(ShiftImm);
1661 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
1662 .addReg(SllRes).addImm(ShiftImm);
1664 MI->eraseFromParent(); // The instruction is gone now.
1669 //===----------------------------------------------------------------------===//
1670 // Misc Lower Operation implementation
1671 //===----------------------------------------------------------------------===//
1672 SDValue MipsTargetLowering::
1673 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1675 // The first operand is the chain, the second is the condition, the third is
1676 // the block to branch to if the condition is true.
1677 SDValue Chain = Op.getOperand(0);
1678 SDValue Dest = Op.getOperand(2);
1679 DebugLoc dl = Op.getDebugLoc();
1681 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1683 // Return if flag is not set by a floating point comparison.
1684 if (CondRes.getOpcode() != MipsISD::FPCmp)
1687 SDValue CCNode = CondRes.getOperand(2);
1689 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1690 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
1692 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
1696 SDValue MipsTargetLowering::
1697 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
1699 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
1701 // Return if flag is not set by a floating point comparison.
1702 if (Cond.getOpcode() != MipsISD::FPCmp)
1705 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1709 SDValue MipsTargetLowering::
1710 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1712 DebugLoc DL = Op.getDebugLoc();
1713 EVT Ty = Op.getOperand(0).getValueType();
1714 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
1715 Op.getOperand(0), Op.getOperand(1),
1718 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1722 SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1723 SDValue Cond = CreateFPCmp(DAG, Op);
1725 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1726 "Floating point operand expected.");
1728 SDValue True = DAG.getConstant(1, MVT::i32);
1729 SDValue False = DAG.getConstant(0, MVT::i32);
1731 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1734 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1735 SelectionDAG &DAG) const {
1736 // FIXME there isn't actually debug info here
1737 DebugLoc dl = Op.getDebugLoc();
1738 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1740 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1741 SDVTList VTs = DAG.getVTList(MVT::i32);
1743 const MipsTargetObjectFile &TLOF =
1744 (const MipsTargetObjectFile&)getObjFileLowering();
1746 // %gp_rel relocation
1747 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1748 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1750 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1751 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1752 return DAG.getNode(ISD::ADD, dl, MVT::i32, GPReg, GPRelNode);
1754 // %hi/%lo relocation
1755 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1757 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1759 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1760 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
1761 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1764 EVT ValTy = Op.getValueType();
1765 bool HasGotOfst = (GV->hasInternalLinkage() ||
1766 (GV->hasLocalLinkage() && !isa<Function>(GV)));
1767 unsigned GotFlag = HasMips64 ?
1768 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
1769 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
1770 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
1771 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
1772 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1773 MachinePointerInfo(), false, false, false, 0);
1774 // On functions and global targets not internal linked only
1775 // a load from got/GP is necessary for PIC to work.
1778 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
1779 HasMips64 ? MipsII::MO_GOT_OFST :
1781 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1782 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
1785 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1786 SelectionDAG &DAG) const {
1787 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1788 // FIXME there isn't actually debug info here
1789 DebugLoc dl = Op.getDebugLoc();
1791 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1792 // %hi/%lo relocation
1794 DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_HI);
1796 DAG.getTargetBlockAddress(BA, MVT::i32, 0, MipsII::MO_ABS_LO);
1797 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1798 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1799 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
1802 EVT ValTy = Op.getValueType();
1803 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1804 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1805 SDValue BAGOTOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, GOTFlag);
1806 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1807 GetGlobalReg(DAG, ValTy), BAGOTOffset);
1808 SDValue BALOOffset = DAG.getTargetBlockAddress(BA, ValTy, 0, OFSTFlag);
1809 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
1810 MachinePointerInfo(), false, false, false, 0);
1811 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1812 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
1815 SDValue MipsTargetLowering::
1816 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1818 // If the relocation model is PIC, use the General Dynamic TLS Model or
1819 // Local Dynamic TLS model, otherwise use the Initial Exec or
1820 // Local Exec TLS Model.
1822 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1823 DebugLoc dl = GA->getDebugLoc();
1824 const GlobalValue *GV = GA->getGlobal();
1825 EVT PtrVT = getPointerTy();
1827 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1829 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1830 // General Dynamic and Local Dynamic TLS Model.
1831 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1834 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
1835 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1836 GetGlobalReg(DAG, PtrVT), TGA);
1837 unsigned PtrSize = PtrVT.getSizeInBits();
1838 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1840 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1844 Entry.Node = Argument;
1846 Args.push_back(Entry);
1848 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1849 false, false, false, false, 0, CallingConv::C,
1850 /*isTailCall=*/false, /*doesNotRet=*/false,
1851 /*isReturnValueUsed=*/true,
1852 TlsGetAddr, Args, DAG, dl);
1853 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1855 SDValue Ret = CallResult.first;
1857 if (model != TLSModel::LocalDynamic)
1860 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1861 MipsII::MO_DTPREL_HI);
1862 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1863 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1864 MipsII::MO_DTPREL_LO);
1865 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1866 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1867 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
1871 if (model == TLSModel::InitialExec) {
1872 // Initial Exec TLS Model
1873 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1874 MipsII::MO_GOTTPREL);
1875 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1877 Offset = DAG.getLoad(PtrVT, dl,
1878 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1879 false, false, false, 0);
1881 // Local Exec TLS Model
1882 assert(model == TLSModel::LocalExec);
1883 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1884 MipsII::MO_TPREL_HI);
1885 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1886 MipsII::MO_TPREL_LO);
1887 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1888 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1889 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1892 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1893 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1896 SDValue MipsTargetLowering::
1897 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1899 SDValue HiPart, JTI, JTILo;
1900 // FIXME there isn't actually debug info here
1901 DebugLoc dl = Op.getDebugLoc();
1902 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1903 EVT PtrVT = Op.getValueType();
1904 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1906 if (!IsPIC && !IsN64) {
1907 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1908 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1909 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
1910 } else {// Emit Load from Global Pointer
1911 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1912 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1913 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
1914 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1916 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1917 MachinePointerInfo(), false, false, false, 0);
1918 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
1921 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1922 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
1925 SDValue MipsTargetLowering::
1926 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1929 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1930 const Constant *C = N->getConstVal();
1931 // FIXME there isn't actually debug info here
1932 DebugLoc dl = Op.getDebugLoc();
1934 // gp_rel relocation
1935 // FIXME: we should reference the constant pool using small data sections,
1936 // but the asm printer currently doesn't support this feature without
1937 // hacking it. This feature should come soon so we can uncomment the
1939 //if (IsInSmallSection(C->getType())) {
1940 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1941 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1942 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1944 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1945 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1946 N->getOffset(), MipsII::MO_ABS_HI);
1947 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
1948 N->getOffset(), MipsII::MO_ABS_LO);
1949 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1950 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
1951 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
1953 EVT ValTy = Op.getValueType();
1954 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1955 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
1956 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1957 N->getOffset(), GOTFlag);
1958 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
1959 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1960 MachinePointerInfo::getConstantPool(), false,
1962 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1963 N->getOffset(), OFSTFlag);
1964 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1965 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
1971 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1972 MachineFunction &MF = DAG.getMachineFunction();
1973 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1975 DebugLoc dl = Op.getDebugLoc();
1976 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1979 // vastart just stores the address of the VarArgsFrameIndex slot into the
1980 // memory location argument.
1981 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1982 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
1983 MachinePointerInfo(SV), false, false, 0);
1986 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1987 EVT TyX = Op.getOperand(0).getValueType();
1988 EVT TyY = Op.getOperand(1).getValueType();
1989 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1990 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1991 DebugLoc DL = Op.getDebugLoc();
1994 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1996 SDValue X = (TyX == MVT::f32) ?
1997 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1998 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2000 SDValue Y = (TyY == MVT::f32) ?
2001 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2002 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2006 // ext E, Y, 31, 1 ; extract bit31 of Y
2007 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2008 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2009 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2012 // srl SrlX, SllX, 1
2014 // sll SllY, SrlX, 31
2015 // or Or, SrlX, SllY
2016 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2017 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2018 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2019 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2020 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2023 if (TyX == MVT::f32)
2024 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2026 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2027 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2028 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2031 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2032 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2033 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2034 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2035 SDValue Const1 = DAG.getConstant(1, MVT::i32);
2036 DebugLoc DL = Op.getDebugLoc();
2038 // Bitcast to integer nodes.
2039 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2040 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2043 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2044 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2045 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2046 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
2048 if (WidthX > WidthY)
2049 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2050 else if (WidthY > WidthX)
2051 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2053 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2054 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
2055 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2058 // (d)sll SllX, X, 1
2059 // (d)srl SrlX, SllX, 1
2060 // (d)srl SrlY, Y, width(Y)-1
2061 // (d)sll SllY, SrlX, width(Y)-1
2062 // or Or, SrlX, SllY
2063 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2064 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2065 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2066 DAG.getConstant(WidthY - 1, MVT::i32));
2068 if (WidthX > WidthY)
2069 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2070 else if (WidthY > WidthX)
2071 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2073 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2074 DAG.getConstant(WidthX - 1, MVT::i32));
2075 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2076 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2080 MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2081 if (Subtarget->hasMips64())
2082 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
2084 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
2087 static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2088 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2089 DebugLoc DL = Op.getDebugLoc();
2091 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2093 SDValue X = (Op.getValueType() == MVT::f32) ?
2094 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2095 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2100 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2101 DAG.getRegister(Mips::ZERO, MVT::i32),
2102 DAG.getConstant(31, MVT::i32), Const1, X);
2104 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2105 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2108 if (Op.getValueType() == MVT::f32)
2109 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2111 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2112 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
2113 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2116 static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
2117 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
2118 DebugLoc DL = Op.getDebugLoc();
2120 // Bitcast to integer node.
2121 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2125 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2126 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2127 DAG.getConstant(63, MVT::i32), Const1, X);
2129 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2130 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2133 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2137 MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
2138 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
2139 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
2141 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
2144 SDValue MipsTargetLowering::
2145 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2147 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2148 "Frame address can only be determined for current frame.");
2150 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2151 MFI->setFrameAddressIsTaken(true);
2152 EVT VT = Op.getValueType();
2153 DebugLoc dl = Op.getDebugLoc();
2154 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2155 IsN64 ? Mips::FP_64 : Mips::FP, VT);
2159 SDValue MipsTargetLowering::LowerRETURNADDR(SDValue Op,
2160 SelectionDAG &DAG) const {
2162 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2163 "Return address can be determined only for current frame.");
2165 MachineFunction &MF = DAG.getMachineFunction();
2166 MachineFrameInfo *MFI = MF.getFrameInfo();
2167 EVT VT = Op.getValueType();
2168 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
2169 MFI->setReturnAddressIsTaken(true);
2171 // Return RA, which contains the return address. Mark it an implicit live-in.
2172 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2173 return DAG.getCopyFromReg(DAG.getEntryNode(), Op.getDebugLoc(), Reg, VT);
2176 // TODO: set SType according to the desired memory barrier behavior.
2178 MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
2180 DebugLoc dl = Op.getDebugLoc();
2181 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2182 DAG.getConstant(SType, MVT::i32));
2185 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
2186 SelectionDAG &DAG) const {
2187 // FIXME: Need pseudo-fence for 'singlethread' fences
2188 // FIXME: Set SType for weaker fences where supported/appropriate.
2190 DebugLoc dl = Op.getDebugLoc();
2191 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
2192 DAG.getConstant(SType, MVT::i32));
2195 SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
2196 SelectionDAG &DAG) const {
2197 DebugLoc DL = Op.getDebugLoc();
2198 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2199 SDValue Shamt = Op.getOperand(2);
2202 // lo = (shl lo, shamt)
2203 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2206 // hi = (shl lo, shamt[4:0])
2207 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2208 DAG.getConstant(-1, MVT::i32));
2209 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2210 DAG.getConstant(1, MVT::i32));
2211 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2213 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2214 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2215 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2216 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2217 DAG.getConstant(0x20, MVT::i32));
2218 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2219 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
2220 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2222 SDValue Ops[2] = {Lo, Hi};
2223 return DAG.getMergeValues(Ops, 2, DL);
2226 SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2228 DebugLoc DL = Op.getDebugLoc();
2229 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2230 SDValue Shamt = Op.getOperand(2);
2233 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2235 // hi = (sra hi, shamt)
2237 // hi = (srl hi, shamt)
2240 // lo = (sra hi, shamt[4:0])
2241 // hi = (sra hi, 31)
2243 // lo = (srl hi, shamt[4:0])
2245 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2246 DAG.getConstant(-1, MVT::i32));
2247 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2248 DAG.getConstant(1, MVT::i32));
2249 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2250 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2251 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2252 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2254 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2255 DAG.getConstant(0x20, MVT::i32));
2256 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2257 DAG.getConstant(31, MVT::i32));
2258 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2259 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2260 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2263 SDValue Ops[2] = {Lo, Hi};
2264 return DAG.getMergeValues(Ops, 2, DL);
2267 static SDValue CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2268 SDValue Chain, SDValue Src, unsigned Offset) {
2269 SDValue Ptr = LD->getBasePtr();
2270 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2271 EVT BasePtrVT = Ptr.getValueType();
2272 DebugLoc DL = LD->getDebugLoc();
2273 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2276 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2277 DAG.getConstant(Offset, BasePtrVT));
2279 SDValue Ops[] = { Chain, Ptr, Src };
2280 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2281 LD->getMemOperand());
2284 // Expand an unaligned 32 or 64-bit integer load node.
2285 SDValue MipsTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2286 LoadSDNode *LD = cast<LoadSDNode>(Op);
2287 EVT MemVT = LD->getMemoryVT();
2289 // Return if load is aligned or if MemVT is neither i32 nor i64.
2290 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2291 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2294 bool IsLittle = Subtarget->isLittle();
2295 EVT VT = Op.getValueType();
2296 ISD::LoadExtType ExtType = LD->getExtensionType();
2297 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2299 assert((VT == MVT::i32) || (VT == MVT::i64));
2302 // (set dst, (i64 (load baseptr)))
2304 // (set tmp, (ldl (add baseptr, 7), undef))
2305 // (set dst, (ldr baseptr, tmp))
2306 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2307 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2309 return CreateLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2313 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2315 SDValue LWR = CreateLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2319 // (set dst, (i32 (load baseptr))) or
2320 // (set dst, (i64 (sextload baseptr))) or
2321 // (set dst, (i64 (extload baseptr)))
2323 // (set tmp, (lwl (add baseptr, 3), undef))
2324 // (set dst, (lwr baseptr, tmp))
2325 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2326 (ExtType == ISD::EXTLOAD))
2329 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2332 // (set dst, (i64 (zextload baseptr)))
2334 // (set tmp0, (lwl (add baseptr, 3), undef))
2335 // (set tmp1, (lwr baseptr, tmp0))
2336 // (set tmp2, (shl tmp1, 32))
2337 // (set dst, (srl tmp2, 32))
2338 DebugLoc DL = LD->getDebugLoc();
2339 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2340 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2341 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2342 SDValue Ops[] = { SRL, LWR.getValue(1) };
2343 return DAG.getMergeValues(Ops, 2, DL);
2346 static SDValue CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2347 SDValue Chain, unsigned Offset) {
2348 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2349 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2350 DebugLoc DL = SD->getDebugLoc();
2351 SDVTList VTList = DAG.getVTList(MVT::Other);
2354 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2355 DAG.getConstant(Offset, BasePtrVT));
2357 SDValue Ops[] = { Chain, Value, Ptr };
2358 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2359 SD->getMemOperand());
2362 // Expand an unaligned 32 or 64-bit integer store node.
2363 SDValue MipsTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2364 StoreSDNode *SD = cast<StoreSDNode>(Op);
2365 EVT MemVT = SD->getMemoryVT();
2367 // Return if store is aligned or if MemVT is neither i32 nor i64.
2368 if ((SD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2369 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2372 bool IsLittle = Subtarget->isLittle();
2373 SDValue Value = SD->getValue(), Chain = SD->getChain();
2374 EVT VT = Value.getValueType();
2377 // (store val, baseptr) or
2378 // (truncstore val, baseptr)
2380 // (swl val, (add baseptr, 3))
2381 // (swr val, baseptr)
2382 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2383 SDValue SWL = CreateStoreLR(MipsISD::SWL, DAG, SD, Chain,
2385 return CreateStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2388 assert(VT == MVT::i64);
2391 // (store val, baseptr)
2393 // (sdl val, (add baseptr, 7))
2394 // (sdr val, baseptr)
2395 SDValue SDL = CreateStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2396 return CreateStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2399 // This function expands mips intrinsic nodes which have 64-bit input operands
2400 // or output values.
2402 // out64 = intrinsic-node in64
2404 // lo = copy (extract-element (in64, 0))
2405 // hi = copy (extract-element (in64, 1))
2406 // mips-specific-node
2409 // out64 = merge-values (v0, v1)
2411 static SDValue LowerDSPIntr(SDValue Op, SelectionDAG &DAG,
2412 unsigned Opc, bool HasI64In, bool HasI64Out) {
2413 DebugLoc DL = Op.getDebugLoc();
2414 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
2415 SDValue Chain = HasChainIn ? Op->getOperand(0) : DAG.getEntryNode();
2416 SmallVector<SDValue, 3> Ops;
2419 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2420 Op->getOperand(1 + HasChainIn),
2421 DAG.getConstant(0, MVT::i32));
2422 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2423 Op->getOperand(1 + HasChainIn),
2424 DAG.getConstant(1, MVT::i32));
2426 Chain = DAG.getCopyToReg(Chain, DL, Mips::LO, InLo, SDValue());
2427 Chain = DAG.getCopyToReg(Chain, DL, Mips::HI, InHi, Chain.getValue(1));
2429 Ops.push_back(Chain);
2430 Ops.append(Op->op_begin() + HasChainIn + 2, Op->op_end());
2431 Ops.push_back(Chain.getValue(1));
2433 Ops.push_back(Chain);
2434 Ops.append(Op->op_begin() + HasChainIn + 1, Op->op_end());
2438 return DAG.getNode(Opc, DL, Op->value_begin(), Op->getNumValues(),
2439 Ops.begin(), Ops.size());
2441 SDValue Intr = DAG.getNode(Opc, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2442 Ops.begin(), Ops.size());
2443 SDValue OutLo = DAG.getCopyFromReg(Intr.getValue(0), DL, Mips::LO, MVT::i32,
2445 SDValue OutHi = DAG.getCopyFromReg(OutLo.getValue(1), DL, Mips::HI, MVT::i32,
2447 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2452 SDValue Vals[] = { Out, OutHi.getValue(1) };
2453 return DAG.getMergeValues(Vals, 2, DL);
2456 SDValue MipsTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2457 SelectionDAG &DAG) const {
2458 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
2461 case Intrinsic::mips_shilo:
2462 return LowerDSPIntr(Op, DAG, MipsISD::SHILO, true, true);
2463 case Intrinsic::mips_dpau_h_qbl:
2464 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL, true, true);
2465 case Intrinsic::mips_dpau_h_qbr:
2466 return LowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR, true, true);
2467 case Intrinsic::mips_dpsu_h_qbl:
2468 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL, true, true);
2469 case Intrinsic::mips_dpsu_h_qbr:
2470 return LowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR, true, true);
2471 case Intrinsic::mips_dpa_w_ph:
2472 return LowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH, true, true);
2473 case Intrinsic::mips_dps_w_ph:
2474 return LowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH, true, true);
2475 case Intrinsic::mips_dpax_w_ph:
2476 return LowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH, true, true);
2477 case Intrinsic::mips_dpsx_w_ph:
2478 return LowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH, true, true);
2479 case Intrinsic::mips_mulsa_w_ph:
2480 return LowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH, true, true);
2481 case Intrinsic::mips_mult:
2482 return LowerDSPIntr(Op, DAG, MipsISD::MULT, false, true);
2483 case Intrinsic::mips_multu:
2484 return LowerDSPIntr(Op, DAG, MipsISD::MULTU, false, true);
2485 case Intrinsic::mips_madd:
2486 return LowerDSPIntr(Op, DAG, MipsISD::MADD_DSP, true, true);
2487 case Intrinsic::mips_maddu:
2488 return LowerDSPIntr(Op, DAG, MipsISD::MADDU_DSP, true, true);
2489 case Intrinsic::mips_msub:
2490 return LowerDSPIntr(Op, DAG, MipsISD::MSUB_DSP, true, true);
2491 case Intrinsic::mips_msubu:
2492 return LowerDSPIntr(Op, DAG, MipsISD::MSUBU_DSP, true, true);
2496 SDValue MipsTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2497 SelectionDAG &DAG) const {
2498 switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
2501 case Intrinsic::mips_extp:
2502 return LowerDSPIntr(Op, DAG, MipsISD::EXTP, true, false);
2503 case Intrinsic::mips_extpdp:
2504 return LowerDSPIntr(Op, DAG, MipsISD::EXTPDP, true, false);
2505 case Intrinsic::mips_extr_w:
2506 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_W, true, false);
2507 case Intrinsic::mips_extr_r_w:
2508 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W, true, false);
2509 case Intrinsic::mips_extr_rs_w:
2510 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W, true, false);
2511 case Intrinsic::mips_extr_s_h:
2512 return LowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H, true, false);
2513 case Intrinsic::mips_mthlip:
2514 return LowerDSPIntr(Op, DAG, MipsISD::MTHLIP, true, true);
2515 case Intrinsic::mips_mulsaq_s_w_ph:
2516 return LowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH, true, true);
2517 case Intrinsic::mips_maq_s_w_phl:
2518 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL, true, true);
2519 case Intrinsic::mips_maq_s_w_phr:
2520 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR, true, true);
2521 case Intrinsic::mips_maq_sa_w_phl:
2522 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL, true, true);
2523 case Intrinsic::mips_maq_sa_w_phr:
2524 return LowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR, true, true);
2525 case Intrinsic::mips_dpaq_s_w_ph:
2526 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH, true, true);
2527 case Intrinsic::mips_dpsq_s_w_ph:
2528 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH, true, true);
2529 case Intrinsic::mips_dpaq_sa_l_w:
2530 return LowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W, true, true);
2531 case Intrinsic::mips_dpsq_sa_l_w:
2532 return LowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W, true, true);
2533 case Intrinsic::mips_dpaqx_s_w_ph:
2534 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH, true, true);
2535 case Intrinsic::mips_dpaqx_sa_w_ph:
2536 return LowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH, true, true);
2537 case Intrinsic::mips_dpsqx_s_w_ph:
2538 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH, true, true);
2539 case Intrinsic::mips_dpsqx_sa_w_ph:
2540 return LowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH, true, true);
2544 //===----------------------------------------------------------------------===//
2545 // Calling Convention Implementation
2546 //===----------------------------------------------------------------------===//
2548 //===----------------------------------------------------------------------===//
2549 // TODO: Implement a generic logic using tblgen that can support this.
2550 // Mips O32 ABI rules:
2552 // i32 - Passed in A0, A1, A2, A3 and stack
2553 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2554 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2555 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2556 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2557 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
2560 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2561 //===----------------------------------------------------------------------===//
2563 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2564 MVT LocVT, CCValAssign::LocInfo LocInfo,
2565 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2567 static const unsigned IntRegsSize=4, FloatRegsSize=2;
2569 static const uint16_t IntRegs[] = {
2570 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2572 static const uint16_t F32Regs[] = {
2573 Mips::F12, Mips::F14
2575 static const uint16_t F64Regs[] = {
2579 // Do not process byval args here.
2580 if (ArgFlags.isByVal())
2583 // Promote i8 and i16
2584 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2586 if (ArgFlags.isSExt())
2587 LocInfo = CCValAssign::SExt;
2588 else if (ArgFlags.isZExt())
2589 LocInfo = CCValAssign::ZExt;
2591 LocInfo = CCValAssign::AExt;
2596 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2597 // is true: function is vararg, argument is 3rd or higher, there is previous
2598 // argument which is not f32 or f64.
2599 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2600 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2601 unsigned OrigAlign = ArgFlags.getOrigAlign();
2602 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2604 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2605 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2606 // If this is the first part of an i64 arg,
2607 // the allocated register must be either A0 or A2.
2608 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2609 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2611 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2612 // Allocate int register and shadow next int register. If first
2613 // available register is Mips::A1 or Mips::A3, shadow it too.
2614 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2615 if (Reg == Mips::A1 || Reg == Mips::A3)
2616 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2617 State.AllocateReg(IntRegs, IntRegsSize);
2619 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2620 // we are guaranteed to find an available float register
2621 if (ValVT == MVT::f32) {
2622 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2623 // Shadow int register
2624 State.AllocateReg(IntRegs, IntRegsSize);
2626 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2627 // Shadow int registers
2628 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2629 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2630 State.AllocateReg(IntRegs, IntRegsSize);
2631 State.AllocateReg(IntRegs, IntRegsSize);
2634 llvm_unreachable("Cannot handle this ValVT.");
2637 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2639 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2641 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2646 #include "MipsGenCallingConv.inc"
2648 //===----------------------------------------------------------------------===//
2649 // Call Calling Convention Implementation
2650 //===----------------------------------------------------------------------===//
2652 static const unsigned O32IntRegsSize = 4;
2654 // Return next O32 integer argument register.
2655 static unsigned getNextIntArgReg(unsigned Reg) {
2656 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2657 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2660 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2661 /// for tail call optimization.
2662 bool MipsTargetLowering::
2663 IsEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
2664 unsigned NextStackOffset,
2665 const MipsFunctionInfo& FI) const {
2666 if (!EnableMipsTailCalls)
2669 // No tail call optimization for mips16.
2670 if (Subtarget->inMips16Mode())
2673 // Return false if either the callee or caller has a byval argument.
2674 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
2677 // Return true if the callee's argument area is no larger than the
2679 return NextStackOffset <= FI.getIncomingArgSize();
2683 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2684 SDValue Chain, SDValue Arg, DebugLoc DL,
2685 bool IsTailCall, SelectionDAG &DAG) const {
2687 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2688 DAG.getIntPtrConstant(Offset));
2689 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2693 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2694 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2695 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2696 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2697 /*isVolatile=*/ true, false, 0);
2700 /// LowerCall - functions arguments are copied from virtual regs to
2701 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2703 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2704 SmallVectorImpl<SDValue> &InVals) const {
2705 SelectionDAG &DAG = CLI.DAG;
2706 DebugLoc &dl = CLI.DL;
2707 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2708 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2709 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2710 SDValue Chain = CLI.Chain;
2711 SDValue Callee = CLI.Callee;
2712 bool &isTailCall = CLI.IsTailCall;
2713 CallingConv::ID CallConv = CLI.CallConv;
2714 bool isVarArg = CLI.IsVarArg;
2716 MachineFunction &MF = DAG.getMachineFunction();
2717 MachineFrameInfo *MFI = MF.getFrameInfo();
2718 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2719 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2721 // Analyze operands of the call, assigning locations to each operand.
2722 SmallVector<CCValAssign, 16> ArgLocs;
2723 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2724 getTargetMachine(), ArgLocs, *DAG.getContext());
2725 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo);
2727 MipsCCInfo.analyzeCallOperands(Outs);
2729 // Get a count of how many bytes are to be pushed on the stack.
2730 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2732 // Check if it's really possible to do a tail call.
2735 IsEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
2736 *MF.getInfo<MipsFunctionInfo>());
2741 // Chain is the output chain of the last Load/Store or CopyToReg node.
2742 // ByValChain is the output chain of the last Memcpy node created for copying
2743 // byval arguments to the stack.
2744 unsigned StackAlignment = TFL->getStackAlignment();
2745 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2746 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2749 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal);
2751 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl,
2752 IsN64 ? Mips::SP_64 : Mips::SP,
2755 // With EABI is it possible to have 16 args on registers.
2756 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2757 SmallVector<SDValue, 8> MemOpChains;
2758 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2760 // Walk the register/memloc assignments, inserting copies/loads.
2761 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2762 SDValue Arg = OutVals[i];
2763 CCValAssign &VA = ArgLocs[i];
2764 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2765 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2768 if (Flags.isByVal()) {
2769 assert(Flags.getByValSize() &&
2770 "ByVal args of size 0 should have been ignored by front-end.");
2771 assert(ByValArg != MipsCCInfo.byval_end());
2772 assert(!isTailCall &&
2773 "Do not tail-call optimize if there is a byval argument.");
2774 passByValArg(Chain, dl, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2775 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
2780 // Promote the value if needed.
2781 switch (VA.getLocInfo()) {
2782 default: llvm_unreachable("Unknown loc info!");
2783 case CCValAssign::Full:
2784 if (VA.isRegLoc()) {
2785 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2786 (ValVT == MVT::f64 && LocVT == MVT::i64))
2787 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2788 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2789 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2790 Arg, DAG.getConstant(0, MVT::i32));
2791 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2792 Arg, DAG.getConstant(1, MVT::i32));
2793 if (!Subtarget->isLittle())
2795 unsigned LocRegLo = VA.getLocReg();
2796 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2797 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2798 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2803 case CCValAssign::SExt:
2804 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
2806 case CCValAssign::ZExt:
2807 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
2809 case CCValAssign::AExt:
2810 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
2814 // Arguments that can be passed on register must be kept at
2815 // RegsToPass vector
2816 if (VA.isRegLoc()) {
2817 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2821 // Register can't get to this point...
2822 assert(VA.isMemLoc());
2824 // emit ISD::STORE whichs stores the
2825 // parameter value to a stack Location
2826 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2827 Chain, Arg, dl, isTailCall, DAG));
2830 // Transform all store nodes into one single node because all store
2831 // nodes are independent of each other.
2832 if (!MemOpChains.empty())
2833 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2834 &MemOpChains[0], MemOpChains.size());
2836 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2837 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2838 // node so that legalize doesn't hack it.
2839 unsigned char OpFlag;
2840 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2841 bool GlobalOrExternal = false;
2844 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2845 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2846 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2847 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2848 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2850 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
2853 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
2854 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2855 getPointerTy(), 0, OpFlag);
2858 GlobalOrExternal = true;
2860 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2861 if (IsN64 || (!IsO32 && IsPIC))
2862 OpFlag = MipsII::MO_GOT_DISP;
2863 else if (!IsPIC) // !N64 && static
2864 OpFlag = MipsII::MO_NO_FLAG;
2866 OpFlag = MipsII::MO_GOT_CALL;
2867 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2869 GlobalOrExternal = true;
2874 // Create nodes that load address of callee and copy it to T9
2876 if (GlobalOrExternal) {
2877 // Load callee address
2878 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
2879 GetGlobalReg(DAG, getPointerTy()), Callee);
2880 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2881 Callee, MachinePointerInfo::getGOT(),
2882 false, false, false, 0);
2884 // Use GOT+LO if callee has internal linkage.
2885 if (CalleeLo.getNode()) {
2886 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2887 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
2893 // T9 register operand.
2896 // T9 should contain the address of the callee function if
2897 // -reloction-model=pic or it is an indirect call.
2898 if (IsPICCall || !GlobalOrExternal) {
2900 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2901 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
2902 InFlag = Chain.getValue(1);
2904 if (Subtarget->inMips16Mode())
2905 T9 = DAG.getRegister(T9Reg, getPointerTy());
2907 Callee = DAG.getRegister(T9Reg, getPointerTy());
2910 // Insert node "GP copy globalreg" before call to function.
2911 // Lazy-binding stubs require GP to point to the GOT.
2913 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2914 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2915 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
2918 // Build a sequence of copy-to-reg nodes chained together with token
2919 // chain and flag operands which copy the outgoing args into registers.
2920 // The InFlag in necessary since all emitted instructions must be
2922 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2923 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2924 RegsToPass[i].second, InFlag);
2925 InFlag = Chain.getValue(1);
2928 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
2929 // = Chain, Callee, Reg#1, Reg#2, ...
2931 // Returns a chain & a flag for retval copy to use.
2932 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2933 SmallVector<SDValue, 8> Ops;
2934 Ops.push_back(Chain);
2935 Ops.push_back(Callee);
2937 // Add argument registers to the end of the list so that they are
2938 // known live into the call.
2939 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2940 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2941 RegsToPass[i].second.getValueType()));
2943 // Add T9 register operand.
2947 // Add a register mask operand representing the call-preserved registers.
2948 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2949 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2950 assert(Mask && "Missing call preserved mask for calling convention");
2951 Ops.push_back(DAG.getRegisterMask(Mask));
2953 if (InFlag.getNode())
2954 Ops.push_back(InFlag);
2957 return DAG.getNode(MipsISD::TailCall, dl, MVT::Other, &Ops[0], Ops.size());
2959 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
2960 InFlag = Chain.getValue(1);
2962 // Create the CALLSEQ_END node.
2963 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2964 DAG.getIntPtrConstant(0, true), InFlag);
2965 InFlag = Chain.getValue(1);
2967 // Handle result values, copying them out of physregs into vregs that we
2969 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2970 Ins, dl, DAG, InVals);
2973 /// LowerCallResult - Lower the result values of a call into the
2974 /// appropriate copies out of appropriate physical registers.
2976 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2977 CallingConv::ID CallConv, bool isVarArg,
2978 const SmallVectorImpl<ISD::InputArg> &Ins,
2979 DebugLoc dl, SelectionDAG &DAG,
2980 SmallVectorImpl<SDValue> &InVals) const {
2981 // Assign locations to each value returned by this call.
2982 SmallVector<CCValAssign, 16> RVLocs;
2983 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2984 getTargetMachine(), RVLocs, *DAG.getContext());
2986 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
2988 // Copy all of the result registers out of their specified physreg.
2989 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2990 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
2991 RVLocs[i].getValVT(), InFlag).getValue(1);
2992 InFlag = Chain.getValue(2);
2993 InVals.push_back(Chain.getValue(0));
2999 //===----------------------------------------------------------------------===//
3000 // Formal Arguments Calling Convention Implementation
3001 //===----------------------------------------------------------------------===//
3002 /// LowerFormalArguments - transform physical registers into virtual registers
3003 /// and generate load operations for arguments places on the stack.
3005 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
3006 CallingConv::ID CallConv,
3008 const SmallVectorImpl<ISD::InputArg> &Ins,
3009 DebugLoc dl, SelectionDAG &DAG,
3010 SmallVectorImpl<SDValue> &InVals)
3012 MachineFunction &MF = DAG.getMachineFunction();
3013 MachineFrameInfo *MFI = MF.getFrameInfo();
3014 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3016 MipsFI->setVarArgsFrameIndex(0);
3018 // Used with vargs to acumulate store chains.
3019 std::vector<SDValue> OutChains;
3021 // Assign locations to all of the incoming arguments.
3022 SmallVector<CCValAssign, 16> ArgLocs;
3023 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3024 getTargetMachine(), ArgLocs, *DAG.getContext());
3025 MipsCC MipsCCInfo(CallConv, isVarArg, IsO32, CCInfo);
3027 MipsCCInfo.analyzeFormalArguments(Ins);
3028 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3029 MipsCCInfo.hasByValArg());
3031 Function::const_arg_iterator FuncArg =
3032 DAG.getMachineFunction().getFunction()->arg_begin();
3033 unsigned CurArgIdx = 0;
3034 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
3036 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3037 CCValAssign &VA = ArgLocs[i];
3038 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
3039 CurArgIdx = Ins[i].OrigArgIndex;
3040 EVT ValVT = VA.getValVT();
3041 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3042 bool IsRegLoc = VA.isRegLoc();
3044 if (Flags.isByVal()) {
3045 assert(Flags.getByValSize() &&
3046 "ByVal args of size 0 should have been ignored by front-end.");
3047 assert(ByValArg != MipsCCInfo.byval_end());
3048 copyByValRegs(Chain, dl, OutChains, DAG, Flags, InVals, &*FuncArg,
3049 MipsCCInfo, *ByValArg);
3054 // Arguments stored on registers
3056 EVT RegVT = VA.getLocVT();
3057 unsigned ArgReg = VA.getLocReg();
3058 const TargetRegisterClass *RC;
3060 if (RegVT == MVT::i32)
3061 RC = &Mips::CPURegsRegClass;
3062 else if (RegVT == MVT::i64)
3063 RC = &Mips::CPU64RegsRegClass;
3064 else if (RegVT == MVT::f32)
3065 RC = &Mips::FGR32RegClass;
3066 else if (RegVT == MVT::f64)
3067 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
3069 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3071 // Transform the arguments stored on
3072 // physical registers into virtual ones
3073 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3074 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3076 // If this is an 8 or 16-bit value, it has been passed promoted
3077 // to 32 bits. Insert an assert[sz]ext to capture this, then
3078 // truncate to the right size.
3079 if (VA.getLocInfo() != CCValAssign::Full) {
3080 unsigned Opcode = 0;
3081 if (VA.getLocInfo() == CCValAssign::SExt)
3082 Opcode = ISD::AssertSext;
3083 else if (VA.getLocInfo() == CCValAssign::ZExt)
3084 Opcode = ISD::AssertZext;
3086 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3087 DAG.getValueType(ValVT));
3088 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
3091 // Handle floating point arguments passed in integer registers.
3092 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3093 (RegVT == MVT::i64 && ValVT == MVT::f64))
3094 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
3095 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
3096 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
3097 getNextIntArgReg(ArgReg), RC);
3098 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
3099 if (!Subtarget->isLittle())
3100 std::swap(ArgValue, ArgValue2);
3101 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
3102 ArgValue, ArgValue2);
3105 InVals.push_back(ArgValue);
3106 } else { // VA.isRegLoc()
3109 assert(VA.isMemLoc());
3111 // The stack pointer offset is relative to the caller stack frame.
3112 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
3113 VA.getLocMemOffset(), true);
3115 // Create load nodes to retrieve arguments from the stack
3116 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3117 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
3118 MachinePointerInfo::getFixedStack(FI),
3119 false, false, false, 0));
3123 // The mips ABIs for returning structs by value requires that we copy
3124 // the sret argument into $v0 for the return. Save the argument into
3125 // a virtual register so that we can access it from the return points.
3126 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3127 unsigned Reg = MipsFI->getSRetReturnReg();
3129 Reg = MF.getRegInfo().
3130 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
3131 MipsFI->setSRetReturnReg(Reg);
3133 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
3134 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
3138 writeVarArgRegs(OutChains, MipsCCInfo, Chain, dl, DAG);
3140 // All stores are grouped in one node to allow the matching between
3141 // the size of Ins and InVals. This only happens when on varg functions
3142 if (!OutChains.empty()) {
3143 OutChains.push_back(Chain);
3144 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3145 &OutChains[0], OutChains.size());
3151 //===----------------------------------------------------------------------===//
3152 // Return Value Calling Convention Implementation
3153 //===----------------------------------------------------------------------===//
3156 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3157 MachineFunction &MF, bool isVarArg,
3158 const SmallVectorImpl<ISD::OutputArg> &Outs,
3159 LLVMContext &Context) const {
3160 SmallVector<CCValAssign, 16> RVLocs;
3161 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3163 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3167 MipsTargetLowering::LowerReturn(SDValue Chain,
3168 CallingConv::ID CallConv, bool isVarArg,
3169 const SmallVectorImpl<ISD::OutputArg> &Outs,
3170 const SmallVectorImpl<SDValue> &OutVals,
3171 DebugLoc dl, SelectionDAG &DAG) const {
3173 // CCValAssign - represent the assignment of
3174 // the return value to a location
3175 SmallVector<CCValAssign, 16> RVLocs;
3177 // CCState - Info about the registers and stack slot.
3178 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3179 getTargetMachine(), RVLocs, *DAG.getContext());
3181 // Analize return values.
3182 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3184 // If this is the first return lowered for this function, add
3185 // the regs to the liveout set for the function.
3186 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3187 for (unsigned i = 0; i != RVLocs.size(); ++i)
3188 if (RVLocs[i].isRegLoc())
3189 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3194 // Copy the result values into the output registers.
3195 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3196 CCValAssign &VA = RVLocs[i];
3197 assert(VA.isRegLoc() && "Can only return in registers!");
3199 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
3201 // guarantee that all emitted copies are
3202 // stuck together, avoiding something bad
3203 Flag = Chain.getValue(1);
3206 // The mips ABIs for returning structs by value requires that we copy
3207 // the sret argument into $v0 for the return. We saved the argument into
3208 // a virtual register in the entry block, so now we copy the value out
3210 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3211 MachineFunction &MF = DAG.getMachineFunction();
3212 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3213 unsigned Reg = MipsFI->getSRetReturnReg();
3216 llvm_unreachable("sret virtual register not created in the entry block");
3217 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
3218 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
3220 Chain = DAG.getCopyToReg(Chain, dl, V0, Val, Flag);
3221 Flag = Chain.getValue(1);
3222 MF.getRegInfo().addLiveOut(V0);
3225 // Return on Mips is always a "jr $ra"
3227 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain, Flag);
3230 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, Chain);
3233 //===----------------------------------------------------------------------===//
3234 // Mips Inline Assembly Support
3235 //===----------------------------------------------------------------------===//
3237 /// getConstraintType - Given a constraint letter, return the type of
3238 /// constraint it is for this target.
3239 MipsTargetLowering::ConstraintType MipsTargetLowering::
3240 getConstraintType(const std::string &Constraint) const
3242 // Mips specific constrainy
3243 // GCC config/mips/constraints.md
3245 // 'd' : An address register. Equivalent to r
3246 // unless generating MIPS16 code.
3247 // 'y' : Equivalent to r; retained for
3248 // backwards compatibility.
3249 // 'c' : A register suitable for use in an indirect
3250 // jump. This will always be $25 for -mabicalls.
3251 // 'l' : The lo register. 1 word storage.
3252 // 'x' : The hilo register pair. Double word storage.
3253 if (Constraint.size() == 1) {
3254 switch (Constraint[0]) {
3262 return C_RegisterClass;
3265 return TargetLowering::getConstraintType(Constraint);
3268 /// Examine constraint type and operand type and determine a weight value.
3269 /// This object must already have been set up with the operand type
3270 /// and the current alternative constraint selected.
3271 TargetLowering::ConstraintWeight
3272 MipsTargetLowering::getSingleConstraintMatchWeight(
3273 AsmOperandInfo &info, const char *constraint) const {
3274 ConstraintWeight weight = CW_Invalid;
3275 Value *CallOperandVal = info.CallOperandVal;
3276 // If we don't have a value, we can't do a match,
3277 // but allow it at the lowest weight.
3278 if (CallOperandVal == NULL)
3280 Type *type = CallOperandVal->getType();
3281 // Look at the constraint type.
3282 switch (*constraint) {
3284 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3288 if (type->isIntegerTy())
3289 weight = CW_Register;
3292 if (type->isFloatTy())
3293 weight = CW_Register;
3295 case 'c': // $25 for indirect jumps
3296 case 'l': // lo register
3297 case 'x': // hilo register pair
3298 if (type->isIntegerTy())
3299 weight = CW_SpecificReg;
3301 case 'I': // signed 16 bit immediate
3302 case 'J': // integer zero
3303 case 'K': // unsigned 16 bit immediate
3304 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3305 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3306 case 'O': // signed 15 bit immediate (+- 16383)
3307 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3308 if (isa<ConstantInt>(CallOperandVal))
3309 weight = CW_Constant;
3315 /// Given a register class constraint, like 'r', if this corresponds directly
3316 /// to an LLVM register class, return a register of 0 and the register class
3318 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
3319 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
3321 if (Constraint.size() == 1) {
3322 switch (Constraint[0]) {
3323 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3324 case 'y': // Same as 'r'. Exists for compatibility.
3326 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3327 if (Subtarget->inMips16Mode())
3328 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3329 return std::make_pair(0U, &Mips::CPURegsRegClass);
3331 if (VT == MVT::i64 && !HasMips64)
3332 return std::make_pair(0U, &Mips::CPURegsRegClass);
3333 if (VT == MVT::i64 && HasMips64)
3334 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3335 // This will generate an error message
3336 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3339 return std::make_pair(0U, &Mips::FGR32RegClass);
3340 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3341 if (Subtarget->isFP64bit())
3342 return std::make_pair(0U, &Mips::FGR64RegClass);
3343 return std::make_pair(0U, &Mips::AFGR64RegClass);
3346 case 'c': // register suitable for indirect jump
3348 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3349 assert(VT == MVT::i64 && "Unexpected type.");
3350 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
3351 case 'l': // register suitable for indirect jump
3353 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3354 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
3355 case 'x': // register suitable for indirect jump
3356 // Fixme: Not triggering the use of both hi and low
3357 // This will generate an error message
3358 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3361 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3364 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3365 /// vector. If it is invalid, don't add anything to Ops.
3366 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3367 std::string &Constraint,
3368 std::vector<SDValue>&Ops,
3369 SelectionDAG &DAG) const {
3370 SDValue Result(0, 0);
3372 // Only support length 1 constraints for now.
3373 if (Constraint.length() > 1) return;
3375 char ConstraintLetter = Constraint[0];
3376 switch (ConstraintLetter) {
3377 default: break; // This will fall through to the generic implementation
3378 case 'I': // Signed 16 bit constant
3379 // If this fails, the parent routine will give an error
3380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3381 EVT Type = Op.getValueType();
3382 int64_t Val = C->getSExtValue();
3383 if (isInt<16>(Val)) {
3384 Result = DAG.getTargetConstant(Val, Type);
3389 case 'J': // integer zero
3390 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3391 EVT Type = Op.getValueType();
3392 int64_t Val = C->getZExtValue();
3394 Result = DAG.getTargetConstant(0, Type);
3399 case 'K': // unsigned 16 bit immediate
3400 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3401 EVT Type = Op.getValueType();
3402 uint64_t Val = (uint64_t)C->getZExtValue();
3403 if (isUInt<16>(Val)) {
3404 Result = DAG.getTargetConstant(Val, Type);
3409 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3410 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3411 EVT Type = Op.getValueType();
3412 int64_t Val = C->getSExtValue();
3413 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3414 Result = DAG.getTargetConstant(Val, Type);
3419 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3420 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3421 EVT Type = Op.getValueType();
3422 int64_t Val = C->getSExtValue();
3423 if ((Val >= -65535) && (Val <= -1)) {
3424 Result = DAG.getTargetConstant(Val, Type);
3429 case 'O': // signed 15 bit immediate
3430 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3431 EVT Type = Op.getValueType();
3432 int64_t Val = C->getSExtValue();
3433 if ((isInt<15>(Val))) {
3434 Result = DAG.getTargetConstant(Val, Type);
3439 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3441 EVT Type = Op.getValueType();
3442 int64_t Val = C->getSExtValue();
3443 if ((Val <= 65535) && (Val >= 1)) {
3444 Result = DAG.getTargetConstant(Val, Type);
3451 if (Result.getNode()) {
3452 Ops.push_back(Result);
3456 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3460 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3461 // The Mips target isn't yet aware of offsets.
3465 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3466 unsigned SrcAlign, bool IsZeroVal,
3468 MachineFunction &MF) const {
3469 if (Subtarget->hasMips64())
3475 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3476 if (VT != MVT::f32 && VT != MVT::f64)
3478 if (Imm.isNegZero())
3480 return Imm.isZero();
3483 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3485 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3487 return TargetLowering::getJumpTableEncoding();
3490 MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CallConv, bool IsVarArg,
3491 bool IsO32, CCState &Info) : CCInfo(Info) {
3492 UseRegsForByval = true;
3496 NumIntArgRegs = array_lengthof(O32IntRegs);
3497 ReservedArgArea = 16;
3498 IntArgRegs = ShadowRegs = O32IntRegs;
3499 FixedFn = VarFn = CC_MipsO32;
3502 NumIntArgRegs = array_lengthof(Mips64IntRegs);
3503 ReservedArgArea = 0;
3504 IntArgRegs = Mips64IntRegs;
3505 ShadowRegs = Mips64DPRegs;
3507 VarFn = CC_MipsN_VarArg;
3510 if (CallConv == CallingConv::Fast) {
3512 UseRegsForByval = false;
3513 ReservedArgArea = 0;
3514 FixedFn = VarFn = CC_Mips_FastCC;
3517 // Pre-allocate reserved argument area.
3518 CCInfo.AllocateStack(ReservedArgArea, 1);
3521 void MipsTargetLowering::MipsCC::
3522 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args) {
3523 unsigned NumOpnds = Args.size();
3525 for (unsigned I = 0; I != NumOpnds; ++I) {
3526 MVT ArgVT = Args[I].VT;
3527 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3530 if (ArgFlags.isByVal()) {
3531 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3535 if (Args[I].IsFixed)
3536 R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3538 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3542 dbgs() << "Call operand #" << I << " has unhandled type "
3543 << EVT(ArgVT).getEVTString();
3545 llvm_unreachable(0);
3550 void MipsTargetLowering::MipsCC::
3551 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args) {
3552 unsigned NumArgs = Args.size();
3554 for (unsigned I = 0; I != NumArgs; ++I) {
3555 MVT ArgVT = Args[I].VT;
3556 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3558 if (ArgFlags.isByVal()) {
3559 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3563 if (!FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
3567 dbgs() << "Formal Arg #" << I << " has unhandled type "
3568 << EVT(ArgVT).getEVTString();
3570 llvm_unreachable(0);
3575 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
3577 CCValAssign::LocInfo LocInfo,
3578 ISD::ArgFlagsTy ArgFlags) {
3579 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
3581 struct ByValArgInfo ByVal;
3582 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
3583 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
3586 if (UseRegsForByval)
3587 allocateRegs(ByVal, ByValSize, Align);
3589 // Allocate space on caller's stack.
3590 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
3592 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
3594 ByValArgs.push_back(ByVal);
3597 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
3600 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
3601 "Byval argument's size and alignment should be a multiple of"
3604 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
3606 // If Align > RegSize, the first arg register must be even.
3607 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
3608 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
3612 // Mark the registers allocated.
3613 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
3614 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
3615 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3618 void MipsTargetLowering::
3619 copyByValRegs(SDValue Chain, DebugLoc DL, std::vector<SDValue> &OutChains,
3620 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3621 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3622 const MipsCC &CC, const ByValArgInfo &ByVal) const {
3623 MachineFunction &MF = DAG.getMachineFunction();
3624 MachineFrameInfo *MFI = MF.getFrameInfo();
3625 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3626 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3630 FrameObjOffset = (int)CC.reservedArgArea() -
3631 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3633 FrameObjOffset = ByVal.Address;
3635 // Create frame object.
3636 EVT PtrTy = getPointerTy();
3637 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3638 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3639 InVals.push_back(FIN);
3644 // Copy arg registers.
3645 EVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3646 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3648 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
3649 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3650 unsigned VReg = AddLiveIn(MF, ArgReg, RC);
3651 unsigned Offset = I * CC.regSize();
3652 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3653 DAG.getConstant(Offset, PtrTy));
3654 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3655 StorePtr, MachinePointerInfo(FuncArg, Offset),
3657 OutChains.push_back(Store);
3661 // Copy byVal arg to registers and stack.
3662 void MipsTargetLowering::
3663 passByValArg(SDValue Chain, DebugLoc DL,
3664 SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
3665 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
3666 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
3667 const MipsCC &CC, const ByValArgInfo &ByVal,
3668 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3669 unsigned ByValSize = Flags.getByValSize();
3670 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
3671 unsigned RegSize = CC.regSize();
3672 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
3673 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
3675 if (ByVal.NumRegs) {
3676 const uint16_t *ArgRegs = CC.intArgRegs();
3677 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
3680 // Copy words to registers.
3681 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
3682 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3683 DAG.getConstant(Offset, PtrTy));
3684 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3685 MachinePointerInfo(), false, false, false,
3687 MemOpChains.push_back(LoadVal.getValue(1));
3688 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3689 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3692 // Return if the struct has been fully copied.
3693 if (ByValSize == Offset)
3696 // Copy the remainder of the byval argument with sub-word loads and shifts.
3697 if (LeftoverBytes) {
3698 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
3699 "Size of the remainder should be smaller than RegSize.");
3702 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
3703 Offset < ByValSize; LoadSize /= 2) {
3704 unsigned RemSize = ByValSize - Offset;
3706 if (RemSize < LoadSize)
3710 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3711 DAG.getConstant(Offset, PtrTy));
3713 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3714 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
3715 false, false, Alignment);
3716 MemOpChains.push_back(LoadVal.getValue(1));
3718 // Shift the loaded value.
3722 Shamt = TotalSizeLoaded;
3724 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
3726 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3727 DAG.getConstant(Shamt, MVT::i32));
3730 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3735 TotalSizeLoaded += LoadSize;
3736 Alignment = std::min(Alignment, LoadSize);
3739 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3740 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3745 // Copy remainder of byval arg to it with memcpy.
3746 unsigned MemCpySize = ByValSize - Offset;
3747 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3748 DAG.getConstant(Offset, PtrTy));
3749 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3750 DAG.getIntPtrConstant(ByVal.Address));
3751 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3752 DAG.getConstant(MemCpySize, PtrTy), Alignment,
3753 /*isVolatile=*/false, /*AlwaysInline=*/false,
3754 MachinePointerInfo(0), MachinePointerInfo(0));
3755 MemOpChains.push_back(Chain);
3759 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3760 const MipsCC &CC, SDValue Chain,
3761 DebugLoc DL, SelectionDAG &DAG) const {
3762 unsigned NumRegs = CC.numIntArgRegs();
3763 const uint16_t *ArgRegs = CC.intArgRegs();
3764 const CCState &CCInfo = CC.getCCInfo();
3765 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
3766 unsigned RegSize = CC.regSize();
3767 EVT RegTy = MVT::getIntegerVT(RegSize * 8);
3768 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3769 MachineFunction &MF = DAG.getMachineFunction();
3770 MachineFrameInfo *MFI = MF.getFrameInfo();
3771 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3773 // Offset of the first variable argument from stack pointer.
3777 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
3780 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
3782 // Record the frame index of the first variable argument
3783 // which is a value necessary to VASTART.
3784 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3785 MipsFI->setVarArgsFrameIndex(FI);
3787 // Copy the integer registers that have not been used for argument passing
3788 // to the argument register save area. For O32, the save area is allocated
3789 // in the caller's stack frame, while for N32/64, it is allocated in the
3790 // callee's stack frame.
3791 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
3792 unsigned Reg = AddLiveIn(MF, ArgRegs[I], RC);
3793 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3794 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3795 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3796 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3797 MachinePointerInfo(), false, false, 0);
3798 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
3799 OutChains.push_back(Store);