1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-lower"
15 #include "MipsISelLowering.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 STATISTIC(NumTailCalls, "Number of tail calls");
44 LargeGOT("mxgot", cl::Hidden,
45 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
48 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
49 cl::desc("MIPS: Don't trap on integer division by zero."),
52 static const uint16_t O32IntRegs[4] = {
53 Mips::A0, Mips::A1, Mips::A2, Mips::A3
56 static const uint16_t Mips64IntRegs[8] = {
57 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
58 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
61 static const uint16_t Mips64DPRegs[8] = {
62 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
63 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
66 // If I is a shifted mask, set the size (Size) and the first bit of the
67 // mask (Pos), and return true.
68 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
69 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
70 if (!isShiftedMask_64(I))
73 Size = CountPopulation_64(I);
74 Pos = countTrailingZeros(I);
78 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
79 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
80 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
83 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
84 EVT Ty = Op.getValueType();
86 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
87 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(Op), Ty, 0,
89 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
90 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
91 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
92 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
93 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
94 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
95 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
96 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
97 N->getOffset(), Flag);
99 llvm_unreachable("Unexpected node type.");
103 static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
105 EVT Ty = Op.getValueType();
106 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
107 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
108 return DAG.getNode(ISD::ADD, DL, Ty,
109 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
110 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
113 SDValue MipsTargetLowering::getAddrLocal(SDValue Op, SelectionDAG &DAG,
114 bool HasMips64) const {
116 EVT Ty = Op.getValueType();
117 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
118 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
119 getTargetNode(Op, DAG, GOTFlag));
120 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
121 MachinePointerInfo::getGOT(), false, false, false,
123 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
124 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
125 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
128 SDValue MipsTargetLowering::getAddrGlobal(SDValue Op, SelectionDAG &DAG,
129 unsigned Flag) const {
131 EVT Ty = Op.getValueType();
132 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
133 getTargetNode(Op, DAG, Flag));
134 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
135 MachinePointerInfo::getGOT(), false, false, false, 0);
138 SDValue MipsTargetLowering::getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
140 unsigned LoFlag) const {
142 EVT Ty = Op.getValueType();
143 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
144 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
145 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
146 getTargetNode(Op, DAG, LoFlag));
147 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
148 MachinePointerInfo::getGOT(), false, false, false, 0);
151 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
153 case MipsISD::JmpLink: return "MipsISD::JmpLink";
154 case MipsISD::TailCall: return "MipsISD::TailCall";
155 case MipsISD::Hi: return "MipsISD::Hi";
156 case MipsISD::Lo: return "MipsISD::Lo";
157 case MipsISD::GPRel: return "MipsISD::GPRel";
158 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
159 case MipsISD::Ret: return "MipsISD::Ret";
160 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
161 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
162 case MipsISD::FPCmp: return "MipsISD::FPCmp";
163 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
164 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
165 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
166 case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI";
167 case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI";
168 case MipsISD::Mult: return "MipsISD::Mult";
169 case MipsISD::Multu: return "MipsISD::Multu";
170 case MipsISD::MAdd: return "MipsISD::MAdd";
171 case MipsISD::MAddu: return "MipsISD::MAddu";
172 case MipsISD::MSub: return "MipsISD::MSub";
173 case MipsISD::MSubu: return "MipsISD::MSubu";
174 case MipsISD::DivRem: return "MipsISD::DivRem";
175 case MipsISD::DivRemU: return "MipsISD::DivRemU";
176 case MipsISD::DivRem16: return "MipsISD::DivRem16";
177 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
178 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
179 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
180 case MipsISD::Wrapper: return "MipsISD::Wrapper";
181 case MipsISD::Sync: return "MipsISD::Sync";
182 case MipsISD::Ext: return "MipsISD::Ext";
183 case MipsISD::Ins: return "MipsISD::Ins";
184 case MipsISD::LWL: return "MipsISD::LWL";
185 case MipsISD::LWR: return "MipsISD::LWR";
186 case MipsISD::SWL: return "MipsISD::SWL";
187 case MipsISD::SWR: return "MipsISD::SWR";
188 case MipsISD::LDL: return "MipsISD::LDL";
189 case MipsISD::LDR: return "MipsISD::LDR";
190 case MipsISD::SDL: return "MipsISD::SDL";
191 case MipsISD::SDR: return "MipsISD::SDR";
192 case MipsISD::EXTP: return "MipsISD::EXTP";
193 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
194 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
195 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
196 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
197 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
198 case MipsISD::SHILO: return "MipsISD::SHILO";
199 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
200 case MipsISD::MULT: return "MipsISD::MULT";
201 case MipsISD::MULTU: return "MipsISD::MULTU";
202 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
203 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
204 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
205 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
206 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
207 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
208 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
209 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
210 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
211 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
212 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
213 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
214 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
215 case MipsISD::VCEQ: return "MipsISD::VCEQ";
216 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
217 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
218 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
219 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
220 case MipsISD::VSMAX: return "MipsISD::VSMAX";
221 case MipsISD::VSMIN: return "MipsISD::VSMIN";
222 case MipsISD::VUMAX: return "MipsISD::VUMAX";
223 case MipsISD::VUMIN: return "MipsISD::VUMIN";
224 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
225 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
226 case MipsISD::VNOR: return "MipsISD::VNOR";
227 case MipsISD::VSHF: return "MipsISD::VSHF";
228 case MipsISD::SHF: return "MipsISD::SHF";
229 case MipsISD::ILVEV: return "MipsISD::ILVEV";
230 case MipsISD::ILVOD: return "MipsISD::ILVOD";
231 case MipsISD::ILVL: return "MipsISD::ILVL";
232 case MipsISD::ILVR: return "MipsISD::ILVR";
233 case MipsISD::PCKEV: return "MipsISD::PCKEV";
234 case MipsISD::PCKOD: return "MipsISD::PCKOD";
235 default: return NULL;
240 MipsTargetLowering(MipsTargetMachine &TM)
241 : TargetLowering(TM, new MipsTargetObjectFile()),
242 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
243 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
244 IsO32(Subtarget->isABI_O32()) {
245 // Mips does not have i1 type, so use i32 for
246 // setcc operations results (slt, sgt, ...).
247 setBooleanContents(ZeroOrOneBooleanContent);
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // Load extented operations for i1 types must be promoted
251 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
252 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
253 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
255 // MIPS doesn't have extending float->double load/store
256 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
257 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
259 // Used by legalize types to correctly generate the setcc result.
260 // Without this, every float setcc comes with a AND/OR with the result,
261 // we don't want this, since the fpcmp result goes to a flag register,
262 // which is used implicitly by brcond and select operations.
263 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
265 // Mips Custom Operations
266 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
267 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
268 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
269 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
270 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
271 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
272 setOperationAction(ISD::SELECT, MVT::f32, Custom);
273 setOperationAction(ISD::SELECT, MVT::f64, Custom);
274 setOperationAction(ISD::SELECT, MVT::i32, Custom);
275 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
276 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
277 setOperationAction(ISD::SETCC, MVT::f32, Custom);
278 setOperationAction(ISD::SETCC, MVT::f64, Custom);
279 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
280 setOperationAction(ISD::VASTART, MVT::Other, Custom);
281 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
283 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
285 if (!TM.Options.NoNaNsFPMath) {
286 setOperationAction(ISD::FABS, MVT::f32, Custom);
287 setOperationAction(ISD::FABS, MVT::f64, Custom);
291 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
292 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
293 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
294 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
295 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
296 setOperationAction(ISD::SELECT, MVT::i64, Custom);
297 setOperationAction(ISD::LOAD, MVT::i64, Custom);
298 setOperationAction(ISD::STORE, MVT::i64, Custom);
299 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
303 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
304 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
305 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
308 setOperationAction(ISD::ADD, MVT::i32, Custom);
310 setOperationAction(ISD::ADD, MVT::i64, Custom);
312 setOperationAction(ISD::SDIV, MVT::i32, Expand);
313 setOperationAction(ISD::SREM, MVT::i32, Expand);
314 setOperationAction(ISD::UDIV, MVT::i32, Expand);
315 setOperationAction(ISD::UREM, MVT::i32, Expand);
316 setOperationAction(ISD::SDIV, MVT::i64, Expand);
317 setOperationAction(ISD::SREM, MVT::i64, Expand);
318 setOperationAction(ISD::UDIV, MVT::i64, Expand);
319 setOperationAction(ISD::UREM, MVT::i64, Expand);
321 // Operations not directly supported by Mips.
322 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
323 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
324 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
325 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
326 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
327 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
328 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
329 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
330 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
331 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
332 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
333 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
334 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
335 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
337 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
339 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
340 setOperationAction(ISD::ROTL, MVT::i32, Expand);
341 setOperationAction(ISD::ROTL, MVT::i64, Expand);
342 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
343 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
345 if (!Subtarget->hasMips32r2())
346 setOperationAction(ISD::ROTR, MVT::i32, Expand);
348 if (!Subtarget->hasMips64r2())
349 setOperationAction(ISD::ROTR, MVT::i64, Expand);
351 setOperationAction(ISD::FSIN, MVT::f32, Expand);
352 setOperationAction(ISD::FSIN, MVT::f64, Expand);
353 setOperationAction(ISD::FCOS, MVT::f32, Expand);
354 setOperationAction(ISD::FCOS, MVT::f64, Expand);
355 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
356 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
357 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
358 setOperationAction(ISD::FPOW, MVT::f32, Expand);
359 setOperationAction(ISD::FPOW, MVT::f64, Expand);
360 setOperationAction(ISD::FLOG, MVT::f32, Expand);
361 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
362 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
363 setOperationAction(ISD::FEXP, MVT::f32, Expand);
364 setOperationAction(ISD::FMA, MVT::f32, Expand);
365 setOperationAction(ISD::FMA, MVT::f64, Expand);
366 setOperationAction(ISD::FREM, MVT::f32, Expand);
367 setOperationAction(ISD::FREM, MVT::f64, Expand);
369 if (!TM.Options.NoNaNsFPMath) {
370 setOperationAction(ISD::FNEG, MVT::f32, Expand);
371 setOperationAction(ISD::FNEG, MVT::f64, Expand);
374 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
376 setOperationAction(ISD::VAARG, MVT::Other, Expand);
377 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
378 setOperationAction(ISD::VAEND, MVT::Other, Expand);
380 // Use the default for now
381 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
382 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
384 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
385 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
386 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
387 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
389 setInsertFencesForAtomic(true);
391 if (!Subtarget->hasSEInReg()) {
392 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
393 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
396 if (!Subtarget->hasBitCount()) {
397 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
398 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
401 if (!Subtarget->hasSwap()) {
402 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
403 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
407 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
408 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
409 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
410 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
413 setOperationAction(ISD::TRAP, MVT::Other, Legal);
415 setTargetDAGCombine(ISD::SDIVREM);
416 setTargetDAGCombine(ISD::UDIVREM);
417 setTargetDAGCombine(ISD::SELECT);
418 setTargetDAGCombine(ISD::AND);
419 setTargetDAGCombine(ISD::OR);
420 setTargetDAGCombine(ISD::ADD);
422 setMinFunctionAlignment(HasMips64 ? 3 : 2);
424 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
426 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
427 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
429 MaxStoresPerMemcpy = 16;
432 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
433 if (TM.getSubtargetImpl()->inMips16Mode())
434 return llvm::createMips16TargetLowering(TM);
436 return llvm::createMipsSETargetLowering(TM);
439 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
442 return VT.changeVectorElementTypeToInteger();
445 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
446 TargetLowering::DAGCombinerInfo &DCI,
447 const MipsSubtarget *Subtarget) {
448 if (DCI.isBeforeLegalizeOps())
451 EVT Ty = N->getValueType(0);
452 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
453 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
454 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
458 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
459 N->getOperand(0), N->getOperand(1));
460 SDValue InChain = DAG.getEntryNode();
461 SDValue InGlue = DivRem;
464 if (N->hasAnyUseOfValue(0)) {
465 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
467 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
468 InChain = CopyFromLo.getValue(1);
469 InGlue = CopyFromLo.getValue(2);
473 if (N->hasAnyUseOfValue(1)) {
474 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
476 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
482 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
484 default: llvm_unreachable("Unknown fp condition code!");
486 case ISD::SETOEQ: return Mips::FCOND_OEQ;
487 case ISD::SETUNE: return Mips::FCOND_UNE;
489 case ISD::SETOLT: return Mips::FCOND_OLT;
491 case ISD::SETOGT: return Mips::FCOND_OGT;
493 case ISD::SETOLE: return Mips::FCOND_OLE;
495 case ISD::SETOGE: return Mips::FCOND_OGE;
496 case ISD::SETULT: return Mips::FCOND_ULT;
497 case ISD::SETULE: return Mips::FCOND_ULE;
498 case ISD::SETUGT: return Mips::FCOND_UGT;
499 case ISD::SETUGE: return Mips::FCOND_UGE;
500 case ISD::SETUO: return Mips::FCOND_UN;
501 case ISD::SETO: return Mips::FCOND_OR;
503 case ISD::SETONE: return Mips::FCOND_ONE;
504 case ISD::SETUEQ: return Mips::FCOND_UEQ;
509 /// This function returns true if the floating point conditional branches and
510 /// conditional moves which use condition code CC should be inverted.
511 static bool invertFPCondCodeUser(Mips::CondCode CC) {
512 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
515 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
516 "Illegal Condition Code");
521 // Creates and returns an FPCmp node from a setcc node.
522 // Returns Op if setcc is not a floating point comparison.
523 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
524 // must be a SETCC node
525 if (Op.getOpcode() != ISD::SETCC)
528 SDValue LHS = Op.getOperand(0);
530 if (!LHS.getValueType().isFloatingPoint())
533 SDValue RHS = Op.getOperand(1);
536 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
537 // node if necessary.
538 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
540 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
541 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
544 // Creates and returns a CMovFPT/F node.
545 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
546 SDValue False, SDLoc DL) {
547 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
548 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
549 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
551 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
552 True.getValueType(), True, FCC0, False, Cond);
555 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
556 TargetLowering::DAGCombinerInfo &DCI,
557 const MipsSubtarget *Subtarget) {
558 if (DCI.isBeforeLegalizeOps())
561 SDValue SetCC = N->getOperand(0);
563 if ((SetCC.getOpcode() != ISD::SETCC) ||
564 !SetCC.getOperand(0).getValueType().isInteger())
567 SDValue False = N->getOperand(2);
568 EVT FalseTy = False.getValueType();
570 if (!FalseTy.isInteger())
573 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
575 if (!CN || CN->getZExtValue())
579 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
580 SDValue True = N->getOperand(1);
582 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
583 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
585 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
588 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
589 TargetLowering::DAGCombinerInfo &DCI,
590 const MipsSubtarget *Subtarget) {
591 // Pattern match EXT.
592 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
593 // => ext $dst, $src, size, pos
594 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
597 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
598 unsigned ShiftRightOpc = ShiftRight.getOpcode();
600 // Op's first operand must be a shift right.
601 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
604 // The second operand of the shift must be an immediate.
606 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
609 uint64_t Pos = CN->getZExtValue();
610 uint64_t SMPos, SMSize;
612 // Op's second operand must be a shifted mask.
613 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
614 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
617 // Return if the shifted mask does not start at bit 0 or the sum of its size
618 // and Pos exceeds the word's size.
619 EVT ValTy = N->getValueType(0);
620 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
623 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
624 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
625 DAG.getConstant(SMSize, MVT::i32));
628 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
629 TargetLowering::DAGCombinerInfo &DCI,
630 const MipsSubtarget *Subtarget) {
631 // Pattern match INS.
632 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
633 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
634 // => ins $dst, $src, size, pos, $src1
635 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
638 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
639 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
642 // See if Op's first operand matches (and $src1 , mask0).
643 if (And0.getOpcode() != ISD::AND)
646 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
647 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
650 // See if Op's second operand matches (and (shl $src, pos), mask1).
651 if (And1.getOpcode() != ISD::AND)
654 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
655 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
658 // The shift masks must have the same position and size.
659 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
662 SDValue Shl = And1.getOperand(0);
663 if (Shl.getOpcode() != ISD::SHL)
666 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
669 unsigned Shamt = CN->getZExtValue();
671 // Return if the shift amount and the first bit position of mask are not the
673 EVT ValTy = N->getValueType(0);
674 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
677 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
678 DAG.getConstant(SMPos0, MVT::i32),
679 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
682 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
683 TargetLowering::DAGCombinerInfo &DCI,
684 const MipsSubtarget *Subtarget) {
685 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
687 if (DCI.isBeforeLegalizeOps())
690 SDValue Add = N->getOperand(1);
692 if (Add.getOpcode() != ISD::ADD)
695 SDValue Lo = Add.getOperand(1);
697 if ((Lo.getOpcode() != MipsISD::Lo) ||
698 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
701 EVT ValTy = N->getValueType(0);
704 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
706 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
709 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
711 SelectionDAG &DAG = DCI.DAG;
712 unsigned Opc = N->getOpcode();
718 return performDivRemCombine(N, DAG, DCI, Subtarget);
720 return performSELECTCombine(N, DAG, DCI, Subtarget);
722 return performANDCombine(N, DAG, DCI, Subtarget);
724 return performORCombine(N, DAG, DCI, Subtarget);
726 return performADDCombine(N, DAG, DCI, Subtarget);
733 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
734 SmallVectorImpl<SDValue> &Results,
735 SelectionDAG &DAG) const {
736 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
738 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
739 Results.push_back(Res.getValue(I));
743 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
744 SmallVectorImpl<SDValue> &Results,
745 SelectionDAG &DAG) const {
746 return LowerOperationWrapper(N, Results, DAG);
749 SDValue MipsTargetLowering::
750 LowerOperation(SDValue Op, SelectionDAG &DAG) const
752 switch (Op.getOpcode())
754 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
755 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
756 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
757 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
758 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
759 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
760 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
761 case ISD::SELECT: return lowerSELECT(Op, DAG);
762 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
763 case ISD::SETCC: return lowerSETCC(Op, DAG);
764 case ISD::VASTART: return lowerVASTART(Op, DAG);
765 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
766 case ISD::FABS: return lowerFABS(Op, DAG);
767 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
768 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
769 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
770 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
771 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
772 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
773 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
774 case ISD::LOAD: return lowerLOAD(Op, DAG);
775 case ISD::STORE: return lowerSTORE(Op, DAG);
776 case ISD::ADD: return lowerADD(Op, DAG);
777 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
782 //===----------------------------------------------------------------------===//
783 // Lower helper functions
784 //===----------------------------------------------------------------------===//
786 // addLiveIn - This helper function adds the specified physical register to the
787 // MachineFunction as a live in value. It also creates a corresponding
788 // virtual register for it.
790 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
792 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
793 MF.getRegInfo().addLiveIn(PReg, VReg);
797 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI,
798 MachineBasicBlock &MBB,
799 const TargetInstrInfo &TII,
804 // Insert instruction "teq $divisor_reg, $zero, 7".
805 MachineBasicBlock::iterator I(MI);
806 MachineInstrBuilder MIB;
807 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
808 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7);
810 // Use the 32-bit sub-register if this is a 64-bit division.
812 MIB->getOperand(0).setSubReg(Mips::sub_32);
818 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
819 MachineBasicBlock *BB) const {
820 switch (MI->getOpcode()) {
822 llvm_unreachable("Unexpected instr type to insert");
823 case Mips::ATOMIC_LOAD_ADD_I8:
824 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
825 case Mips::ATOMIC_LOAD_ADD_I16:
826 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
827 case Mips::ATOMIC_LOAD_ADD_I32:
828 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
829 case Mips::ATOMIC_LOAD_ADD_I64:
830 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
832 case Mips::ATOMIC_LOAD_AND_I8:
833 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
834 case Mips::ATOMIC_LOAD_AND_I16:
835 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
836 case Mips::ATOMIC_LOAD_AND_I32:
837 return emitAtomicBinary(MI, BB, 4, Mips::AND);
838 case Mips::ATOMIC_LOAD_AND_I64:
839 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
841 case Mips::ATOMIC_LOAD_OR_I8:
842 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
843 case Mips::ATOMIC_LOAD_OR_I16:
844 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
845 case Mips::ATOMIC_LOAD_OR_I32:
846 return emitAtomicBinary(MI, BB, 4, Mips::OR);
847 case Mips::ATOMIC_LOAD_OR_I64:
848 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
850 case Mips::ATOMIC_LOAD_XOR_I8:
851 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
852 case Mips::ATOMIC_LOAD_XOR_I16:
853 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
854 case Mips::ATOMIC_LOAD_XOR_I32:
855 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
856 case Mips::ATOMIC_LOAD_XOR_I64:
857 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
859 case Mips::ATOMIC_LOAD_NAND_I8:
860 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
861 case Mips::ATOMIC_LOAD_NAND_I16:
862 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
863 case Mips::ATOMIC_LOAD_NAND_I32:
864 return emitAtomicBinary(MI, BB, 4, 0, true);
865 case Mips::ATOMIC_LOAD_NAND_I64:
866 return emitAtomicBinary(MI, BB, 8, 0, true);
868 case Mips::ATOMIC_LOAD_SUB_I8:
869 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
870 case Mips::ATOMIC_LOAD_SUB_I16:
871 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
872 case Mips::ATOMIC_LOAD_SUB_I32:
873 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
874 case Mips::ATOMIC_LOAD_SUB_I64:
875 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
877 case Mips::ATOMIC_SWAP_I8:
878 return emitAtomicBinaryPartword(MI, BB, 1, 0);
879 case Mips::ATOMIC_SWAP_I16:
880 return emitAtomicBinaryPartword(MI, BB, 2, 0);
881 case Mips::ATOMIC_SWAP_I32:
882 return emitAtomicBinary(MI, BB, 4, 0);
883 case Mips::ATOMIC_SWAP_I64:
884 return emitAtomicBinary(MI, BB, 8, 0);
886 case Mips::ATOMIC_CMP_SWAP_I8:
887 return emitAtomicCmpSwapPartword(MI, BB, 1);
888 case Mips::ATOMIC_CMP_SWAP_I16:
889 return emitAtomicCmpSwapPartword(MI, BB, 2);
890 case Mips::ATOMIC_CMP_SWAP_I32:
891 return emitAtomicCmpSwap(MI, BB, 4);
892 case Mips::ATOMIC_CMP_SWAP_I64:
893 return emitAtomicCmpSwap(MI, BB, 8);
894 case Mips::PseudoSDIV:
895 case Mips::PseudoUDIV:
896 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false);
897 case Mips::PseudoDSDIV:
898 case Mips::PseudoDUDIV:
899 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true);
903 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
904 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
906 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
907 unsigned Size, unsigned BinOpcode,
909 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
911 MachineFunction *MF = BB->getParent();
912 MachineRegisterInfo &RegInfo = MF->getRegInfo();
913 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
914 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
915 DebugLoc DL = MI->getDebugLoc();
916 unsigned LL, SC, AND, NOR, ZERO, BEQ;
931 ZERO = Mips::ZERO_64;
935 unsigned OldVal = MI->getOperand(0).getReg();
936 unsigned Ptr = MI->getOperand(1).getReg();
937 unsigned Incr = MI->getOperand(2).getReg();
939 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
940 unsigned AndRes = RegInfo.createVirtualRegister(RC);
941 unsigned Success = RegInfo.createVirtualRegister(RC);
943 // insert new blocks after the current block
944 const BasicBlock *LLVM_BB = BB->getBasicBlock();
945 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
946 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
947 MachineFunction::iterator It = BB;
949 MF->insert(It, loopMBB);
950 MF->insert(It, exitMBB);
952 // Transfer the remainder of BB and its successor edges to exitMBB.
953 exitMBB->splice(exitMBB->begin(), BB,
954 llvm::next(MachineBasicBlock::iterator(MI)),
956 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
960 // fallthrough --> loopMBB
961 BB->addSuccessor(loopMBB);
962 loopMBB->addSuccessor(loopMBB);
963 loopMBB->addSuccessor(exitMBB);
967 // <binop> storeval, oldval, incr
968 // sc success, storeval, 0(ptr)
969 // beq success, $0, loopMBB
971 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
973 // and andres, oldval, incr
974 // nor storeval, $0, andres
975 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
976 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
977 } else if (BinOpcode) {
978 // <binop> storeval, oldval, incr
979 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
983 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
984 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
986 MI->eraseFromParent(); // The instruction is gone now.
992 MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
993 MachineBasicBlock *BB,
994 unsigned Size, unsigned BinOpcode,
996 assert((Size == 1 || Size == 2) &&
997 "Unsupported size for EmitAtomicBinaryPartial.");
999 MachineFunction *MF = BB->getParent();
1000 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1001 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1002 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1003 DebugLoc DL = MI->getDebugLoc();
1005 unsigned Dest = MI->getOperand(0).getReg();
1006 unsigned Ptr = MI->getOperand(1).getReg();
1007 unsigned Incr = MI->getOperand(2).getReg();
1009 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1010 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1011 unsigned Mask = RegInfo.createVirtualRegister(RC);
1012 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1013 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1014 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1015 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1016 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1017 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1018 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1019 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1020 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1021 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1022 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1023 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1024 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1025 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1026 unsigned Success = RegInfo.createVirtualRegister(RC);
1028 // insert new blocks after the current block
1029 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1030 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1031 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1032 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1033 MachineFunction::iterator It = BB;
1035 MF->insert(It, loopMBB);
1036 MF->insert(It, sinkMBB);
1037 MF->insert(It, exitMBB);
1039 // Transfer the remainder of BB and its successor edges to exitMBB.
1040 exitMBB->splice(exitMBB->begin(), BB,
1041 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1042 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1044 BB->addSuccessor(loopMBB);
1045 loopMBB->addSuccessor(loopMBB);
1046 loopMBB->addSuccessor(sinkMBB);
1047 sinkMBB->addSuccessor(exitMBB);
1050 // addiu masklsb2,$0,-4 # 0xfffffffc
1051 // and alignedaddr,ptr,masklsb2
1052 // andi ptrlsb2,ptr,3
1053 // sll shiftamt,ptrlsb2,3
1054 // ori maskupper,$0,255 # 0xff
1055 // sll mask,maskupper,shiftamt
1056 // nor mask2,$0,mask
1057 // sll incr2,incr,shiftamt
1059 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1060 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1061 .addReg(Mips::ZERO).addImm(-4);
1062 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1063 .addReg(Ptr).addReg(MaskLSB2);
1064 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1065 if (Subtarget->isLittle()) {
1066 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1068 unsigned Off = RegInfo.createVirtualRegister(RC);
1069 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1070 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1071 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1073 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1074 .addReg(Mips::ZERO).addImm(MaskImm);
1075 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1076 .addReg(MaskUpper).addReg(ShiftAmt);
1077 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1078 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1080 // atomic.load.binop
1082 // ll oldval,0(alignedaddr)
1083 // binop binopres,oldval,incr2
1084 // and newval,binopres,mask
1085 // and maskedoldval0,oldval,mask2
1086 // or storeval,maskedoldval0,newval
1087 // sc success,storeval,0(alignedaddr)
1088 // beq success,$0,loopMBB
1092 // ll oldval,0(alignedaddr)
1093 // and newval,incr2,mask
1094 // and maskedoldval0,oldval,mask2
1095 // or storeval,maskedoldval0,newval
1096 // sc success,storeval,0(alignedaddr)
1097 // beq success,$0,loopMBB
1100 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1102 // and andres, oldval, incr2
1103 // nor binopres, $0, andres
1104 // and newval, binopres, mask
1105 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1106 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1107 .addReg(Mips::ZERO).addReg(AndRes);
1108 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1109 } else if (BinOpcode) {
1110 // <binop> binopres, oldval, incr2
1111 // and newval, binopres, mask
1112 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1113 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1114 } else {// atomic.swap
1115 // and newval, incr2, mask
1116 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1119 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1120 .addReg(OldVal).addReg(Mask2);
1121 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1122 .addReg(MaskedOldVal0).addReg(NewVal);
1123 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1124 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1125 BuildMI(BB, DL, TII->get(Mips::BEQ))
1126 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1129 // and maskedoldval1,oldval,mask
1130 // srl srlres,maskedoldval1,shiftamt
1131 // sll sllres,srlres,24
1132 // sra dest,sllres,24
1134 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1136 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1137 .addReg(OldVal).addReg(Mask);
1138 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1139 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1140 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1141 .addReg(SrlRes).addImm(ShiftImm);
1142 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1143 .addReg(SllRes).addImm(ShiftImm);
1145 MI->eraseFromParent(); // The instruction is gone now.
1151 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1152 MachineBasicBlock *BB,
1153 unsigned Size) const {
1154 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1156 MachineFunction *MF = BB->getParent();
1157 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1158 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1159 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1160 DebugLoc DL = MI->getDebugLoc();
1161 unsigned LL, SC, ZERO, BNE, BEQ;
1173 ZERO = Mips::ZERO_64;
1178 unsigned Dest = MI->getOperand(0).getReg();
1179 unsigned Ptr = MI->getOperand(1).getReg();
1180 unsigned OldVal = MI->getOperand(2).getReg();
1181 unsigned NewVal = MI->getOperand(3).getReg();
1183 unsigned Success = RegInfo.createVirtualRegister(RC);
1185 // insert new blocks after the current block
1186 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1187 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1188 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1189 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1190 MachineFunction::iterator It = BB;
1192 MF->insert(It, loop1MBB);
1193 MF->insert(It, loop2MBB);
1194 MF->insert(It, exitMBB);
1196 // Transfer the remainder of BB and its successor edges to exitMBB.
1197 exitMBB->splice(exitMBB->begin(), BB,
1198 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1199 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1203 // fallthrough --> loop1MBB
1204 BB->addSuccessor(loop1MBB);
1205 loop1MBB->addSuccessor(exitMBB);
1206 loop1MBB->addSuccessor(loop2MBB);
1207 loop2MBB->addSuccessor(loop1MBB);
1208 loop2MBB->addSuccessor(exitMBB);
1212 // bne dest, oldval, exitMBB
1214 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1215 BuildMI(BB, DL, TII->get(BNE))
1216 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1219 // sc success, newval, 0(ptr)
1220 // beq success, $0, loop1MBB
1222 BuildMI(BB, DL, TII->get(SC), Success)
1223 .addReg(NewVal).addReg(Ptr).addImm(0);
1224 BuildMI(BB, DL, TII->get(BEQ))
1225 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1227 MI->eraseFromParent(); // The instruction is gone now.
1233 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1234 MachineBasicBlock *BB,
1235 unsigned Size) const {
1236 assert((Size == 1 || Size == 2) &&
1237 "Unsupported size for EmitAtomicCmpSwapPartial.");
1239 MachineFunction *MF = BB->getParent();
1240 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1241 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1242 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1243 DebugLoc DL = MI->getDebugLoc();
1245 unsigned Dest = MI->getOperand(0).getReg();
1246 unsigned Ptr = MI->getOperand(1).getReg();
1247 unsigned CmpVal = MI->getOperand(2).getReg();
1248 unsigned NewVal = MI->getOperand(3).getReg();
1250 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1251 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1252 unsigned Mask = RegInfo.createVirtualRegister(RC);
1253 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1254 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1255 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1256 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1257 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1258 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1259 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1260 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1261 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1262 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1263 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1264 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1265 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1266 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1267 unsigned Success = RegInfo.createVirtualRegister(RC);
1269 // insert new blocks after the current block
1270 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1271 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1272 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1273 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1274 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1275 MachineFunction::iterator It = BB;
1277 MF->insert(It, loop1MBB);
1278 MF->insert(It, loop2MBB);
1279 MF->insert(It, sinkMBB);
1280 MF->insert(It, exitMBB);
1282 // Transfer the remainder of BB and its successor edges to exitMBB.
1283 exitMBB->splice(exitMBB->begin(), BB,
1284 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1285 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1287 BB->addSuccessor(loop1MBB);
1288 loop1MBB->addSuccessor(sinkMBB);
1289 loop1MBB->addSuccessor(loop2MBB);
1290 loop2MBB->addSuccessor(loop1MBB);
1291 loop2MBB->addSuccessor(sinkMBB);
1292 sinkMBB->addSuccessor(exitMBB);
1294 // FIXME: computation of newval2 can be moved to loop2MBB.
1296 // addiu masklsb2,$0,-4 # 0xfffffffc
1297 // and alignedaddr,ptr,masklsb2
1298 // andi ptrlsb2,ptr,3
1299 // sll shiftamt,ptrlsb2,3
1300 // ori maskupper,$0,255 # 0xff
1301 // sll mask,maskupper,shiftamt
1302 // nor mask2,$0,mask
1303 // andi maskedcmpval,cmpval,255
1304 // sll shiftedcmpval,maskedcmpval,shiftamt
1305 // andi maskednewval,newval,255
1306 // sll shiftednewval,maskednewval,shiftamt
1307 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1308 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1309 .addReg(Mips::ZERO).addImm(-4);
1310 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1311 .addReg(Ptr).addReg(MaskLSB2);
1312 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1313 if (Subtarget->isLittle()) {
1314 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1316 unsigned Off = RegInfo.createVirtualRegister(RC);
1317 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1318 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1319 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1321 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1322 .addReg(Mips::ZERO).addImm(MaskImm);
1323 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1324 .addReg(MaskUpper).addReg(ShiftAmt);
1325 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1326 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1327 .addReg(CmpVal).addImm(MaskImm);
1328 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1329 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1330 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1331 .addReg(NewVal).addImm(MaskImm);
1332 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1333 .addReg(MaskedNewVal).addReg(ShiftAmt);
1336 // ll oldval,0(alginedaddr)
1337 // and maskedoldval0,oldval,mask
1338 // bne maskedoldval0,shiftedcmpval,sinkMBB
1340 BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0);
1341 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1342 .addReg(OldVal).addReg(Mask);
1343 BuildMI(BB, DL, TII->get(Mips::BNE))
1344 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1347 // and maskedoldval1,oldval,mask2
1348 // or storeval,maskedoldval1,shiftednewval
1349 // sc success,storeval,0(alignedaddr)
1350 // beq success,$0,loop1MBB
1352 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1353 .addReg(OldVal).addReg(Mask2);
1354 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1355 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1356 BuildMI(BB, DL, TII->get(Mips::SC), Success)
1357 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1358 BuildMI(BB, DL, TII->get(Mips::BEQ))
1359 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1362 // srl srlres,maskedoldval0,shiftamt
1363 // sll sllres,srlres,24
1364 // sra dest,sllres,24
1366 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1368 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1369 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1370 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1371 .addReg(SrlRes).addImm(ShiftImm);
1372 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1373 .addReg(SllRes).addImm(ShiftImm);
1375 MI->eraseFromParent(); // The instruction is gone now.
1380 //===----------------------------------------------------------------------===//
1381 // Misc Lower Operation implementation
1382 //===----------------------------------------------------------------------===//
1383 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1384 SDValue Chain = Op.getOperand(0);
1385 SDValue Table = Op.getOperand(1);
1386 SDValue Index = Op.getOperand(2);
1388 EVT PTy = getPointerTy();
1389 unsigned EntrySize =
1390 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1392 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1393 DAG.getConstant(EntrySize, PTy));
1394 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1396 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1397 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1398 MachinePointerInfo::getJumpTable(), MemVT, false, false,
1400 Chain = Addr.getValue(1);
1402 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
1403 // For PIC, the sequence is:
1404 // BRIND(load(Jumptable + index) + RelocBase)
1405 // RelocBase can be JumpTable, GOT or some sort of global base.
1406 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1407 getPICJumpTableRelocBase(Table, DAG));
1410 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1413 SDValue MipsTargetLowering::
1414 lowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1416 // The first operand is the chain, the second is the condition, the third is
1417 // the block to branch to if the condition is true.
1418 SDValue Chain = Op.getOperand(0);
1419 SDValue Dest = Op.getOperand(2);
1422 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1424 // Return if flag is not set by a floating point comparison.
1425 if (CondRes.getOpcode() != MipsISD::FPCmp)
1428 SDValue CCNode = CondRes.getOperand(2);
1430 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1431 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1432 SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1433 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1434 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1435 FCC0, Dest, CondRes);
1438 SDValue MipsTargetLowering::
1439 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1441 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1443 // Return if flag is not set by a floating point comparison.
1444 if (Cond.getOpcode() != MipsISD::FPCmp)
1447 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1451 SDValue MipsTargetLowering::
1452 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1455 EVT Ty = Op.getOperand(0).getValueType();
1456 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1457 getSetCCResultType(*DAG.getContext(), Ty),
1458 Op.getOperand(0), Op.getOperand(1),
1461 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1465 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1466 SDValue Cond = createFPCmp(DAG, Op);
1468 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1469 "Floating point operand expected.");
1471 SDValue True = DAG.getConstant(1, MVT::i32);
1472 SDValue False = DAG.getConstant(0, MVT::i32);
1474 return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1477 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1478 SelectionDAG &DAG) const {
1479 // FIXME there isn't actually debug info here
1481 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1483 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1484 const MipsTargetObjectFile &TLOF =
1485 (const MipsTargetObjectFile&)getObjFileLowering();
1487 // %gp_rel relocation
1488 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1489 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
1491 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
1492 DAG.getVTList(MVT::i32), &GA, 1);
1493 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1494 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
1497 // %hi/%lo relocation
1498 return getAddrNonPIC(Op, DAG);
1501 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1502 return getAddrLocal(Op, DAG, HasMips64);
1505 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
1506 MipsII::MO_GOT_LO16);
1508 return getAddrGlobal(Op, DAG,
1509 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
1512 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1513 SelectionDAG &DAG) const {
1514 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1515 return getAddrNonPIC(Op, DAG);
1517 return getAddrLocal(Op, DAG, HasMips64);
1520 SDValue MipsTargetLowering::
1521 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1523 // If the relocation model is PIC, use the General Dynamic TLS Model or
1524 // Local Dynamic TLS model, otherwise use the Initial Exec or
1525 // Local Exec TLS Model.
1527 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1529 const GlobalValue *GV = GA->getGlobal();
1530 EVT PtrVT = getPointerTy();
1532 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1534 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1535 // General Dynamic and Local Dynamic TLS Model.
1536 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1539 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1540 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1541 getGlobalReg(DAG, PtrVT), TGA);
1542 unsigned PtrSize = PtrVT.getSizeInBits();
1543 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1545 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1549 Entry.Node = Argument;
1551 Args.push_back(Entry);
1553 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1554 false, false, false, false, 0, CallingConv::C,
1555 /*IsTailCall=*/false, /*doesNotRet=*/false,
1556 /*isReturnValueUsed=*/true,
1557 TlsGetAddr, Args, DAG, DL);
1558 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1560 SDValue Ret = CallResult.first;
1562 if (model != TLSModel::LocalDynamic)
1565 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1566 MipsII::MO_DTPREL_HI);
1567 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1568 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1569 MipsII::MO_DTPREL_LO);
1570 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1571 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1572 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1576 if (model == TLSModel::InitialExec) {
1577 // Initial Exec TLS Model
1578 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1579 MipsII::MO_GOTTPREL);
1580 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1582 Offset = DAG.getLoad(PtrVT, DL,
1583 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1584 false, false, false, 0);
1586 // Local Exec TLS Model
1587 assert(model == TLSModel::LocalExec);
1588 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1589 MipsII::MO_TPREL_HI);
1590 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1591 MipsII::MO_TPREL_LO);
1592 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1593 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1594 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1597 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1598 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1601 SDValue MipsTargetLowering::
1602 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1604 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1605 return getAddrNonPIC(Op, DAG);
1607 return getAddrLocal(Op, DAG, HasMips64);
1610 SDValue MipsTargetLowering::
1611 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1613 // gp_rel relocation
1614 // FIXME: we should reference the constant pool using small data sections,
1615 // but the asm printer currently doesn't support this feature without
1616 // hacking it. This feature should come soon so we can uncomment the
1618 //if (IsInSmallSection(C->getType())) {
1619 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1620 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1621 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1623 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1624 return getAddrNonPIC(Op, DAG);
1626 return getAddrLocal(Op, DAG, HasMips64);
1629 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1630 MachineFunction &MF = DAG.getMachineFunction();
1631 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1634 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1637 // vastart just stores the address of the VarArgsFrameIndex slot into the
1638 // memory location argument.
1639 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1640 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1641 MachinePointerInfo(SV), false, false, 0);
1644 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1645 EVT TyX = Op.getOperand(0).getValueType();
1646 EVT TyY = Op.getOperand(1).getValueType();
1647 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1648 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1652 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1654 SDValue X = (TyX == MVT::f32) ?
1655 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1656 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1658 SDValue Y = (TyY == MVT::f32) ?
1659 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1660 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1664 // ext E, Y, 31, 1 ; extract bit31 of Y
1665 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1666 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1667 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1670 // srl SrlX, SllX, 1
1672 // sll SllY, SrlX, 31
1673 // or Or, SrlX, SllY
1674 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1675 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1676 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1677 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1678 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1681 if (TyX == MVT::f32)
1682 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1684 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1685 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1686 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1689 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1690 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1691 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1692 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1693 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1696 // Bitcast to integer nodes.
1697 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1698 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1701 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1702 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1703 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1704 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1706 if (WidthX > WidthY)
1707 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1708 else if (WidthY > WidthX)
1709 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1711 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1712 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1713 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1716 // (d)sll SllX, X, 1
1717 // (d)srl SrlX, SllX, 1
1718 // (d)srl SrlY, Y, width(Y)-1
1719 // (d)sll SllY, SrlX, width(Y)-1
1720 // or Or, SrlX, SllY
1721 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1722 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1723 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1724 DAG.getConstant(WidthY - 1, MVT::i32));
1726 if (WidthX > WidthY)
1727 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1728 else if (WidthY > WidthX)
1729 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1731 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1732 DAG.getConstant(WidthX - 1, MVT::i32));
1733 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1734 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1738 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1739 if (Subtarget->hasMips64())
1740 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
1742 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
1745 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1746 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1749 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1751 SDValue X = (Op.getValueType() == MVT::f32) ?
1752 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1753 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1758 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1759 DAG.getRegister(Mips::ZERO, MVT::i32),
1760 DAG.getConstant(31, MVT::i32), Const1, X);
1762 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1763 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1766 if (Op.getValueType() == MVT::f32)
1767 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1769 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1770 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1771 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1774 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1775 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1778 // Bitcast to integer node.
1779 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1783 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1784 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1785 DAG.getConstant(63, MVT::i32), Const1, X);
1787 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1788 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1791 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1795 MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
1796 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1797 return lowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1799 return lowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1802 SDValue MipsTargetLowering::
1803 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1805 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1806 "Frame address can only be determined for current frame.");
1808 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1809 MFI->setFrameAddressIsTaken(true);
1810 EVT VT = Op.getValueType();
1812 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1813 IsN64 ? Mips::FP_64 : Mips::FP, VT);
1817 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1818 SelectionDAG &DAG) const {
1820 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1821 "Return address can be determined only for current frame.");
1823 MachineFunction &MF = DAG.getMachineFunction();
1824 MachineFrameInfo *MFI = MF.getFrameInfo();
1825 MVT VT = Op.getSimpleValueType();
1826 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
1827 MFI->setReturnAddressIsTaken(true);
1829 // Return RA, which contains the return address. Mark it an implicit live-in.
1830 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
1831 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
1834 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
1835 // generated from __builtin_eh_return (offset, handler)
1836 // The effect of this is to adjust the stack pointer by "offset"
1837 // and then branch to "handler".
1838 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
1840 MachineFunction &MF = DAG.getMachineFunction();
1841 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1843 MipsFI->setCallsEhReturn();
1844 SDValue Chain = Op.getOperand(0);
1845 SDValue Offset = Op.getOperand(1);
1846 SDValue Handler = Op.getOperand(2);
1848 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
1850 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
1851 // EH_RETURN nodes, so that instructions are emitted back-to-back.
1852 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
1853 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
1854 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
1855 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
1856 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
1857 DAG.getRegister(OffsetReg, Ty),
1858 DAG.getRegister(AddrReg, getPointerTy()),
1862 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
1863 SelectionDAG &DAG) const {
1864 // FIXME: Need pseudo-fence for 'singlethread' fences
1865 // FIXME: Set SType for weaker fences where supported/appropriate.
1868 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
1869 DAG.getConstant(SType, MVT::i32));
1872 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
1873 SelectionDAG &DAG) const {
1875 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1876 SDValue Shamt = Op.getOperand(2);
1879 // lo = (shl lo, shamt)
1880 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
1883 // hi = (shl lo, shamt[4:0])
1884 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1885 DAG.getConstant(-1, MVT::i32));
1886 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1887 DAG.getConstant(1, MVT::i32));
1888 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1890 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1891 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1892 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1893 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1894 DAG.getConstant(0x20, MVT::i32));
1895 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1896 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
1897 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
1899 SDValue Ops[2] = {Lo, Hi};
1900 return DAG.getMergeValues(Ops, 2, DL);
1903 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
1906 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1907 SDValue Shamt = Op.getOperand(2);
1910 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
1912 // hi = (sra hi, shamt)
1914 // hi = (srl hi, shamt)
1917 // lo = (sra hi, shamt[4:0])
1918 // hi = (sra hi, 31)
1920 // lo = (srl hi, shamt[4:0])
1922 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1923 DAG.getConstant(-1, MVT::i32));
1924 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
1925 DAG.getConstant(1, MVT::i32));
1926 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
1927 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
1928 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1929 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1931 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1932 DAG.getConstant(0x20, MVT::i32));
1933 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
1934 DAG.getConstant(31, MVT::i32));
1935 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
1936 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1937 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
1940 SDValue Ops[2] = {Lo, Hi};
1941 return DAG.getMergeValues(Ops, 2, DL);
1944 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
1945 SDValue Chain, SDValue Src, unsigned Offset) {
1946 SDValue Ptr = LD->getBasePtr();
1947 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
1948 EVT BasePtrVT = Ptr.getValueType();
1950 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1953 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
1954 DAG.getConstant(Offset, BasePtrVT));
1956 SDValue Ops[] = { Chain, Ptr, Src };
1957 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
1958 LD->getMemOperand());
1961 // Expand an unaligned 32 or 64-bit integer load node.
1962 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1963 LoadSDNode *LD = cast<LoadSDNode>(Op);
1964 EVT MemVT = LD->getMemoryVT();
1966 // Return if load is aligned or if MemVT is neither i32 nor i64.
1967 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
1968 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
1971 bool IsLittle = Subtarget->isLittle();
1972 EVT VT = Op.getValueType();
1973 ISD::LoadExtType ExtType = LD->getExtensionType();
1974 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
1976 assert((VT == MVT::i32) || (VT == MVT::i64));
1979 // (set dst, (i64 (load baseptr)))
1981 // (set tmp, (ldl (add baseptr, 7), undef))
1982 // (set dst, (ldr baseptr, tmp))
1983 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
1984 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
1986 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
1990 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
1992 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
1996 // (set dst, (i32 (load baseptr))) or
1997 // (set dst, (i64 (sextload baseptr))) or
1998 // (set dst, (i64 (extload baseptr)))
2000 // (set tmp, (lwl (add baseptr, 3), undef))
2001 // (set dst, (lwr baseptr, tmp))
2002 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2003 (ExtType == ISD::EXTLOAD))
2006 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2009 // (set dst, (i64 (zextload baseptr)))
2011 // (set tmp0, (lwl (add baseptr, 3), undef))
2012 // (set tmp1, (lwr baseptr, tmp0))
2013 // (set tmp2, (shl tmp1, 32))
2014 // (set dst, (srl tmp2, 32))
2016 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2017 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2018 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2019 SDValue Ops[] = { SRL, LWR.getValue(1) };
2020 return DAG.getMergeValues(Ops, 2, DL);
2023 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2024 SDValue Chain, unsigned Offset) {
2025 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2026 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2028 SDVTList VTList = DAG.getVTList(MVT::Other);
2031 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2032 DAG.getConstant(Offset, BasePtrVT));
2034 SDValue Ops[] = { Chain, Value, Ptr };
2035 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2036 SD->getMemOperand());
2039 // Expand an unaligned 32 or 64-bit integer store node.
2040 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2042 SDValue Value = SD->getValue(), Chain = SD->getChain();
2043 EVT VT = Value.getValueType();
2046 // (store val, baseptr) or
2047 // (truncstore val, baseptr)
2049 // (swl val, (add baseptr, 3))
2050 // (swr val, baseptr)
2051 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2052 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2054 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2057 assert(VT == MVT::i64);
2060 // (store val, baseptr)
2062 // (sdl val, (add baseptr, 7))
2063 // (sdr val, baseptr)
2064 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2065 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2068 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2069 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2070 SDValue Val = SD->getValue();
2072 if (Val.getOpcode() != ISD::FP_TO_SINT)
2075 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2076 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2079 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2080 SD->getPointerInfo(), SD->isVolatile(),
2081 SD->isNonTemporal(), SD->getAlignment());
2084 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2085 StoreSDNode *SD = cast<StoreSDNode>(Op);
2086 EVT MemVT = SD->getMemoryVT();
2088 // Lower unaligned integer stores.
2089 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2090 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2091 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle());
2093 return lowerFP_TO_SINT_STORE(SD, DAG);
2096 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2097 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2098 || cast<ConstantSDNode>
2099 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2100 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2104 // (add (frameaddr 0), (frame_to_args_offset))
2105 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2106 // (add FrameObject, 0)
2107 // where FrameObject is a fixed StackObject with offset 0 which points to
2108 // the old stack pointer.
2109 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2110 EVT ValTy = Op->getValueType(0);
2111 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2112 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2113 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2114 DAG.getConstant(0, ValTy));
2117 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2118 SelectionDAG &DAG) const {
2119 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2120 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2122 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2125 //===----------------------------------------------------------------------===//
2126 // Calling Convention Implementation
2127 //===----------------------------------------------------------------------===//
2129 //===----------------------------------------------------------------------===//
2130 // TODO: Implement a generic logic using tblgen that can support this.
2131 // Mips O32 ABI rules:
2133 // i32 - Passed in A0, A1, A2, A3 and stack
2134 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2135 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2136 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2137 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2138 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
2141 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2142 //===----------------------------------------------------------------------===//
2144 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2145 MVT LocVT, CCValAssign::LocInfo LocInfo,
2146 ISD::ArgFlagsTy ArgFlags, CCState &State,
2147 const uint16_t *F64Regs) {
2149 static const unsigned IntRegsSize=4, FloatRegsSize=2;
2151 static const uint16_t IntRegs[] = {
2152 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2154 static const uint16_t F32Regs[] = {
2155 Mips::F12, Mips::F14
2158 // Do not process byval args here.
2159 if (ArgFlags.isByVal())
2162 // Promote i8 and i16
2163 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2165 if (ArgFlags.isSExt())
2166 LocInfo = CCValAssign::SExt;
2167 else if (ArgFlags.isZExt())
2168 LocInfo = CCValAssign::ZExt;
2170 LocInfo = CCValAssign::AExt;
2175 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2176 // is true: function is vararg, argument is 3rd or higher, there is previous
2177 // argument which is not f32 or f64.
2178 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2179 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2180 unsigned OrigAlign = ArgFlags.getOrigAlign();
2181 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2183 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2184 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2185 // If this is the first part of an i64 arg,
2186 // the allocated register must be either A0 or A2.
2187 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2188 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2190 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2191 // Allocate int register and shadow next int register. If first
2192 // available register is Mips::A1 or Mips::A3, shadow it too.
2193 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2194 if (Reg == Mips::A1 || Reg == Mips::A3)
2195 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2196 State.AllocateReg(IntRegs, IntRegsSize);
2198 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2199 // we are guaranteed to find an available float register
2200 if (ValVT == MVT::f32) {
2201 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2202 // Shadow int register
2203 State.AllocateReg(IntRegs, IntRegsSize);
2205 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2206 // Shadow int registers
2207 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2208 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2209 State.AllocateReg(IntRegs, IntRegsSize);
2210 State.AllocateReg(IntRegs, IntRegsSize);
2213 llvm_unreachable("Cannot handle this ValVT.");
2216 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2218 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2220 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2225 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2226 MVT LocVT, CCValAssign::LocInfo LocInfo,
2227 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2228 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 };
2230 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2233 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2234 MVT LocVT, CCValAssign::LocInfo LocInfo,
2235 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2236 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D12_64 };
2238 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2241 #include "MipsGenCallingConv.inc"
2243 //===----------------------------------------------------------------------===//
2244 // Call Calling Convention Implementation
2245 //===----------------------------------------------------------------------===//
2247 // Return next O32 integer argument register.
2248 static unsigned getNextIntArgReg(unsigned Reg) {
2249 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2250 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2254 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2255 SDValue Chain, SDValue Arg, SDLoc DL,
2256 bool IsTailCall, SelectionDAG &DAG) const {
2258 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2259 DAG.getIntPtrConstant(Offset));
2260 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2264 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2265 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2266 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2267 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2268 /*isVolatile=*/ true, false, 0);
2271 void MipsTargetLowering::
2272 getOpndList(SmallVectorImpl<SDValue> &Ops,
2273 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2274 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2275 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
2276 // Insert node "GP copy globalreg" before call to function.
2278 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2279 // in PIC mode) allow symbols to be resolved via lazy binding.
2280 // The lazy binding stub requires GP to point to the GOT.
2281 if (IsPICCall && !InternalLinkage) {
2282 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2283 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2284 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2287 // Build a sequence of copy-to-reg nodes chained together with token
2288 // chain and flag operands which copy the outgoing args into registers.
2289 // The InFlag in necessary since all emitted instructions must be
2293 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2294 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2295 RegsToPass[i].second, InFlag);
2296 InFlag = Chain.getValue(1);
2299 // Add argument registers to the end of the list so that they are
2300 // known live into the call.
2301 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2302 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2303 RegsToPass[i].second.getValueType()));
2305 // Add a register mask operand representing the call-preserved registers.
2306 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2307 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2308 assert(Mask && "Missing call preserved mask for calling convention");
2309 if (Subtarget->inMips16HardFloat()) {
2310 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2311 llvm::StringRef Sym = G->getGlobal()->getName();
2312 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2313 if (F->hasFnAttribute("__Mips16RetHelper")) {
2314 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2318 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2320 if (InFlag.getNode())
2321 Ops.push_back(InFlag);
2324 /// LowerCall - functions arguments are copied from virtual regs to
2325 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2327 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2328 SmallVectorImpl<SDValue> &InVals) const {
2329 SelectionDAG &DAG = CLI.DAG;
2331 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2332 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2333 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2334 SDValue Chain = CLI.Chain;
2335 SDValue Callee = CLI.Callee;
2336 bool &IsTailCall = CLI.IsTailCall;
2337 CallingConv::ID CallConv = CLI.CallConv;
2338 bool IsVarArg = CLI.IsVarArg;
2340 MachineFunction &MF = DAG.getMachineFunction();
2341 MachineFrameInfo *MFI = MF.getFrameInfo();
2342 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2343 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2345 // Analyze operands of the call, assigning locations to each operand.
2346 SmallVector<CCValAssign, 16> ArgLocs;
2347 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2348 getTargetMachine(), ArgLocs, *DAG.getContext());
2349 MipsCC::SpecialCallingConvType SpecialCallingConv =
2350 getSpecialCallingConv(Callee);
2351 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo,
2352 SpecialCallingConv);
2354 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
2355 Subtarget->mipsSEUsesSoftFloat(),
2356 Callee.getNode(), CLI.Args);
2358 // Get a count of how many bytes are to be pushed on the stack.
2359 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2361 // Check if it's really possible to do a tail call.
2364 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
2365 *MF.getInfo<MipsFunctionInfo>());
2370 // Chain is the output chain of the last Load/Store or CopyToReg node.
2371 // ByValChain is the output chain of the last Memcpy node created for copying
2372 // byval arguments to the stack.
2373 unsigned StackAlignment = TFL->getStackAlignment();
2374 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2375 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2378 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2380 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL,
2381 IsN64 ? Mips::SP_64 : Mips::SP,
2384 // With EABI is it possible to have 16 args on registers.
2385 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2386 SmallVector<SDValue, 8> MemOpChains;
2387 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2389 // Walk the register/memloc assignments, inserting copies/loads.
2390 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2391 SDValue Arg = OutVals[i];
2392 CCValAssign &VA = ArgLocs[i];
2393 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2394 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2397 if (Flags.isByVal()) {
2398 assert(Flags.getByValSize() &&
2399 "ByVal args of size 0 should have been ignored by front-end.");
2400 assert(ByValArg != MipsCCInfo.byval_end());
2401 assert(!IsTailCall &&
2402 "Do not tail-call optimize if there is a byval argument.");
2403 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2404 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
2409 // Promote the value if needed.
2410 switch (VA.getLocInfo()) {
2411 default: llvm_unreachable("Unknown loc info!");
2412 case CCValAssign::Full:
2413 if (VA.isRegLoc()) {
2414 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2415 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2416 (ValVT == MVT::i64 && LocVT == MVT::f64))
2417 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2418 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2419 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2420 Arg, DAG.getConstant(0, MVT::i32));
2421 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2422 Arg, DAG.getConstant(1, MVT::i32));
2423 if (!Subtarget->isLittle())
2425 unsigned LocRegLo = VA.getLocReg();
2426 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2427 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2428 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2433 case CCValAssign::SExt:
2434 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2436 case CCValAssign::ZExt:
2437 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2439 case CCValAssign::AExt:
2440 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2444 // Arguments that can be passed on register must be kept at
2445 // RegsToPass vector
2446 if (VA.isRegLoc()) {
2447 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2451 // Register can't get to this point...
2452 assert(VA.isMemLoc());
2454 // emit ISD::STORE whichs stores the
2455 // parameter value to a stack Location
2456 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2457 Chain, Arg, DL, IsTailCall, DAG));
2460 // Transform all store nodes into one single node because all store
2461 // nodes are independent of each other.
2462 if (!MemOpChains.empty())
2463 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2464 &MemOpChains[0], MemOpChains.size());
2466 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2467 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2468 // node so that legalize doesn't hack it.
2469 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2470 bool GlobalOrExternal = false, InternalLinkage = false;
2473 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2475 InternalLinkage = G->getGlobal()->hasInternalLinkage();
2477 if (InternalLinkage)
2478 Callee = getAddrLocal(Callee, DAG, HasMips64);
2480 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
2481 MipsII::MO_CALL_LO16);
2483 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
2485 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2486 MipsII::MO_NO_FLAG);
2487 GlobalOrExternal = true;
2489 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2490 if (!IsN64 && !IsPIC) // !N64 && static
2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2492 MipsII::MO_NO_FLAG);
2494 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
2495 MipsII::MO_CALL_LO16);
2497 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
2499 GlobalOrExternal = true;
2502 SmallVector<SDValue, 8> Ops(1, Chain);
2503 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2505 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2506 CLI, Callee, Chain);
2509 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
2511 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
2512 SDValue InFlag = Chain.getValue(1);
2514 // Create the CALLSEQ_END node.
2515 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2516 DAG.getIntPtrConstant(0, true), InFlag, DL);
2517 InFlag = Chain.getValue(1);
2519 // Handle result values, copying them out of physregs into vregs that we
2521 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
2522 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
2525 /// LowerCallResult - Lower the result values of a call into the
2526 /// appropriate copies out of appropriate physical registers.
2528 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2529 CallingConv::ID CallConv, bool IsVarArg,
2530 const SmallVectorImpl<ISD::InputArg> &Ins,
2531 SDLoc DL, SelectionDAG &DAG,
2532 SmallVectorImpl<SDValue> &InVals,
2533 const SDNode *CallNode,
2534 const Type *RetTy) const {
2535 // Assign locations to each value returned by this call.
2536 SmallVector<CCValAssign, 16> RVLocs;
2537 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2538 getTargetMachine(), RVLocs, *DAG.getContext());
2539 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2541 MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(),
2544 // Copy all of the result registers out of their specified physreg.
2545 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2546 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2547 RVLocs[i].getLocVT(), InFlag);
2548 Chain = Val.getValue(1);
2549 InFlag = Val.getValue(2);
2551 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2552 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
2554 InVals.push_back(Val);
2560 //===----------------------------------------------------------------------===//
2561 // Formal Arguments Calling Convention Implementation
2562 //===----------------------------------------------------------------------===//
2563 /// LowerFormalArguments - transform physical registers into virtual registers
2564 /// and generate load operations for arguments places on the stack.
2566 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2567 CallingConv::ID CallConv,
2569 const SmallVectorImpl<ISD::InputArg> &Ins,
2570 SDLoc DL, SelectionDAG &DAG,
2571 SmallVectorImpl<SDValue> &InVals)
2573 MachineFunction &MF = DAG.getMachineFunction();
2574 MachineFrameInfo *MFI = MF.getFrameInfo();
2575 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2577 MipsFI->setVarArgsFrameIndex(0);
2579 // Used with vargs to acumulate store chains.
2580 std::vector<SDValue> OutChains;
2582 // Assign locations to all of the incoming arguments.
2583 SmallVector<CCValAssign, 16> ArgLocs;
2584 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2585 getTargetMachine(), ArgLocs, *DAG.getContext());
2586 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2587 Function::const_arg_iterator FuncArg =
2588 DAG.getMachineFunction().getFunction()->arg_begin();
2589 bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat();
2591 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
2592 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2593 MipsCCInfo.hasByValArg());
2595 unsigned CurArgIdx = 0;
2596 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2598 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2599 CCValAssign &VA = ArgLocs[i];
2600 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
2601 CurArgIdx = Ins[i].OrigArgIndex;
2602 EVT ValVT = VA.getValVT();
2603 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2604 bool IsRegLoc = VA.isRegLoc();
2606 if (Flags.isByVal()) {
2607 assert(Flags.getByValSize() &&
2608 "ByVal args of size 0 should have been ignored by front-end.");
2609 assert(ByValArg != MipsCCInfo.byval_end());
2610 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2611 MipsCCInfo, *ByValArg);
2616 // Arguments stored on registers
2618 EVT RegVT = VA.getLocVT();
2619 unsigned ArgReg = VA.getLocReg();
2620 const TargetRegisterClass *RC;
2622 if (RegVT == MVT::i32)
2623 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
2624 &Mips::GPR32RegClass;
2625 else if (RegVT == MVT::i64)
2626 RC = &Mips::GPR64RegClass;
2627 else if (RegVT == MVT::f32)
2628 RC = &Mips::FGR32RegClass;
2629 else if (RegVT == MVT::f64)
2630 RC = Subtarget->isFP64bit() ? &Mips::FGR64RegClass :
2631 &Mips::AFGR64RegClass;
2633 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2635 // Transform the arguments stored on
2636 // physical registers into virtual ones
2637 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2638 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2640 // If this is an 8 or 16-bit value, it has been passed promoted
2641 // to 32 bits. Insert an assert[sz]ext to capture this, then
2642 // truncate to the right size.
2643 if (VA.getLocInfo() != CCValAssign::Full) {
2644 unsigned Opcode = 0;
2645 if (VA.getLocInfo() == CCValAssign::SExt)
2646 Opcode = ISD::AssertSext;
2647 else if (VA.getLocInfo() == CCValAssign::ZExt)
2648 Opcode = ISD::AssertZext;
2650 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
2651 DAG.getValueType(ValVT));
2652 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
2655 // Handle floating point arguments passed in integer registers and
2656 // long double arguments passed in floating point registers.
2657 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2658 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2659 (RegVT == MVT::f64 && ValVT == MVT::i64))
2660 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2661 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2662 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2663 getNextIntArgReg(ArgReg), RC);
2664 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2665 if (!Subtarget->isLittle())
2666 std::swap(ArgValue, ArgValue2);
2667 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2668 ArgValue, ArgValue2);
2671 InVals.push_back(ArgValue);
2672 } else { // VA.isRegLoc()
2675 assert(VA.isMemLoc());
2677 // The stack pointer offset is relative to the caller stack frame.
2678 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2679 VA.getLocMemOffset(), true);
2681 // Create load nodes to retrieve arguments from the stack
2682 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2683 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN,
2684 MachinePointerInfo::getFixedStack(FI),
2685 false, false, false, 0));
2689 // The mips ABIs for returning structs by value requires that we copy
2690 // the sret argument into $v0 for the return. Save the argument into
2691 // a virtual register so that we can access it from the return points.
2692 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2693 unsigned Reg = MipsFI->getSRetReturnReg();
2695 Reg = MF.getRegInfo().
2696 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
2697 MipsFI->setSRetReturnReg(Reg);
2699 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
2700 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
2704 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
2706 // All stores are grouped in one node to allow the matching between
2707 // the size of Ins and InVals. This only happens when on varg functions
2708 if (!OutChains.empty()) {
2709 OutChains.push_back(Chain);
2710 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2711 &OutChains[0], OutChains.size());
2717 //===----------------------------------------------------------------------===//
2718 // Return Value Calling Convention Implementation
2719 //===----------------------------------------------------------------------===//
2722 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2723 MachineFunction &MF, bool IsVarArg,
2724 const SmallVectorImpl<ISD::OutputArg> &Outs,
2725 LLVMContext &Context) const {
2726 SmallVector<CCValAssign, 16> RVLocs;
2727 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
2729 return CCInfo.CheckReturn(Outs, RetCC_Mips);
2733 MipsTargetLowering::LowerReturn(SDValue Chain,
2734 CallingConv::ID CallConv, bool IsVarArg,
2735 const SmallVectorImpl<ISD::OutputArg> &Outs,
2736 const SmallVectorImpl<SDValue> &OutVals,
2737 SDLoc DL, SelectionDAG &DAG) const {
2738 // CCValAssign - represent the assignment of
2739 // the return value to a location
2740 SmallVector<CCValAssign, 16> RVLocs;
2741 MachineFunction &MF = DAG.getMachineFunction();
2743 // CCState - Info about the registers and stack slot.
2744 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
2746 MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo);
2748 // Analyze return values.
2749 MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(),
2750 MF.getFunction()->getReturnType());
2753 SmallVector<SDValue, 4> RetOps(1, Chain);
2755 // Copy the result values into the output registers.
2756 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2757 SDValue Val = OutVals[i];
2758 CCValAssign &VA = RVLocs[i];
2759 assert(VA.isRegLoc() && "Can only return in registers!");
2761 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2762 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
2764 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
2766 // Guarantee that all emitted copies are stuck together with flags.
2767 Flag = Chain.getValue(1);
2768 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2771 // The mips ABIs for returning structs by value requires that we copy
2772 // the sret argument into $v0 for the return. We saved the argument into
2773 // a virtual register in the entry block, so now we copy the value out
2775 if (MF.getFunction()->hasStructRetAttr()) {
2776 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2777 unsigned Reg = MipsFI->getSRetReturnReg();
2780 llvm_unreachable("sret virtual register not created in the entry block");
2781 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
2782 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
2784 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
2785 Flag = Chain.getValue(1);
2786 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
2789 RetOps[0] = Chain; // Update chain.
2791 // Add the flag if we have it.
2793 RetOps.push_back(Flag);
2795 // Return on Mips is always a "jr $ra"
2796 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size());
2799 //===----------------------------------------------------------------------===//
2800 // Mips Inline Assembly Support
2801 //===----------------------------------------------------------------------===//
2803 /// getConstraintType - Given a constraint letter, return the type of
2804 /// constraint it is for this target.
2805 MipsTargetLowering::ConstraintType MipsTargetLowering::
2806 getConstraintType(const std::string &Constraint) const
2808 // Mips specific constrainy
2809 // GCC config/mips/constraints.md
2811 // 'd' : An address register. Equivalent to r
2812 // unless generating MIPS16 code.
2813 // 'y' : Equivalent to r; retained for
2814 // backwards compatibility.
2815 // 'c' : A register suitable for use in an indirect
2816 // jump. This will always be $25 for -mabicalls.
2817 // 'l' : The lo register. 1 word storage.
2818 // 'x' : The hilo register pair. Double word storage.
2819 if (Constraint.size() == 1) {
2820 switch (Constraint[0]) {
2828 return C_RegisterClass;
2833 return TargetLowering::getConstraintType(Constraint);
2836 /// Examine constraint type and operand type and determine a weight value.
2837 /// This object must already have been set up with the operand type
2838 /// and the current alternative constraint selected.
2839 TargetLowering::ConstraintWeight
2840 MipsTargetLowering::getSingleConstraintMatchWeight(
2841 AsmOperandInfo &info, const char *constraint) const {
2842 ConstraintWeight weight = CW_Invalid;
2843 Value *CallOperandVal = info.CallOperandVal;
2844 // If we don't have a value, we can't do a match,
2845 // but allow it at the lowest weight.
2846 if (CallOperandVal == NULL)
2848 Type *type = CallOperandVal->getType();
2849 // Look at the constraint type.
2850 switch (*constraint) {
2852 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2856 if (type->isIntegerTy())
2857 weight = CW_Register;
2860 if (type->isFloatTy())
2861 weight = CW_Register;
2863 case 'c': // $25 for indirect jumps
2864 case 'l': // lo register
2865 case 'x': // hilo register pair
2866 if (type->isIntegerTy())
2867 weight = CW_SpecificReg;
2869 case 'I': // signed 16 bit immediate
2870 case 'J': // integer zero
2871 case 'K': // unsigned 16 bit immediate
2872 case 'L': // signed 32 bit immediate where lower 16 bits are 0
2873 case 'N': // immediate in the range of -65535 to -1 (inclusive)
2874 case 'O': // signed 15 bit immediate (+- 16383)
2875 case 'P': // immediate in the range of 65535 to 1 (inclusive)
2876 if (isa<ConstantInt>(CallOperandVal))
2877 weight = CW_Constant;
2886 /// This is a helper function to parse a physical register string and split it
2887 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
2888 /// that is returned indicates whether parsing was successful. The second flag
2889 /// is true if the numeric part exists.
2890 static std::pair<bool, bool>
2891 parsePhysicalReg(const StringRef &C, std::string &Prefix,
2892 unsigned long long &Reg) {
2893 if (C.front() != '{' || C.back() != '}')
2894 return std::make_pair(false, false);
2896 // Search for the first numeric character.
2897 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
2898 I = std::find_if(B, E, std::ptr_fun(isdigit));
2900 Prefix.assign(B, I - B);
2902 // The second flag is set to false if no numeric characters were found.
2904 return std::make_pair(true, false);
2906 // Parse the numeric characters.
2907 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
2911 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
2912 parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
2913 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2914 const TargetRegisterClass *RC;
2916 unsigned long long Reg;
2918 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
2921 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2923 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
2924 // No numeric characters follow "hi" or "lo".
2926 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2928 RC = TRI->getRegClass(Prefix == "hi" ?
2929 Mips::HI32RegClassID : Mips::LO32RegClassID);
2930 return std::make_pair(*(RC->begin()), RC);
2934 return std::make_pair((unsigned)0, (const TargetRegisterClass*)0);
2936 if (Prefix == "$f") { // Parse $f0-$f31.
2937 // If the size of FP registers is 64-bit or Reg is an even number, select
2938 // the 64-bit register class. Otherwise, select the 32-bit register class.
2939 if (VT == MVT::Other)
2940 VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
2942 RC= getRegClassFor(VT);
2944 if (RC == &Mips::AFGR64RegClass) {
2945 assert(Reg % 2 == 0);
2948 } else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7.
2949 RC = TRI->getRegClass(Mips::FCCRegClassID);
2950 } else { // Parse $0-$31.
2951 assert(Prefix == "$");
2952 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
2955 assert(Reg < RC->getNumRegs());
2956 return std::make_pair(*(RC->begin() + Reg), RC);
2959 /// Given a register class constraint, like 'r', if this corresponds directly
2960 /// to an LLVM register class, return a register of 0 and the register class
2962 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2963 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
2965 if (Constraint.size() == 1) {
2966 switch (Constraint[0]) {
2967 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2968 case 'y': // Same as 'r'. Exists for compatibility.
2970 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
2971 if (Subtarget->inMips16Mode())
2972 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
2973 return std::make_pair(0U, &Mips::GPR32RegClass);
2975 if (VT == MVT::i64 && !HasMips64)
2976 return std::make_pair(0U, &Mips::GPR32RegClass);
2977 if (VT == MVT::i64 && HasMips64)
2978 return std::make_pair(0U, &Mips::GPR64RegClass);
2979 // This will generate an error message
2980 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2983 return std::make_pair(0U, &Mips::FGR32RegClass);
2984 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
2985 if (Subtarget->isFP64bit())
2986 return std::make_pair(0U, &Mips::FGR64RegClass);
2987 return std::make_pair(0U, &Mips::AFGR64RegClass);
2990 case 'c': // register suitable for indirect jump
2992 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
2993 assert(VT == MVT::i64 && "Unexpected type.");
2994 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
2995 case 'l': // register suitable for indirect jump
2997 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
2998 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
2999 case 'x': // register suitable for indirect jump
3000 // Fixme: Not triggering the use of both hi and low
3001 // This will generate an error message
3002 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
3006 std::pair<unsigned, const TargetRegisterClass *> R;
3007 R = parseRegForInlineAsmConstraint(Constraint, VT);
3012 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3015 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3016 /// vector. If it is invalid, don't add anything to Ops.
3017 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3018 std::string &Constraint,
3019 std::vector<SDValue>&Ops,
3020 SelectionDAG &DAG) const {
3021 SDValue Result(0, 0);
3023 // Only support length 1 constraints for now.
3024 if (Constraint.length() > 1) return;
3026 char ConstraintLetter = Constraint[0];
3027 switch (ConstraintLetter) {
3028 default: break; // This will fall through to the generic implementation
3029 case 'I': // Signed 16 bit constant
3030 // If this fails, the parent routine will give an error
3031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3032 EVT Type = Op.getValueType();
3033 int64_t Val = C->getSExtValue();
3034 if (isInt<16>(Val)) {
3035 Result = DAG.getTargetConstant(Val, Type);
3040 case 'J': // integer zero
3041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3042 EVT Type = Op.getValueType();
3043 int64_t Val = C->getZExtValue();
3045 Result = DAG.getTargetConstant(0, Type);
3050 case 'K': // unsigned 16 bit immediate
3051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3052 EVT Type = Op.getValueType();
3053 uint64_t Val = (uint64_t)C->getZExtValue();
3054 if (isUInt<16>(Val)) {
3055 Result = DAG.getTargetConstant(Val, Type);
3060 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3062 EVT Type = Op.getValueType();
3063 int64_t Val = C->getSExtValue();
3064 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3065 Result = DAG.getTargetConstant(Val, Type);
3070 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3071 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3072 EVT Type = Op.getValueType();
3073 int64_t Val = C->getSExtValue();
3074 if ((Val >= -65535) && (Val <= -1)) {
3075 Result = DAG.getTargetConstant(Val, Type);
3080 case 'O': // signed 15 bit immediate
3081 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3082 EVT Type = Op.getValueType();
3083 int64_t Val = C->getSExtValue();
3084 if ((isInt<15>(Val))) {
3085 Result = DAG.getTargetConstant(Val, Type);
3090 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3091 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3092 EVT Type = Op.getValueType();
3093 int64_t Val = C->getSExtValue();
3094 if ((Val <= 65535) && (Val >= 1)) {
3095 Result = DAG.getTargetConstant(Val, Type);
3102 if (Result.getNode()) {
3103 Ops.push_back(Result);
3107 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3111 MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
3112 // No global is ever allowed as a base.
3117 case 0: // "r+i" or just "i", depending on HasBaseReg.
3120 if (!AM.HasBaseReg) // allow "r+i".
3122 return false; // disallow "r+r" or "r+r+i".
3131 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3132 // The Mips target isn't yet aware of offsets.
3136 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3138 bool IsMemset, bool ZeroMemset,
3140 MachineFunction &MF) const {
3141 if (Subtarget->hasMips64())
3147 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3148 if (VT != MVT::f32 && VT != MVT::f64)
3150 if (Imm.isNegZero())
3152 return Imm.isZero();
3155 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3157 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3159 return TargetLowering::getJumpTableEncoding();
3162 /// This function returns true if CallSym is a long double emulation routine.
3163 static bool isF128SoftLibCall(const char *CallSym) {
3164 const char *const LibCalls[] =
3165 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
3166 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
3167 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
3168 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
3169 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
3170 "__trunctfdf2", "__trunctfsf2", "__unordtf2",
3171 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
3172 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
3175 const char * const *End = LibCalls + array_lengthof(LibCalls);
3177 // Check that LibCalls is sorted alphabetically.
3178 MipsTargetLowering::LTStr Comp;
3181 for (const char * const *I = LibCalls; I < End - 1; ++I)
3182 assert(Comp(*I, *(I + 1)));
3185 return std::binary_search(LibCalls, End, CallSym, Comp);
3188 /// This function returns true if Ty is fp128 or i128 which was originally a
3190 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
3191 if (Ty->isFP128Ty())
3194 const ExternalSymbolSDNode *ES =
3195 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
3197 // If the Ty is i128 and the function being called is a long double emulation
3198 // routine, then the original type is f128.
3199 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
3202 MipsTargetLowering::MipsCC::SpecialCallingConvType
3203 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
3204 MipsCC::SpecialCallingConvType SpecialCallingConv =
3205 MipsCC::NoSpecialCallingConv;;
3206 if (Subtarget->inMips16HardFloat()) {
3207 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3208 llvm::StringRef Sym = G->getGlobal()->getName();
3209 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3210 if (F->hasFnAttribute("__Mips16RetHelper")) {
3211 SpecialCallingConv = MipsCC::Mips16RetHelperConv;
3215 return SpecialCallingConv;
3218 MipsTargetLowering::MipsCC::MipsCC(
3219 CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info,
3220 MipsCC::SpecialCallingConvType SpecialCallingConv_)
3221 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_),
3222 SpecialCallingConv(SpecialCallingConv_){
3223 // Pre-allocate reserved argument area.
3224 CCInfo.AllocateStack(reservedArgArea(), 1);
3228 void MipsTargetLowering::MipsCC::
3229 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
3230 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
3231 std::vector<ArgListEntry> &FuncArgs) {
3232 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
3233 "CallingConv::Fast shouldn't be used for vararg functions.");
3235 unsigned NumOpnds = Args.size();
3236 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
3238 for (unsigned I = 0; I != NumOpnds; ++I) {
3239 MVT ArgVT = Args[I].VT;
3240 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3243 if (ArgFlags.isByVal()) {
3244 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3248 if (IsVarArg && !Args[I].IsFixed)
3249 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3251 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
3253 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
3258 dbgs() << "Call operand #" << I << " has unhandled type "
3259 << EVT(ArgVT).getEVTString();
3261 llvm_unreachable(0);
3266 void MipsTargetLowering::MipsCC::
3267 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
3268 bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
3269 unsigned NumArgs = Args.size();
3270 llvm::CCAssignFn *FixedFn = fixedArgFn();
3271 unsigned CurArgIdx = 0;
3273 for (unsigned I = 0; I != NumArgs; ++I) {
3274 MVT ArgVT = Args[I].VT;
3275 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3276 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
3277 CurArgIdx = Args[I].OrigArgIndex;
3279 if (ArgFlags.isByVal()) {
3280 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3284 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
3286 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
3290 dbgs() << "Formal Arg #" << I << " has unhandled type "
3291 << EVT(ArgVT).getEVTString();
3293 llvm_unreachable(0);
3297 template<typename Ty>
3298 void MipsTargetLowering::MipsCC::
3299 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
3300 const SDNode *CallNode, const Type *RetTy) const {
3303 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
3304 Fn = RetCC_F128Soft;
3308 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
3309 MVT VT = RetVals[I].VT;
3310 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
3311 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
3313 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
3315 dbgs() << "Call result #" << I << " has unhandled type "
3316 << EVT(VT).getEVTString() << '\n';
3318 llvm_unreachable(0);
3323 void MipsTargetLowering::MipsCC::
3324 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
3325 const SDNode *CallNode, const Type *RetTy) const {
3326 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
3329 void MipsTargetLowering::MipsCC::
3330 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
3331 const Type *RetTy) const {
3332 analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
3336 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
3338 CCValAssign::LocInfo LocInfo,
3339 ISD::ArgFlagsTy ArgFlags) {
3340 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
3342 struct ByValArgInfo ByVal;
3343 unsigned RegSize = regSize();
3344 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
3345 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
3348 if (useRegsForByval())
3349 allocateRegs(ByVal, ByValSize, Align);
3351 // Allocate space on caller's stack.
3352 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
3354 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
3356 ByValArgs.push_back(ByVal);
3359 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
3360 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
3363 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
3364 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
3367 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
3368 return IsO32 ? O32IntRegs : Mips64IntRegs;
3371 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
3372 if (CallConv == CallingConv::Fast)
3373 return CC_Mips_FastCC;
3375 if (SpecialCallingConv == Mips16RetHelperConv)
3376 return CC_Mips16RetHelper;
3377 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN;
3380 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
3381 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg;
3384 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
3385 return IsO32 ? O32IntRegs : Mips64DPRegs;
3388 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
3391 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
3392 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
3393 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
3394 "Byval argument's size and alignment should be a multiple of"
3397 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
3399 // If Align > RegSize, the first arg register must be even.
3400 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
3401 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
3405 // Mark the registers allocated.
3406 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
3407 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
3408 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3411 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
3412 const SDNode *CallNode,
3413 bool IsSoftFloat) const {
3414 if (IsSoftFloat || IsO32)
3417 // Check if the original type was fp128.
3418 if (originalTypeIsF128(OrigTy, CallNode)) {
3419 assert(VT == MVT::i64);
3426 void MipsTargetLowering::
3427 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
3428 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3429 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3430 const MipsCC &CC, const ByValArgInfo &ByVal) const {
3431 MachineFunction &MF = DAG.getMachineFunction();
3432 MachineFrameInfo *MFI = MF.getFrameInfo();
3433 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3434 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3438 FrameObjOffset = (int)CC.reservedArgArea() -
3439 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3441 FrameObjOffset = ByVal.Address;
3443 // Create frame object.
3444 EVT PtrTy = getPointerTy();
3445 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3446 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3447 InVals.push_back(FIN);
3452 // Copy arg registers.
3453 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3454 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3456 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
3457 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3458 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3459 unsigned Offset = I * CC.regSize();
3460 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3461 DAG.getConstant(Offset, PtrTy));
3462 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3463 StorePtr, MachinePointerInfo(FuncArg, Offset),
3465 OutChains.push_back(Store);
3469 // Copy byVal arg to registers and stack.
3470 void MipsTargetLowering::
3471 passByValArg(SDValue Chain, SDLoc DL,
3472 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
3473 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3474 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
3475 const MipsCC &CC, const ByValArgInfo &ByVal,
3476 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3477 unsigned ByValSize = Flags.getByValSize();
3478 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
3479 unsigned RegSize = CC.regSize();
3480 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
3481 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
3483 if (ByVal.NumRegs) {
3484 const uint16_t *ArgRegs = CC.intArgRegs();
3485 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
3488 // Copy words to registers.
3489 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
3490 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3491 DAG.getConstant(Offset, PtrTy));
3492 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3493 MachinePointerInfo(), false, false, false,
3495 MemOpChains.push_back(LoadVal.getValue(1));
3496 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3497 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3500 // Return if the struct has been fully copied.
3501 if (ByValSize == Offset)
3504 // Copy the remainder of the byval argument with sub-word loads and shifts.
3505 if (LeftoverBytes) {
3506 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
3507 "Size of the remainder should be smaller than RegSize.");
3510 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
3511 Offset < ByValSize; LoadSize /= 2) {
3512 unsigned RemSize = ByValSize - Offset;
3514 if (RemSize < LoadSize)
3518 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3519 DAG.getConstant(Offset, PtrTy));
3521 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3522 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
3523 false, false, Alignment);
3524 MemOpChains.push_back(LoadVal.getValue(1));
3526 // Shift the loaded value.
3530 Shamt = TotalSizeLoaded;
3532 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
3534 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3535 DAG.getConstant(Shamt, MVT::i32));
3538 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3543 TotalSizeLoaded += LoadSize;
3544 Alignment = std::min(Alignment, LoadSize);
3547 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3548 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3553 // Copy remainder of byval arg to it with memcpy.
3554 unsigned MemCpySize = ByValSize - Offset;
3555 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3556 DAG.getConstant(Offset, PtrTy));
3557 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3558 DAG.getIntPtrConstant(ByVal.Address));
3559 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3560 DAG.getConstant(MemCpySize, PtrTy), Alignment,
3561 /*isVolatile=*/false, /*AlwaysInline=*/false,
3562 MachinePointerInfo(0), MachinePointerInfo(0));
3563 MemOpChains.push_back(Chain);
3567 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3568 const MipsCC &CC, SDValue Chain,
3569 SDLoc DL, SelectionDAG &DAG) const {
3570 unsigned NumRegs = CC.numIntArgRegs();
3571 const uint16_t *ArgRegs = CC.intArgRegs();
3572 const CCState &CCInfo = CC.getCCInfo();
3573 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
3574 unsigned RegSize = CC.regSize();
3575 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
3576 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3577 MachineFunction &MF = DAG.getMachineFunction();
3578 MachineFrameInfo *MFI = MF.getFrameInfo();
3579 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3581 // Offset of the first variable argument from stack pointer.
3585 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
3588 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
3590 // Record the frame index of the first variable argument
3591 // which is a value necessary to VASTART.
3592 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3593 MipsFI->setVarArgsFrameIndex(FI);
3595 // Copy the integer registers that have not been used for argument passing
3596 // to the argument register save area. For O32, the save area is allocated
3597 // in the caller's stack frame, while for N32/64, it is allocated in the
3598 // callee's stack frame.
3599 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
3600 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3601 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3602 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3603 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3604 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3605 MachinePointerInfo(), false, false, 0);
3606 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
3607 OutChains.push_back(Store);