1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::SelectCC : return "MipsISD::SelectCC";
45 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
46 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
47 case MipsISD::FPCmp : return "MipsISD::FPCmp";
48 case MipsISD::FPRound : return "MipsISD::FPRound";
49 case MipsISD::MAdd : return "MipsISD::MAdd";
50 case MipsISD::MAddu : return "MipsISD::MAddu";
51 case MipsISD::MSub : return "MipsISD::MSub";
52 case MipsISD::MSubu : return "MipsISD::MSubu";
53 case MipsISD::DivRem : return "MipsISD::DivRem";
54 case MipsISD::DivRemU : return "MipsISD::DivRemU";
55 default : return NULL;
60 MipsTargetLowering(MipsTargetMachine &TM)
61 : TargetLowering(TM, new MipsTargetObjectFile()) {
62 Subtarget = &TM.getSubtarget<MipsSubtarget>();
64 // Mips does not have i1 type, so use i32 for
65 // setcc operations results (slt, sgt, ...).
66 setBooleanContents(ZeroOrOneBooleanContent);
68 // Set up the register classes
69 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
70 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat())
74 if (!Subtarget->isFP64bit())
75 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
77 // Load extented operations for i1 types must be promoted
78 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
79 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
82 // MIPS doesn't have extending float->double load/store
83 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // Used by legalize types to correctly generate the setcc result.
87 // Without this, every float setcc comes with a AND/OR with the result,
88 // we don't want this, since the fpcmp result goes to a flag register,
89 // which is used implicitly by brcond and select operations.
90 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
92 // Mips Custom Operations
93 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
94 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
95 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
96 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
97 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
98 setOperationAction(ISD::SELECT, MVT::f32, Custom);
99 setOperationAction(ISD::SELECT, MVT::f64, Custom);
100 setOperationAction(ISD::SELECT, MVT::i32, Custom);
101 setOperationAction(ISD::SETCC, MVT::f32, Custom);
102 setOperationAction(ISD::SETCC, MVT::f64, Custom);
103 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
104 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
106 setOperationAction(ISD::VASTART, MVT::Other, Custom);
109 // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
110 // with operands comming from setcc fp comparions. This is necessary since
111 // the result from these setcc are in a flag registers (FCR31).
112 setOperationAction(ISD::AND, MVT::i32, Custom);
113 setOperationAction(ISD::OR, MVT::i32, Custom);
115 setOperationAction(ISD::SDIV, MVT::i32, Expand);
116 setOperationAction(ISD::SREM, MVT::i32, Expand);
117 setOperationAction(ISD::UDIV, MVT::i32, Expand);
118 setOperationAction(ISD::UREM, MVT::i32, Expand);
120 // Operations not directly supported by Mips.
121 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
122 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
123 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
124 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
125 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
127 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
128 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
129 setOperationAction(ISD::ROTL, MVT::i32, Expand);
131 if (!Subtarget->isMips32r2())
132 setOperationAction(ISD::ROTR, MVT::i32, Expand);
134 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
135 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
136 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
137 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
138 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
139 setOperationAction(ISD::FSIN, MVT::f32, Expand);
140 setOperationAction(ISD::FSIN, MVT::f64, Expand);
141 setOperationAction(ISD::FCOS, MVT::f32, Expand);
142 setOperationAction(ISD::FCOS, MVT::f64, Expand);
143 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
144 setOperationAction(ISD::FPOW, MVT::f32, Expand);
145 setOperationAction(ISD::FLOG, MVT::f32, Expand);
146 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
147 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
148 setOperationAction(ISD::FEXP, MVT::f32, Expand);
150 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
152 setOperationAction(ISD::VAARG, MVT::Other, Expand);
153 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
154 setOperationAction(ISD::VAEND, MVT::Other, Expand);
156 // Use the default for now
157 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
158 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
159 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
161 if (Subtarget->isSingleFloat())
162 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
164 if (!Subtarget->hasSEInReg()) {
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
166 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
169 if (!Subtarget->hasBitCount())
170 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
172 if (!Subtarget->hasSwap())
173 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
175 setTargetDAGCombine(ISD::ADDE);
176 setTargetDAGCombine(ISD::SUBE);
177 setTargetDAGCombine(ISD::SDIVREM);
178 setTargetDAGCombine(ISD::UDIVREM);
180 setStackPointerRegisterToSaveRestore(Mips::SP);
181 computeRegisterProperties();
184 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
188 /// getFunctionAlignment - Return the Log2 alignment of this function.
189 unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
194 // Transforms a subgraph in CurDAG if the following pattern is found:
195 // (addc multLo, Lo0), (adde multHi, Hi0),
197 // multHi/Lo: product of multiplication
198 // Lo0: initial value of Lo register
199 // Hi0: initial value of Hi register
200 // Return true if pattern matching was successful.
201 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
202 // ADDENode's second operand must be a flag output of an ADDC node in order
203 // for the matching to be successful.
204 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
206 if (ADDCNode->getOpcode() != ISD::ADDC)
209 SDValue MultHi = ADDENode->getOperand(0);
210 SDValue MultLo = ADDCNode->getOperand(0);
211 SDNode* MultNode = MultHi.getNode();
212 unsigned MultOpc = MultHi.getOpcode();
214 // MultHi and MultLo must be generated by the same node,
215 if (MultLo.getNode() != MultNode)
218 // and it must be a multiplication.
219 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
222 // MultLo amd MultHi must be the first and second output of MultNode
224 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
227 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
228 // of the values of MultNode, in which case MultNode will be removed in later
230 // If there exist users other than ADDENode or ADDCNode, this function returns
231 // here, which will result in MultNode being mapped to a single MULT
232 // instruction node rather than a pair of MULT and MADD instructions being
234 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
237 SDValue Chain = CurDAG->getEntryNode();
238 DebugLoc dl = ADDENode->getDebugLoc();
240 // create MipsMAdd(u) node
241 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
243 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
245 MultNode->getOperand(0),// Factor 0
246 MultNode->getOperand(1),// Factor 1
247 ADDCNode->getOperand(1),// Lo0
248 ADDENode->getOperand(1));// Hi0
250 // create CopyFromReg nodes
251 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
253 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
255 CopyFromLo.getValue(2));
257 // replace uses of adde and addc here
258 if (!SDValue(ADDCNode, 0).use_empty())
259 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
261 if (!SDValue(ADDENode, 0).use_empty())
262 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
268 // Transforms a subgraph in CurDAG if the following pattern is found:
269 // (addc Lo0, multLo), (sube Hi0, multHi),
271 // multHi/Lo: product of multiplication
272 // Lo0: initial value of Lo register
273 // Hi0: initial value of Hi register
274 // Return true if pattern matching was successful.
275 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
276 // SUBENode's second operand must be a flag output of an SUBC node in order
277 // for the matching to be successful.
278 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
280 if (SUBCNode->getOpcode() != ISD::SUBC)
283 SDValue MultHi = SUBENode->getOperand(1);
284 SDValue MultLo = SUBCNode->getOperand(1);
285 SDNode* MultNode = MultHi.getNode();
286 unsigned MultOpc = MultHi.getOpcode();
288 // MultHi and MultLo must be generated by the same node,
289 if (MultLo.getNode() != MultNode)
292 // and it must be a multiplication.
293 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
296 // MultLo amd MultHi must be the first and second output of MultNode
298 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
301 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
302 // of the values of MultNode, in which case MultNode will be removed in later
304 // If there exist users other than SUBENode or SUBCNode, this function returns
305 // here, which will result in MultNode being mapped to a single MULT
306 // instruction node rather than a pair of MULT and MSUB instructions being
308 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
311 SDValue Chain = CurDAG->getEntryNode();
312 DebugLoc dl = SUBENode->getDebugLoc();
314 // create MipsSub(u) node
315 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
317 SDValue MSub = CurDAG->getNode(MultOpc, dl,
319 MultNode->getOperand(0),// Factor 0
320 MultNode->getOperand(1),// Factor 1
321 SUBCNode->getOperand(0),// Lo0
322 SUBENode->getOperand(0));// Hi0
324 // create CopyFromReg nodes
325 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
327 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
329 CopyFromLo.getValue(2));
331 // replace uses of sube and subc here
332 if (!SDValue(SUBCNode, 0).use_empty())
333 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
335 if (!SDValue(SUBENode, 0).use_empty())
336 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
341 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
342 TargetLowering::DAGCombinerInfo &DCI,
343 const MipsSubtarget* Subtarget) {
344 if (DCI.isBeforeLegalize())
347 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
348 return SDValue(N, 0);
353 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
354 TargetLowering::DAGCombinerInfo &DCI,
355 const MipsSubtarget* Subtarget) {
356 if (DCI.isBeforeLegalize())
359 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
360 return SDValue(N, 0);
365 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
366 TargetLowering::DAGCombinerInfo &DCI,
367 const MipsSubtarget* Subtarget) {
368 if (DCI.isBeforeLegalizeOps())
371 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
373 DebugLoc dl = N->getDebugLoc();
375 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
376 N->getOperand(0), N->getOperand(1));
377 SDValue InChain = DAG.getEntryNode();
378 SDValue InGlue = DivRem;
381 if (N->hasAnyUseOfValue(0)) {
382 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
384 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
385 InChain = CopyFromLo.getValue(1);
386 InGlue = CopyFromLo.getValue(2);
390 if (N->hasAnyUseOfValue(1)) {
391 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
392 Mips::HI, MVT::i32, InGlue);
393 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
399 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
401 SelectionDAG &DAG = DCI.DAG;
402 unsigned opc = N->getOpcode();
407 return PerformADDECombine(N, DAG, DCI, Subtarget);
409 return PerformSUBECombine(N, DAG, DCI, Subtarget);
412 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
418 SDValue MipsTargetLowering::
419 LowerOperation(SDValue Op, SelectionDAG &DAG) const
421 switch (Op.getOpcode())
423 case ISD::AND: return LowerANDOR(Op, DAG);
424 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
425 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
426 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
427 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
428 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
429 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
430 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
431 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
432 case ISD::OR: return LowerANDOR(Op, DAG);
433 case ISD::SELECT: return LowerSELECT(Op, DAG);
434 case ISD::SETCC: return LowerSETCC(Op, DAG);
435 case ISD::VASTART: return LowerVASTART(Op, DAG);
440 //===----------------------------------------------------------------------===//
441 // Lower helper functions
442 //===----------------------------------------------------------------------===//
444 // AddLiveIn - This helper function adds the specified physical register to the
445 // MachineFunction as a live in value. It also creates a corresponding
446 // virtual register for it.
448 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
450 assert(RC->contains(PReg) && "Not the correct regclass!");
451 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
452 MF.getRegInfo().addLiveIn(PReg, VReg);
456 // Get fp branch code (not opcode) from condition code.
457 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
458 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
459 return Mips::BRANCH_T;
461 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
462 return Mips::BRANCH_F;
464 return Mips::BRANCH_INVALID;
467 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
470 llvm_unreachable("Unknown branch code");
471 case Mips::BRANCH_T : return Mips::BC1T;
472 case Mips::BRANCH_F : return Mips::BC1F;
473 case Mips::BRANCH_TL : return Mips::BC1TL;
474 case Mips::BRANCH_FL : return Mips::BC1FL;
478 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
480 default: llvm_unreachable("Unknown fp condition code!");
482 case ISD::SETOEQ: return Mips::FCOND_EQ;
483 case ISD::SETUNE: return Mips::FCOND_OGL;
485 case ISD::SETOLT: return Mips::FCOND_OLT;
487 case ISD::SETOGT: return Mips::FCOND_OGT;
489 case ISD::SETOLE: return Mips::FCOND_OLE;
491 case ISD::SETOGE: return Mips::FCOND_OGE;
492 case ISD::SETULT: return Mips::FCOND_ULT;
493 case ISD::SETULE: return Mips::FCOND_ULE;
494 case ISD::SETUGT: return Mips::FCOND_UGT;
495 case ISD::SETUGE: return Mips::FCOND_UGE;
496 case ISD::SETUO: return Mips::FCOND_UN;
497 case ISD::SETO: return Mips::FCOND_OR;
499 case ISD::SETONE: return Mips::FCOND_NEQ;
500 case ISD::SETUEQ: return Mips::FCOND_UEQ;
505 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
506 MachineBasicBlock *BB) const {
507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
508 bool isFPCmp = false;
509 DebugLoc dl = MI->getDebugLoc();
511 switch (MI->getOpcode()) {
512 default: assert(false && "Unexpected instr type to insert");
513 case Mips::Select_FCC:
514 case Mips::Select_FCC_S32:
515 case Mips::Select_FCC_D32:
516 isFPCmp = true; // FALL THROUGH
517 case Mips::Select_CC:
518 case Mips::Select_CC_S32:
519 case Mips::Select_CC_D32: {
520 // To "insert" a SELECT_CC instruction, we actually have to insert the
521 // diamond control-flow pattern. The incoming instruction knows the
522 // destination vreg to set, the condition code register to branch on, the
523 // true/false values to select between, and a branch opcode to use.
524 const BasicBlock *LLVM_BB = BB->getBasicBlock();
525 MachineFunction::iterator It = BB;
532 // bNE r1, r0, copy1MBB
533 // fallthrough --> copy0MBB
534 MachineBasicBlock *thisMBB = BB;
535 MachineFunction *F = BB->getParent();
536 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
537 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
538 F->insert(It, copy0MBB);
539 F->insert(It, sinkMBB);
541 // Transfer the remainder of BB and its successor edges to sinkMBB.
542 sinkMBB->splice(sinkMBB->begin(), BB,
543 llvm::next(MachineBasicBlock::iterator(MI)),
545 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
547 // Next, add the true and fallthrough blocks as its successors.
548 BB->addSuccessor(copy0MBB);
549 BB->addSuccessor(sinkMBB);
551 // Emit the right instruction according to the type of the operands compared
553 // Find the condiction code present in the setcc operation.
554 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
555 // Get the branch opcode from the branch code.
556 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
557 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
559 BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
560 .addReg(Mips::ZERO).addMBB(sinkMBB);
564 // # fallthrough to sinkMBB
567 // Update machine-CFG edges
568 BB->addSuccessor(sinkMBB);
571 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
574 BuildMI(*BB, BB->begin(), dl,
575 TII->get(Mips::PHI), MI->getOperand(0).getReg())
576 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
577 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
579 MI->eraseFromParent(); // The pseudo instruction is gone now.
585 //===----------------------------------------------------------------------===//
586 // Misc Lower Operation implementation
587 //===----------------------------------------------------------------------===//
589 SDValue MipsTargetLowering::
590 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
592 if (!Subtarget->isMips1())
595 MachineFunction &MF = DAG.getMachineFunction();
596 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
598 SDValue Chain = DAG.getEntryNode();
599 DebugLoc dl = Op.getDebugLoc();
600 SDValue Src = Op.getOperand(0);
602 // Set the condition register
603 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
604 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
605 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
607 SDValue Cst = DAG.getConstant(3, MVT::i32);
608 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
609 Cst = DAG.getConstant(2, MVT::i32);
610 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
612 SDValue InFlag(0, 0);
613 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
615 // Emit the round instruction and bit convert to integer
616 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
617 Src, CondReg.getValue(1));
618 SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
622 SDValue MipsTargetLowering::
623 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
625 SDValue Chain = Op.getOperand(0);
626 SDValue Size = Op.getOperand(1);
627 DebugLoc dl = Op.getDebugLoc();
629 // Get a reference from Mips stack pointer
630 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
632 // Subtract the dynamic size from the actual stack size to
633 // obtain the new stack size.
634 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
636 // The Sub result contains the new stack start address, so it
637 // must be placed in the stack pointer register.
638 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
640 // This node always has two return values: a new stack pointer
642 SDValue Ops[2] = { Sub, Chain };
643 return DAG.getMergeValues(Ops, 2, dl);
646 SDValue MipsTargetLowering::
647 LowerANDOR(SDValue Op, SelectionDAG &DAG) const
649 SDValue LHS = Op.getOperand(0);
650 SDValue RHS = Op.getOperand(1);
651 DebugLoc dl = Op.getDebugLoc();
653 if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
656 SDValue True = DAG.getConstant(1, MVT::i32);
657 SDValue False = DAG.getConstant(0, MVT::i32);
659 SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
660 LHS, True, False, LHS.getOperand(2));
661 SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
662 RHS, True, False, RHS.getOperand(2));
664 return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
667 SDValue MipsTargetLowering::
668 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
670 // The first operand is the chain, the second is the condition, the third is
671 // the block to branch to if the condition is true.
672 SDValue Chain = Op.getOperand(0);
673 SDValue Dest = Op.getOperand(2);
674 DebugLoc dl = Op.getDebugLoc();
676 if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
679 SDValue CondRes = Op.getOperand(1);
680 SDValue CCNode = CondRes.getOperand(2);
682 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
683 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
685 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
689 SDValue MipsTargetLowering::
690 LowerSETCC(SDValue Op, SelectionDAG &DAG) const
692 // The operands to this are the left and right operands to compare (ops #0,
693 // and #1) and the condition code to compare them with (op #2) as a
695 SDValue LHS = Op.getOperand(0);
696 SDValue RHS = Op.getOperand(1);
697 DebugLoc dl = Op.getDebugLoc();
699 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
701 return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
702 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
705 SDValue MipsTargetLowering::
706 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
708 SDValue Cond = Op.getOperand(0);
709 SDValue True = Op.getOperand(1);
710 SDValue False = Op.getOperand(2);
711 DebugLoc dl = Op.getDebugLoc();
713 // if the incomming condition comes from a integer compare, the select
714 // operation must be SelectCC or a conditional move if the subtarget
716 if (Cond.getOpcode() != MipsISD::FPCmp) {
717 if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
719 return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
723 // if the incomming condition comes from fpcmp, the select
724 // operation must use FPSelectCC.
725 SDValue CCNode = Cond.getOperand(2);
726 return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
727 Cond, True, False, CCNode);
730 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
731 SelectionDAG &DAG) const {
732 // FIXME there isn't actually debug info here
733 DebugLoc dl = Op.getDebugLoc();
734 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
736 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
737 SDVTList VTs = DAG.getVTList(MVT::i32);
739 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
741 // %gp_rel relocation
742 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
743 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
745 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
746 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
747 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
749 // %hi/%lo relocation
750 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
751 MipsII::MO_ABS_HILO);
752 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
753 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
754 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
757 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
759 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
760 DAG.getEntryNode(), GA, MachinePointerInfo(),
762 // On functions and global targets not internal linked only
763 // a load from got/GP is necessary for PIC to work.
764 if (!GV->hasLocalLinkage() || isa<Function>(GV))
766 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
767 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
770 llvm_unreachable("Dont know how to handle GlobalAddress");
774 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
775 SelectionDAG &DAG) const {
776 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
777 assert(false && "implement LowerBlockAddress for -static");
778 return SDValue(0, 0);
781 // FIXME there isn't actually debug info here
782 DebugLoc dl = Op.getDebugLoc();
783 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
784 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
786 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
787 MipsII::MO_ABS_HILO);
788 SDValue Load = DAG.getLoad(MVT::i32, dl,
789 DAG.getEntryNode(), BAGOTOffset,
790 MachinePointerInfo(), false, false, 0);
791 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
792 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
796 SDValue MipsTargetLowering::
797 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
799 llvm_unreachable("TLS not implemented for MIPS.");
800 return SDValue(); // Not reached
803 SDValue MipsTargetLowering::
804 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
808 // FIXME there isn't actually debug info here
809 DebugLoc dl = Op.getDebugLoc();
810 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
811 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
813 EVT PtrVT = Op.getValueType();
814 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
816 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
819 SDValue Ops[] = { JTI };
820 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
821 } else // Emit Load from Global Pointer
822 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
823 MachinePointerInfo(),
826 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
827 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
832 SDValue MipsTargetLowering::
833 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
836 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
837 const Constant *C = N->getConstVal();
838 // FIXME there isn't actually debug info here
839 DebugLoc dl = Op.getDebugLoc();
842 // FIXME: we should reference the constant pool using small data sections,
843 // but the asm printer currently doens't support this feature without
844 // hacking it. This feature should come soon so we can uncomment the
846 //if (IsInSmallSection(C->getType())) {
847 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
848 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
849 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
851 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
852 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
853 N->getOffset(), MipsII::MO_ABS_HILO);
854 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
855 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
856 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
858 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
859 N->getOffset(), MipsII::MO_GOT);
860 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
861 CP, MachinePointerInfo::getConstantPool(),
863 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
864 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
870 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
871 MachineFunction &MF = DAG.getMachineFunction();
872 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
874 DebugLoc dl = Op.getDebugLoc();
875 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
878 // vastart just stores the address of the VarArgsFrameIndex slot into the
879 // memory location argument.
880 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
881 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
882 MachinePointerInfo(SV),
886 //===----------------------------------------------------------------------===//
887 // Calling Convention Implementation
888 //===----------------------------------------------------------------------===//
890 #include "MipsGenCallingConv.inc"
892 //===----------------------------------------------------------------------===//
893 // TODO: Implement a generic logic using tblgen that can support this.
894 // Mips O32 ABI rules:
896 // i32 - Passed in A0, A1, A2, A3 and stack
897 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
898 // an argument. Otherwise, passed in A1, A2, A3 and stack.
899 // f64 - Only passed in two aliased f32 registers if no int reg has been used
900 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
901 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
903 //===----------------------------------------------------------------------===//
905 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
906 MVT LocVT, CCValAssign::LocInfo LocInfo,
907 ISD::ArgFlagsTy ArgFlags, CCState &State) {
909 static const unsigned IntRegsSize=4, FloatRegsSize=2;
911 static const unsigned IntRegs[] = {
912 Mips::A0, Mips::A1, Mips::A2, Mips::A3
914 static const unsigned F32Regs[] = {
917 static const unsigned F64Regs[] = {
922 static bool IntRegUsed = false;
924 // This must be the first arg of the call if no regs have been allocated.
925 // Initialize IntRegUsed in that case.
926 if (IntRegs[State.getFirstUnallocated(IntRegs, IntRegsSize)] == Mips::A0 &&
927 F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] == Mips::F12 &&
928 F64Regs[State.getFirstUnallocated(F64Regs, FloatRegsSize)] == Mips::D6)
931 // Promote i8 and i16
932 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
934 if (ArgFlags.isSExt())
935 LocInfo = CCValAssign::SExt;
936 else if (ArgFlags.isZExt())
937 LocInfo = CCValAssign::ZExt;
939 LocInfo = CCValAssign::AExt;
942 if (ValVT == MVT::i32) {
943 Reg = State.AllocateReg(IntRegs, IntRegsSize);
945 } else if (ValVT == MVT::f32) {
946 // An int reg has to be marked allocated regardless of whether or not
947 // IntRegUsed is true.
948 Reg = State.AllocateReg(IntRegs, IntRegsSize);
951 if (Reg) // Int reg is available
954 unsigned FReg = State.AllocateReg(F32Regs, FloatRegsSize);
955 if (FReg) // F32 reg is available
957 else if (Reg) // No F32 regs are available, but an int reg is available.
960 } else if (ValVT == MVT::f64) {
961 // Int regs have to be marked allocated regardless of whether or not
962 // IntRegUsed is true.
963 Reg = State.AllocateReg(IntRegs, IntRegsSize);
965 Reg = State.AllocateReg(IntRegs, IntRegsSize);
966 else if (Reg == Mips::A3)
968 State.AllocateReg(IntRegs, IntRegsSize);
970 // At this point, Reg is A0, A2 or 0, and all the unavailable integer regs
971 // are marked as allocated.
973 if (Reg)// if int reg is available
976 unsigned FReg = State.AllocateReg(F64Regs, FloatRegsSize);
977 if (FReg) // F64 reg is available.
979 else if (Reg) // No F64 regs are available, but an int reg is available.
983 assert(false && "cannot handle this ValVT");
986 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
987 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
988 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
990 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
992 return false; // CC must always match
995 static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT,
996 MVT LocVT, CCValAssign::LocInfo LocInfo,
997 ISD::ArgFlagsTy ArgFlags, CCState &State) {
999 static const unsigned IntRegsSize=4;
1001 static const unsigned IntRegs[] = {
1002 Mips::A0, Mips::A1, Mips::A2, Mips::A3
1005 // Promote i8 and i16
1006 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
1008 if (ArgFlags.isSExt())
1009 LocInfo = CCValAssign::SExt;
1010 else if (ArgFlags.isZExt())
1011 LocInfo = CCValAssign::ZExt;
1013 LocInfo = CCValAssign::AExt;
1018 if (ValVT == MVT::i32 || ValVT == MVT::f32) {
1019 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1021 } else if (ValVT == MVT::f64) {
1022 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1023 if (Reg == Mips::A1 || Reg == Mips::A3)
1024 Reg = State.AllocateReg(IntRegs, IntRegsSize);
1025 State.AllocateReg(IntRegs, IntRegsSize);
1028 llvm_unreachable("Cannot handle this ValVT.");
1031 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1032 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
1033 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1035 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1037 return false; // CC must always match
1040 //===----------------------------------------------------------------------===//
1041 // Call Calling Convention Implementation
1042 //===----------------------------------------------------------------------===//
1044 /// LowerCall - functions arguments are copied from virtual regs to
1045 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1046 /// TODO: isTailCall.
1048 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1049 CallingConv::ID CallConv, bool isVarArg,
1051 const SmallVectorImpl<ISD::OutputArg> &Outs,
1052 const SmallVectorImpl<SDValue> &OutVals,
1053 const SmallVectorImpl<ISD::InputArg> &Ins,
1054 DebugLoc dl, SelectionDAG &DAG,
1055 SmallVectorImpl<SDValue> &InVals) const {
1056 // MIPs target does not yet support tail call optimization.
1059 MachineFunction &MF = DAG.getMachineFunction();
1060 MachineFrameInfo *MFI = MF.getFrameInfo();
1061 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1063 // Analyze operands of the call, assigning locations to each operand.
1064 SmallVector<CCValAssign, 16> ArgLocs;
1065 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1068 // To meet O32 ABI, Mips must always allocate 16 bytes on
1069 // the stack (even if less than 4 are used as arguments)
1070 if (Subtarget->isABI_O32()) {
1071 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
1072 MFI->CreateFixedObject(VTsize, (VTsize*3), true);
1073 CCInfo.AnalyzeCallOperands(Outs,
1074 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1076 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1078 // Get a count of how many bytes are to be pushed on the stack.
1079 unsigned NumBytes = CCInfo.getNextStackOffset();
1080 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1082 // With EABI is it possible to have 16 args on registers.
1083 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1084 SmallVector<SDValue, 8> MemOpChains;
1086 // First/LastArgStackLoc contains the first/last
1087 // "at stack" argument location.
1088 int LastArgStackLoc = 0;
1089 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1091 // Walk the register/memloc assignments, inserting copies/loads.
1092 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1093 SDValue Arg = OutVals[i];
1094 CCValAssign &VA = ArgLocs[i];
1096 // Promote the value if needed.
1097 switch (VA.getLocInfo()) {
1098 default: llvm_unreachable("Unknown loc info!");
1099 case CCValAssign::Full:
1100 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1101 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1102 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1103 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1104 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
1105 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
1106 DAG.getConstant(0, getPointerTy()));
1107 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
1108 DAG.getConstant(1, getPointerTy()));
1109 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1110 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1115 case CCValAssign::SExt:
1116 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1118 case CCValAssign::ZExt:
1119 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1121 case CCValAssign::AExt:
1122 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1126 // Arguments that can be passed on register must be kept at
1127 // RegsToPass vector
1128 if (VA.isRegLoc()) {
1129 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1133 // Register can't get to this point...
1134 assert(VA.isMemLoc());
1136 // Create the frame index object for this incoming parameter
1137 // This guarantees that when allocating Local Area the firsts
1138 // 16 bytes which are alwayes reserved won't be overwritten
1139 // if O32 ABI is used. For EABI the first address is zero.
1140 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
1141 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1142 LastArgStackLoc, true);
1144 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
1146 // emit ISD::STORE whichs stores the
1147 // parameter value to a stack Location
1148 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1149 MachinePointerInfo(),
1153 // Transform all store nodes into one single node because all store
1154 // nodes are independent of each other.
1155 if (!MemOpChains.empty())
1156 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1157 &MemOpChains[0], MemOpChains.size());
1159 // Build a sequence of copy-to-reg nodes chained together with token
1160 // chain and flag operands which copy the outgoing args into registers.
1161 // The InFlag in necessary since all emited instructions must be
1164 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1165 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1166 RegsToPass[i].second, InFlag);
1167 InFlag = Chain.getValue(1);
1170 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1171 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1172 // node so that legalize doesn't hack it.
1173 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1174 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1175 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1176 getPointerTy(), 0, OpFlag);
1177 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1178 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1179 getPointerTy(), OpFlag);
1181 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1182 // = Chain, Callee, Reg#1, Reg#2, ...
1184 // Returns a chain & a flag for retval copy to use.
1185 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1186 SmallVector<SDValue, 8> Ops;
1187 Ops.push_back(Chain);
1188 Ops.push_back(Callee);
1190 // Add argument registers to the end of the list so that they are
1191 // known live into the call.
1192 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1193 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1194 RegsToPass[i].second.getValueType()));
1196 if (InFlag.getNode())
1197 Ops.push_back(InFlag);
1199 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1200 InFlag = Chain.getValue(1);
1202 // Create a stack location to hold GP when PIC is used. This stack
1203 // location is used on function prologue to save GP and also after all
1204 // emited CALL's to restore GP.
1206 // Function can have an arbitrary number of calls, so
1207 // hold the LastArgStackLoc with the biggest offset.
1209 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1210 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
1211 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
1212 // Create the frame index only once. SPOffset here can be anything
1213 // (this will be fixed on processFunctionBeforeFrameFinalized)
1214 if (MipsFI->getGPStackOffset() == -1) {
1215 FI = MFI->CreateFixedObject(4, 0, true);
1216 MipsFI->setGPFI(FI);
1218 MipsFI->setGPStackOffset(LastArgStackLoc);
1222 FI = MipsFI->getGPFI();
1223 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1224 SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN,
1225 MachinePointerInfo::getFixedStack(FI),
1227 Chain = GPLoad.getValue(1);
1228 Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
1229 GPLoad, SDValue(0,0));
1230 InFlag = Chain.getValue(1);
1233 // Create the CALLSEQ_END node.
1234 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1235 DAG.getIntPtrConstant(0, true), InFlag);
1236 InFlag = Chain.getValue(1);
1238 // Handle result values, copying them out of physregs into vregs that we
1240 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1241 Ins, dl, DAG, InVals);
1244 /// LowerCallResult - Lower the result values of a call into the
1245 /// appropriate copies out of appropriate physical registers.
1247 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1248 CallingConv::ID CallConv, bool isVarArg,
1249 const SmallVectorImpl<ISD::InputArg> &Ins,
1250 DebugLoc dl, SelectionDAG &DAG,
1251 SmallVectorImpl<SDValue> &InVals) const {
1253 // Assign locations to each value returned by this call.
1254 SmallVector<CCValAssign, 16> RVLocs;
1255 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1256 RVLocs, *DAG.getContext());
1258 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1260 // Copy all of the result registers out of their specified physreg.
1261 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1262 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1263 RVLocs[i].getValVT(), InFlag).getValue(1);
1264 InFlag = Chain.getValue(2);
1265 InVals.push_back(Chain.getValue(0));
1271 //===----------------------------------------------------------------------===//
1272 // Formal Arguments Calling Convention Implementation
1273 //===----------------------------------------------------------------------===//
1275 /// LowerFormalArguments - transform physical registers into virtual registers
1276 /// and generate load operations for arguments places on the stack.
1278 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
1279 CallingConv::ID CallConv, bool isVarArg,
1280 const SmallVectorImpl<ISD::InputArg>
1282 DebugLoc dl, SelectionDAG &DAG,
1283 SmallVectorImpl<SDValue> &InVals)
1286 MachineFunction &MF = DAG.getMachineFunction();
1287 MachineFrameInfo *MFI = MF.getFrameInfo();
1288 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1290 MipsFI->setVarArgsFrameIndex(0);
1292 // Used with vargs to acumulate store chains.
1293 std::vector<SDValue> OutChains;
1295 // Keep track of the last register used for arguments
1296 unsigned ArgRegEnd = 0;
1298 // Assign locations to all of the incoming arguments.
1299 SmallVector<CCValAssign, 16> ArgLocs;
1300 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1301 ArgLocs, *DAG.getContext());
1303 if (Subtarget->isABI_O32())
1304 CCInfo.AnalyzeFormalArguments(Ins,
1305 isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
1307 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1309 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1310 unsigned LastStackArgEndOffset = 0;
1311 EVT LastRegArgValVT;
1313 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1314 CCValAssign &VA = ArgLocs[i];
1316 // Arguments stored on registers
1317 if (VA.isRegLoc()) {
1318 EVT RegVT = VA.getLocVT();
1319 ArgRegEnd = VA.getLocReg();
1320 LastRegArgValVT = VA.getValVT();
1321 TargetRegisterClass *RC = 0;
1323 if (RegVT == MVT::i32)
1324 RC = Mips::CPURegsRegisterClass;
1325 else if (RegVT == MVT::f32)
1326 RC = Mips::FGR32RegisterClass;
1327 else if (RegVT == MVT::f64) {
1328 if (!Subtarget->isSingleFloat())
1329 RC = Mips::AFGR64RegisterClass;
1331 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1333 // Transform the arguments stored on
1334 // physical registers into virtual ones
1335 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1336 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1338 // If this is an 8 or 16-bit value, it has been passed promoted
1339 // to 32 bits. Insert an assert[sz]ext to capture this, then
1340 // truncate to the right size.
1341 if (VA.getLocInfo() != CCValAssign::Full) {
1342 unsigned Opcode = 0;
1343 if (VA.getLocInfo() == CCValAssign::SExt)
1344 Opcode = ISD::AssertSext;
1345 else if (VA.getLocInfo() == CCValAssign::ZExt)
1346 Opcode = ISD::AssertZext;
1348 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1349 DAG.getValueType(VA.getValVT()));
1350 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1353 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1354 if (Subtarget->isABI_O32()) {
1355 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1356 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1357 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1358 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1359 VA.getLocReg()+1, RC);
1360 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1361 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, ArgValue,
1363 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Pair);
1367 InVals.push_back(ArgValue);
1368 } else { // VA.isRegLoc()
1371 assert(VA.isMemLoc());
1373 // The last argument is not a register anymore
1376 // The stack pointer offset is relative to the caller stack frame.
1377 // Since the real stack size is unknown here, a negative SPOffset
1378 // is used so there's a way to adjust these offsets when the stack
1379 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1380 // used instead of a direct negative address (which is recorded to
1381 // be used on emitPrologue) to avoid mis-calc of the first stack
1382 // offset on PEI::calculateFrameObjectOffsets.
1383 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
1384 LastStackArgEndOffset = FirstStackArgLoc + VA.getLocMemOffset() + ArgSize;
1385 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
1386 MipsFI->recordLoadArgsFI(FI, -(4 +
1387 (FirstStackArgLoc + VA.getLocMemOffset())));
1389 // Create load nodes to retrieve arguments from the stack
1390 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1391 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1392 MachinePointerInfo::getFixedStack(FI),
1397 // The mips ABIs for returning structs by value requires that we copy
1398 // the sret argument into $v0 for the return. Save the argument into
1399 // a virtual register so that we can access it from the return points.
1400 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1401 unsigned Reg = MipsFI->getSRetReturnReg();
1403 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1404 MipsFI->setSRetReturnReg(Reg);
1406 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1407 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1410 // To meet ABI, when VARARGS are passed on registers, the registers
1411 // must have their values written to the caller stack frame. If the last
1412 // argument was placed in the stack, there's no need to save any register.
1413 if (isVarArg && Subtarget->isABI_O32()) {
1415 // Last named formal argument is passed in register.
1417 // The last register argument that must be saved is Mips::A3
1418 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1419 if (LastRegArgValVT == MVT::f64)
1422 if (ArgRegEnd < Mips::A3) {
1423 // Both the last named formal argument and the first variable
1424 // argument are passed in registers.
1425 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd) {
1426 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1427 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1429 int FI = MFI->CreateFixedObject(4, 0, true);
1430 MipsFI->recordStoreVarArgsFI(FI, -(4+(ArgRegEnd-Mips::A0)*4));
1431 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1432 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
1433 MachinePointerInfo(),
1436 // Record the frame index of the first variable argument
1437 // which is a value necessary to VASTART.
1438 if (!MipsFI->getVarArgsFrameIndex()) {
1439 MFI->setObjectAlignment(FI, 4);
1440 MipsFI->setVarArgsFrameIndex(FI);
1444 // Last named formal argument is in register Mips::A3, and the first
1445 // variable argument is on stack. Record the frame index of the first
1446 // variable argument.
1447 int FI = MFI->CreateFixedObject(4, 0, true);
1448 MFI->setObjectAlignment(FI, 4);
1449 MipsFI->recordStoreVarArgsFI(FI, -20);
1450 MipsFI->setVarArgsFrameIndex(FI);
1453 // Last named formal argument and all the variable arguments are passed
1454 // on stack. Record the frame index of the first variable argument.
1455 int FI = MFI->CreateFixedObject(4, 0, true);
1456 MFI->setObjectAlignment(FI, 4);
1457 MipsFI->recordStoreVarArgsFI(FI, -(4+LastStackArgEndOffset));
1458 MipsFI->setVarArgsFrameIndex(FI);
1462 // All stores are grouped in one node to allow the matching between
1463 // the size of Ins and InVals. This only happens when on varg functions
1464 if (!OutChains.empty()) {
1465 OutChains.push_back(Chain);
1466 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1467 &OutChains[0], OutChains.size());
1473 //===----------------------------------------------------------------------===//
1474 // Return Value Calling Convention Implementation
1475 //===----------------------------------------------------------------------===//
1478 MipsTargetLowering::LowerReturn(SDValue Chain,
1479 CallingConv::ID CallConv, bool isVarArg,
1480 const SmallVectorImpl<ISD::OutputArg> &Outs,
1481 const SmallVectorImpl<SDValue> &OutVals,
1482 DebugLoc dl, SelectionDAG &DAG) const {
1484 // CCValAssign - represent the assignment of
1485 // the return value to a location
1486 SmallVector<CCValAssign, 16> RVLocs;
1488 // CCState - Info about the registers and stack slot.
1489 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1490 RVLocs, *DAG.getContext());
1492 // Analize return values.
1493 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1495 // If this is the first return lowered for this function, add
1496 // the regs to the liveout set for the function.
1497 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1498 for (unsigned i = 0; i != RVLocs.size(); ++i)
1499 if (RVLocs[i].isRegLoc())
1500 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1505 // Copy the result values into the output registers.
1506 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1507 CCValAssign &VA = RVLocs[i];
1508 assert(VA.isRegLoc() && "Can only return in registers!");
1510 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1513 // guarantee that all emitted copies are
1514 // stuck together, avoiding something bad
1515 Flag = Chain.getValue(1);
1518 // The mips ABIs for returning structs by value requires that we copy
1519 // the sret argument into $v0 for the return. We saved the argument into
1520 // a virtual register in the entry block, so now we copy the value out
1522 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1523 MachineFunction &MF = DAG.getMachineFunction();
1524 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1525 unsigned Reg = MipsFI->getSRetReturnReg();
1528 llvm_unreachable("sret virtual register not created in the entry block");
1529 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1531 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1532 Flag = Chain.getValue(1);
1535 // Return on Mips is always a "jr $ra"
1537 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1538 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1540 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1541 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1544 //===----------------------------------------------------------------------===//
1545 // Mips Inline Assembly Support
1546 //===----------------------------------------------------------------------===//
1548 /// getConstraintType - Given a constraint letter, return the type of
1549 /// constraint it is for this target.
1550 MipsTargetLowering::ConstraintType MipsTargetLowering::
1551 getConstraintType(const std::string &Constraint) const
1553 // Mips specific constrainy
1554 // GCC config/mips/constraints.md
1556 // 'd' : An address register. Equivalent to r
1557 // unless generating MIPS16 code.
1558 // 'y' : Equivalent to r; retained for
1559 // backwards compatibility.
1560 // 'f' : Floating Point registers.
1561 if (Constraint.size() == 1) {
1562 switch (Constraint[0]) {
1567 return C_RegisterClass;
1571 return TargetLowering::getConstraintType(Constraint);
1574 /// Examine constraint type and operand type and determine a weight value.
1575 /// This object must already have been set up with the operand type
1576 /// and the current alternative constraint selected.
1577 TargetLowering::ConstraintWeight
1578 MipsTargetLowering::getSingleConstraintMatchWeight(
1579 AsmOperandInfo &info, const char *constraint) const {
1580 ConstraintWeight weight = CW_Invalid;
1581 Value *CallOperandVal = info.CallOperandVal;
1582 // If we don't have a value, we can't do a match,
1583 // but allow it at the lowest weight.
1584 if (CallOperandVal == NULL)
1586 const Type *type = CallOperandVal->getType();
1587 // Look at the constraint type.
1588 switch (*constraint) {
1590 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1594 if (type->isIntegerTy())
1595 weight = CW_Register;
1598 if (type->isFloatTy())
1599 weight = CW_Register;
1605 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1606 /// return a list of registers that can be used to satisfy the constraint.
1607 /// This should only be used for C_RegisterClass constraints.
1608 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1609 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1611 if (Constraint.size() == 1) {
1612 switch (Constraint[0]) {
1614 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1617 return std::make_pair(0U, Mips::FGR32RegisterClass);
1619 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1620 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1623 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1626 /// Given a register class constraint, like 'r', if this corresponds directly
1627 /// to an LLVM register class, return a register of 0 and the register class
1629 std::vector<unsigned> MipsTargetLowering::
1630 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1633 if (Constraint.size() != 1)
1634 return std::vector<unsigned>();
1636 switch (Constraint[0]) {
1639 // GCC Mips Constraint Letters
1642 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1643 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1644 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1648 if (VT == MVT::f32) {
1649 if (Subtarget->isSingleFloat())
1650 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1651 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1652 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1653 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1654 Mips::F30, Mips::F31, 0);
1656 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1657 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1658 Mips::F28, Mips::F30, 0);
1662 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1663 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1664 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1665 Mips::D14, Mips::D15, 0);
1667 return std::vector<unsigned>();
1671 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1672 // The Mips target isn't yet aware of offsets.
1676 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1677 if (VT != MVT::f32 && VT != MVT::f64)
1679 if (Imm.isNegZero())
1681 return Imm.isZero();