1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-lower"
15 #include "MipsISelLowering.h"
16 #include "InstPrinter/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/CodeGen/ValueTypes.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NumTailCalls, "Number of tail calls");
43 LargeGOT("mxgot", cl::Hidden,
44 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
47 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
48 cl::desc("MIPS: Don't trap on integer division by zero."),
51 static const uint16_t O32IntRegs[4] = {
52 Mips::A0, Mips::A1, Mips::A2, Mips::A3
55 static const uint16_t Mips64IntRegs[8] = {
56 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
57 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
60 static const uint16_t Mips64DPRegs[8] = {
61 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
62 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
65 // If I is a shifted mask, set the size (Size) and the first bit of the
66 // mask (Pos), and return true.
67 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
68 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
69 if (!isShiftedMask_64(I))
72 Size = CountPopulation_64(I);
73 Pos = countTrailingZeros(I);
77 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
78 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
79 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
82 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) {
83 EVT Ty = Op.getValueType();
85 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op))
86 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(Op), Ty, 0,
88 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op))
89 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
90 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op))
91 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
92 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op))
93 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
94 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op))
95 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
96 N->getOffset(), Flag);
98 llvm_unreachable("Unexpected node type.");
102 static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) {
104 EVT Ty = Op.getValueType();
105 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI);
106 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
107 return DAG.getNode(ISD::ADD, DL, Ty,
108 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
109 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
112 SDValue MipsTargetLowering::getAddrLocal(SDValue Op, SelectionDAG &DAG,
113 bool HasMips64) const {
115 EVT Ty = Op.getValueType();
116 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
117 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
118 getTargetNode(Op, DAG, GOTFlag));
119 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
120 MachinePointerInfo::getGOT(), false, false, false,
122 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
123 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
124 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
127 SDValue MipsTargetLowering::getAddrGlobal(SDValue Op, SelectionDAG &DAG,
128 unsigned Flag) const {
130 EVT Ty = Op.getValueType();
131 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
132 getTargetNode(Op, DAG, Flag));
133 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt,
134 MachinePointerInfo::getGOT(), false, false, false, 0);
137 SDValue MipsTargetLowering::getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
139 unsigned LoFlag) const {
141 EVT Ty = Op.getValueType();
142 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag));
143 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
144 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
145 getTargetNode(Op, DAG, LoFlag));
146 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper,
147 MachinePointerInfo::getGOT(), false, false, false, 0);
150 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
152 case MipsISD::JmpLink: return "MipsISD::JmpLink";
153 case MipsISD::TailCall: return "MipsISD::TailCall";
154 case MipsISD::Hi: return "MipsISD::Hi";
155 case MipsISD::Lo: return "MipsISD::Lo";
156 case MipsISD::GPRel: return "MipsISD::GPRel";
157 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
158 case MipsISD::Ret: return "MipsISD::Ret";
159 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
160 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
161 case MipsISD::FPCmp: return "MipsISD::FPCmp";
162 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
163 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
164 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
165 case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI";
166 case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI";
167 case MipsISD::Mult: return "MipsISD::Mult";
168 case MipsISD::Multu: return "MipsISD::Multu";
169 case MipsISD::MAdd: return "MipsISD::MAdd";
170 case MipsISD::MAddu: return "MipsISD::MAddu";
171 case MipsISD::MSub: return "MipsISD::MSub";
172 case MipsISD::MSubu: return "MipsISD::MSubu";
173 case MipsISD::DivRem: return "MipsISD::DivRem";
174 case MipsISD::DivRemU: return "MipsISD::DivRemU";
175 case MipsISD::DivRem16: return "MipsISD::DivRem16";
176 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
177 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
178 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
179 case MipsISD::Wrapper: return "MipsISD::Wrapper";
180 case MipsISD::Sync: return "MipsISD::Sync";
181 case MipsISD::Ext: return "MipsISD::Ext";
182 case MipsISD::Ins: return "MipsISD::Ins";
183 case MipsISD::LWL: return "MipsISD::LWL";
184 case MipsISD::LWR: return "MipsISD::LWR";
185 case MipsISD::SWL: return "MipsISD::SWL";
186 case MipsISD::SWR: return "MipsISD::SWR";
187 case MipsISD::LDL: return "MipsISD::LDL";
188 case MipsISD::LDR: return "MipsISD::LDR";
189 case MipsISD::SDL: return "MipsISD::SDL";
190 case MipsISD::SDR: return "MipsISD::SDR";
191 case MipsISD::EXTP: return "MipsISD::EXTP";
192 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
193 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
194 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
195 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
196 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
197 case MipsISD::SHILO: return "MipsISD::SHILO";
198 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
199 case MipsISD::MULT: return "MipsISD::MULT";
200 case MipsISD::MULTU: return "MipsISD::MULTU";
201 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
202 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
203 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
204 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
205 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
206 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
207 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
208 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
209 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
210 default: return NULL;
215 MipsTargetLowering(MipsTargetMachine &TM)
216 : TargetLowering(TM, new MipsTargetObjectFile()),
217 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
218 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
219 IsO32(Subtarget->isABI_O32()) {
220 // Mips does not have i1 type, so use i32 for
221 // setcc operations results (slt, sgt, ...).
222 setBooleanContents(ZeroOrOneBooleanContent);
223 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
225 // Load extented operations for i1 types must be promoted
226 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
228 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
230 // MIPS doesn't have extending float->double load/store
231 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
232 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
234 // Used by legalize types to correctly generate the setcc result.
235 // Without this, every float setcc comes with a AND/OR with the result,
236 // we don't want this, since the fpcmp result goes to a flag register,
237 // which is used implicitly by brcond and select operations.
238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
240 // Mips Custom Operations
241 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
245 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
247 setOperationAction(ISD::SELECT, MVT::f32, Custom);
248 setOperationAction(ISD::SELECT, MVT::f64, Custom);
249 setOperationAction(ISD::SELECT, MVT::i32, Custom);
250 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
251 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
252 setOperationAction(ISD::SETCC, MVT::f32, Custom);
253 setOperationAction(ISD::SETCC, MVT::f64, Custom);
254 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
255 setOperationAction(ISD::VASTART, MVT::Other, Custom);
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
258 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
260 if (!TM.Options.NoNaNsFPMath) {
261 setOperationAction(ISD::FABS, MVT::f32, Custom);
262 setOperationAction(ISD::FABS, MVT::f64, Custom);
266 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
267 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
268 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
269 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
270 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
271 setOperationAction(ISD::SELECT, MVT::i64, Custom);
272 setOperationAction(ISD::LOAD, MVT::i64, Custom);
273 setOperationAction(ISD::STORE, MVT::i64, Custom);
274 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
278 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
279 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
280 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
283 setOperationAction(ISD::ADD, MVT::i32, Custom);
285 setOperationAction(ISD::ADD, MVT::i64, Custom);
287 setOperationAction(ISD::SDIV, MVT::i32, Expand);
288 setOperationAction(ISD::SREM, MVT::i32, Expand);
289 setOperationAction(ISD::UDIV, MVT::i32, Expand);
290 setOperationAction(ISD::UREM, MVT::i32, Expand);
291 setOperationAction(ISD::SDIV, MVT::i64, Expand);
292 setOperationAction(ISD::SREM, MVT::i64, Expand);
293 setOperationAction(ISD::UDIV, MVT::i64, Expand);
294 setOperationAction(ISD::UREM, MVT::i64, Expand);
296 // Operations not directly supported by Mips.
297 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
298 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
299 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
300 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
301 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
302 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
303 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
304 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
305 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
307 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
308 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
309 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
310 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
311 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
312 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
313 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
314 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
315 setOperationAction(ISD::ROTL, MVT::i32, Expand);
316 setOperationAction(ISD::ROTL, MVT::i64, Expand);
317 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
318 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
320 if (!Subtarget->hasMips32r2())
321 setOperationAction(ISD::ROTR, MVT::i32, Expand);
323 if (!Subtarget->hasMips64r2())
324 setOperationAction(ISD::ROTR, MVT::i64, Expand);
326 setOperationAction(ISD::FSIN, MVT::f32, Expand);
327 setOperationAction(ISD::FSIN, MVT::f64, Expand);
328 setOperationAction(ISD::FCOS, MVT::f32, Expand);
329 setOperationAction(ISD::FCOS, MVT::f64, Expand);
330 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
331 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
332 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
333 setOperationAction(ISD::FPOW, MVT::f32, Expand);
334 setOperationAction(ISD::FPOW, MVT::f64, Expand);
335 setOperationAction(ISD::FLOG, MVT::f32, Expand);
336 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
337 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
338 setOperationAction(ISD::FEXP, MVT::f32, Expand);
339 setOperationAction(ISD::FMA, MVT::f32, Expand);
340 setOperationAction(ISD::FMA, MVT::f64, Expand);
341 setOperationAction(ISD::FREM, MVT::f32, Expand);
342 setOperationAction(ISD::FREM, MVT::f64, Expand);
344 if (!TM.Options.NoNaNsFPMath) {
345 setOperationAction(ISD::FNEG, MVT::f32, Expand);
346 setOperationAction(ISD::FNEG, MVT::f64, Expand);
349 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
351 setOperationAction(ISD::VAARG, MVT::Other, Expand);
352 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
353 setOperationAction(ISD::VAEND, MVT::Other, Expand);
355 // Use the default for now
356 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
357 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
359 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
360 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
361 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
362 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
364 setInsertFencesForAtomic(true);
366 if (!Subtarget->hasSEInReg()) {
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
371 if (!Subtarget->hasBitCount()) {
372 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
373 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
376 if (!Subtarget->hasSwap()) {
377 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
378 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
382 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
383 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
384 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
385 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
388 setTargetDAGCombine(ISD::SDIVREM);
389 setTargetDAGCombine(ISD::UDIVREM);
390 setTargetDAGCombine(ISD::SELECT);
391 setTargetDAGCombine(ISD::AND);
392 setTargetDAGCombine(ISD::OR);
393 setTargetDAGCombine(ISD::ADD);
395 setMinFunctionAlignment(HasMips64 ? 3 : 2);
397 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
399 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
400 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
402 MaxStoresPerMemcpy = 16;
405 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
406 if (TM.getSubtargetImpl()->inMips16Mode())
407 return llvm::createMips16TargetLowering(TM);
409 return llvm::createMipsSETargetLowering(TM);
412 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
415 return VT.changeVectorElementTypeToInteger();
418 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
419 TargetLowering::DAGCombinerInfo &DCI,
420 const MipsSubtarget *Subtarget) {
421 if (DCI.isBeforeLegalizeOps())
424 EVT Ty = N->getValueType(0);
425 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
426 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
427 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
431 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
432 N->getOperand(0), N->getOperand(1));
433 SDValue InChain = DAG.getEntryNode();
434 SDValue InGlue = DivRem;
437 if (N->hasAnyUseOfValue(0)) {
438 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
440 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
441 InChain = CopyFromLo.getValue(1);
442 InGlue = CopyFromLo.getValue(2);
446 if (N->hasAnyUseOfValue(1)) {
447 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
449 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
455 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
457 default: llvm_unreachable("Unknown fp condition code!");
459 case ISD::SETOEQ: return Mips::FCOND_OEQ;
460 case ISD::SETUNE: return Mips::FCOND_UNE;
462 case ISD::SETOLT: return Mips::FCOND_OLT;
464 case ISD::SETOGT: return Mips::FCOND_OGT;
466 case ISD::SETOLE: return Mips::FCOND_OLE;
468 case ISD::SETOGE: return Mips::FCOND_OGE;
469 case ISD::SETULT: return Mips::FCOND_ULT;
470 case ISD::SETULE: return Mips::FCOND_ULE;
471 case ISD::SETUGT: return Mips::FCOND_UGT;
472 case ISD::SETUGE: return Mips::FCOND_UGE;
473 case ISD::SETUO: return Mips::FCOND_UN;
474 case ISD::SETO: return Mips::FCOND_OR;
476 case ISD::SETONE: return Mips::FCOND_ONE;
477 case ISD::SETUEQ: return Mips::FCOND_UEQ;
482 /// This function returns true if the floating point conditional branches and
483 /// conditional moves which use condition code CC should be inverted.
484 static bool invertFPCondCodeUser(Mips::CondCode CC) {
485 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
488 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
489 "Illegal Condition Code");
494 // Creates and returns an FPCmp node from a setcc node.
495 // Returns Op if setcc is not a floating point comparison.
496 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
497 // must be a SETCC node
498 if (Op.getOpcode() != ISD::SETCC)
501 SDValue LHS = Op.getOperand(0);
503 if (!LHS.getValueType().isFloatingPoint())
506 SDValue RHS = Op.getOperand(1);
509 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
510 // node if necessary.
511 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
513 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
514 DAG.getConstant(condCodeToFCC(CC), MVT::i32));
517 // Creates and returns a CMovFPT/F node.
518 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
519 SDValue False, SDLoc DL) {
520 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
521 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
523 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
524 True.getValueType(), True, False, Cond);
527 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
528 TargetLowering::DAGCombinerInfo &DCI,
529 const MipsSubtarget *Subtarget) {
530 if (DCI.isBeforeLegalizeOps())
533 SDValue SetCC = N->getOperand(0);
535 if ((SetCC.getOpcode() != ISD::SETCC) ||
536 !SetCC.getOperand(0).getValueType().isInteger())
539 SDValue False = N->getOperand(2);
540 EVT FalseTy = False.getValueType();
542 if (!FalseTy.isInteger())
545 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
547 if (!CN || CN->getZExtValue())
551 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
552 SDValue True = N->getOperand(1);
554 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
555 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
557 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
560 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
561 TargetLowering::DAGCombinerInfo &DCI,
562 const MipsSubtarget *Subtarget) {
563 // Pattern match EXT.
564 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
565 // => ext $dst, $src, size, pos
566 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
569 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
570 unsigned ShiftRightOpc = ShiftRight.getOpcode();
572 // Op's first operand must be a shift right.
573 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
576 // The second operand of the shift must be an immediate.
578 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
581 uint64_t Pos = CN->getZExtValue();
582 uint64_t SMPos, SMSize;
584 // Op's second operand must be a shifted mask.
585 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
586 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
589 // Return if the shifted mask does not start at bit 0 or the sum of its size
590 // and Pos exceeds the word's size.
591 EVT ValTy = N->getValueType(0);
592 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
595 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy,
596 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
597 DAG.getConstant(SMSize, MVT::i32));
600 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
601 TargetLowering::DAGCombinerInfo &DCI,
602 const MipsSubtarget *Subtarget) {
603 // Pattern match INS.
604 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
605 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
606 // => ins $dst, $src, size, pos, $src1
607 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
610 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
611 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
614 // See if Op's first operand matches (and $src1 , mask0).
615 if (And0.getOpcode() != ISD::AND)
618 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
619 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
622 // See if Op's second operand matches (and (shl $src, pos), mask1).
623 if (And1.getOpcode() != ISD::AND)
626 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
627 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
630 // The shift masks must have the same position and size.
631 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
634 SDValue Shl = And1.getOperand(0);
635 if (Shl.getOpcode() != ISD::SHL)
638 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
641 unsigned Shamt = CN->getZExtValue();
643 // Return if the shift amount and the first bit position of mask are not the
645 EVT ValTy = N->getValueType(0);
646 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
649 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0),
650 DAG.getConstant(SMPos0, MVT::i32),
651 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
654 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
655 TargetLowering::DAGCombinerInfo &DCI,
656 const MipsSubtarget *Subtarget) {
657 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
659 if (DCI.isBeforeLegalizeOps())
662 SDValue Add = N->getOperand(1);
664 if (Add.getOpcode() != ISD::ADD)
667 SDValue Lo = Add.getOperand(1);
669 if ((Lo.getOpcode() != MipsISD::Lo) ||
670 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
673 EVT ValTy = N->getValueType(0);
676 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
678 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
681 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
683 SelectionDAG &DAG = DCI.DAG;
684 unsigned Opc = N->getOpcode();
690 return performDivRemCombine(N, DAG, DCI, Subtarget);
692 return performSELECTCombine(N, DAG, DCI, Subtarget);
694 return performANDCombine(N, DAG, DCI, Subtarget);
696 return performORCombine(N, DAG, DCI, Subtarget);
698 return performADDCombine(N, DAG, DCI, Subtarget);
705 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
706 SmallVectorImpl<SDValue> &Results,
707 SelectionDAG &DAG) const {
708 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
710 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
711 Results.push_back(Res.getValue(I));
715 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
716 SmallVectorImpl<SDValue> &Results,
717 SelectionDAG &DAG) const {
718 return LowerOperationWrapper(N, Results, DAG);
721 SDValue MipsTargetLowering::
722 LowerOperation(SDValue Op, SelectionDAG &DAG) const
724 switch (Op.getOpcode())
726 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
727 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
728 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
729 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
730 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
731 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
732 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
733 case ISD::SELECT: return lowerSELECT(Op, DAG);
734 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
735 case ISD::SETCC: return lowerSETCC(Op, DAG);
736 case ISD::VASTART: return lowerVASTART(Op, DAG);
737 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
738 case ISD::FABS: return lowerFABS(Op, DAG);
739 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
740 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
741 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
742 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
743 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
744 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
745 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
746 case ISD::LOAD: return lowerLOAD(Op, DAG);
747 case ISD::STORE: return lowerSTORE(Op, DAG);
748 case ISD::ADD: return lowerADD(Op, DAG);
749 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
754 //===----------------------------------------------------------------------===//
755 // Lower helper functions
756 //===----------------------------------------------------------------------===//
758 // addLiveIn - This helper function adds the specified physical register to the
759 // MachineFunction as a live in value. It also creates a corresponding
760 // virtual register for it.
762 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
764 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
765 MF.getRegInfo().addLiveIn(PReg, VReg);
769 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI,
770 MachineBasicBlock &MBB,
771 const TargetInstrInfo &TII,
776 // Insert instruction "teq $divisor_reg, $zero, 7".
777 MachineBasicBlock::iterator I(MI);
778 MachineInstrBuilder MIB;
779 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
780 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7);
782 // Use the 32-bit sub-register if this is a 64-bit division.
784 MIB->getOperand(0).setSubReg(Mips::sub_32);
790 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
791 MachineBasicBlock *BB) const {
792 switch (MI->getOpcode()) {
794 llvm_unreachable("Unexpected instr type to insert");
795 case Mips::ATOMIC_LOAD_ADD_I8:
796 case Mips::ATOMIC_LOAD_ADD_I8_P8:
797 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
798 case Mips::ATOMIC_LOAD_ADD_I16:
799 case Mips::ATOMIC_LOAD_ADD_I16_P8:
800 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
801 case Mips::ATOMIC_LOAD_ADD_I32:
802 case Mips::ATOMIC_LOAD_ADD_I32_P8:
803 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
804 case Mips::ATOMIC_LOAD_ADD_I64:
805 case Mips::ATOMIC_LOAD_ADD_I64_P8:
806 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
808 case Mips::ATOMIC_LOAD_AND_I8:
809 case Mips::ATOMIC_LOAD_AND_I8_P8:
810 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
811 case Mips::ATOMIC_LOAD_AND_I16:
812 case Mips::ATOMIC_LOAD_AND_I16_P8:
813 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
814 case Mips::ATOMIC_LOAD_AND_I32:
815 case Mips::ATOMIC_LOAD_AND_I32_P8:
816 return emitAtomicBinary(MI, BB, 4, Mips::AND);
817 case Mips::ATOMIC_LOAD_AND_I64:
818 case Mips::ATOMIC_LOAD_AND_I64_P8:
819 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
821 case Mips::ATOMIC_LOAD_OR_I8:
822 case Mips::ATOMIC_LOAD_OR_I8_P8:
823 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
824 case Mips::ATOMIC_LOAD_OR_I16:
825 case Mips::ATOMIC_LOAD_OR_I16_P8:
826 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
827 case Mips::ATOMIC_LOAD_OR_I32:
828 case Mips::ATOMIC_LOAD_OR_I32_P8:
829 return emitAtomicBinary(MI, BB, 4, Mips::OR);
830 case Mips::ATOMIC_LOAD_OR_I64:
831 case Mips::ATOMIC_LOAD_OR_I64_P8:
832 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
834 case Mips::ATOMIC_LOAD_XOR_I8:
835 case Mips::ATOMIC_LOAD_XOR_I8_P8:
836 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
837 case Mips::ATOMIC_LOAD_XOR_I16:
838 case Mips::ATOMIC_LOAD_XOR_I16_P8:
839 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
840 case Mips::ATOMIC_LOAD_XOR_I32:
841 case Mips::ATOMIC_LOAD_XOR_I32_P8:
842 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
843 case Mips::ATOMIC_LOAD_XOR_I64:
844 case Mips::ATOMIC_LOAD_XOR_I64_P8:
845 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
847 case Mips::ATOMIC_LOAD_NAND_I8:
848 case Mips::ATOMIC_LOAD_NAND_I8_P8:
849 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
850 case Mips::ATOMIC_LOAD_NAND_I16:
851 case Mips::ATOMIC_LOAD_NAND_I16_P8:
852 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
853 case Mips::ATOMIC_LOAD_NAND_I32:
854 case Mips::ATOMIC_LOAD_NAND_I32_P8:
855 return emitAtomicBinary(MI, BB, 4, 0, true);
856 case Mips::ATOMIC_LOAD_NAND_I64:
857 case Mips::ATOMIC_LOAD_NAND_I64_P8:
858 return emitAtomicBinary(MI, BB, 8, 0, true);
860 case Mips::ATOMIC_LOAD_SUB_I8:
861 case Mips::ATOMIC_LOAD_SUB_I8_P8:
862 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
863 case Mips::ATOMIC_LOAD_SUB_I16:
864 case Mips::ATOMIC_LOAD_SUB_I16_P8:
865 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
866 case Mips::ATOMIC_LOAD_SUB_I32:
867 case Mips::ATOMIC_LOAD_SUB_I32_P8:
868 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
869 case Mips::ATOMIC_LOAD_SUB_I64:
870 case Mips::ATOMIC_LOAD_SUB_I64_P8:
871 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
873 case Mips::ATOMIC_SWAP_I8:
874 case Mips::ATOMIC_SWAP_I8_P8:
875 return emitAtomicBinaryPartword(MI, BB, 1, 0);
876 case Mips::ATOMIC_SWAP_I16:
877 case Mips::ATOMIC_SWAP_I16_P8:
878 return emitAtomicBinaryPartword(MI, BB, 2, 0);
879 case Mips::ATOMIC_SWAP_I32:
880 case Mips::ATOMIC_SWAP_I32_P8:
881 return emitAtomicBinary(MI, BB, 4, 0);
882 case Mips::ATOMIC_SWAP_I64:
883 case Mips::ATOMIC_SWAP_I64_P8:
884 return emitAtomicBinary(MI, BB, 8, 0);
886 case Mips::ATOMIC_CMP_SWAP_I8:
887 case Mips::ATOMIC_CMP_SWAP_I8_P8:
888 return emitAtomicCmpSwapPartword(MI, BB, 1);
889 case Mips::ATOMIC_CMP_SWAP_I16:
890 case Mips::ATOMIC_CMP_SWAP_I16_P8:
891 return emitAtomicCmpSwapPartword(MI, BB, 2);
892 case Mips::ATOMIC_CMP_SWAP_I32:
893 case Mips::ATOMIC_CMP_SWAP_I32_P8:
894 return emitAtomicCmpSwap(MI, BB, 4);
895 case Mips::ATOMIC_CMP_SWAP_I64:
896 case Mips::ATOMIC_CMP_SWAP_I64_P8:
897 return emitAtomicCmpSwap(MI, BB, 8);
898 case Mips::PseudoSDIV:
899 case Mips::PseudoUDIV:
900 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false);
901 case Mips::PseudoDSDIV:
902 case Mips::PseudoDUDIV:
903 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true);
907 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
908 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
910 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
911 unsigned Size, unsigned BinOpcode,
913 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
915 MachineFunction *MF = BB->getParent();
916 MachineRegisterInfo &RegInfo = MF->getRegInfo();
917 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
918 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
919 DebugLoc DL = MI->getDebugLoc();
920 unsigned LL, SC, AND, NOR, ZERO, BEQ;
923 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
924 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
931 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
932 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
935 ZERO = Mips::ZERO_64;
939 unsigned OldVal = MI->getOperand(0).getReg();
940 unsigned Ptr = MI->getOperand(1).getReg();
941 unsigned Incr = MI->getOperand(2).getReg();
943 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
944 unsigned AndRes = RegInfo.createVirtualRegister(RC);
945 unsigned Success = RegInfo.createVirtualRegister(RC);
947 // insert new blocks after the current block
948 const BasicBlock *LLVM_BB = BB->getBasicBlock();
949 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
950 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
951 MachineFunction::iterator It = BB;
953 MF->insert(It, loopMBB);
954 MF->insert(It, exitMBB);
956 // Transfer the remainder of BB and its successor edges to exitMBB.
957 exitMBB->splice(exitMBB->begin(), BB,
958 llvm::next(MachineBasicBlock::iterator(MI)),
960 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
964 // fallthrough --> loopMBB
965 BB->addSuccessor(loopMBB);
966 loopMBB->addSuccessor(loopMBB);
967 loopMBB->addSuccessor(exitMBB);
971 // <binop> storeval, oldval, incr
972 // sc success, storeval, 0(ptr)
973 // beq success, $0, loopMBB
975 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
977 // and andres, oldval, incr
978 // nor storeval, $0, andres
979 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
980 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
981 } else if (BinOpcode) {
982 // <binop> storeval, oldval, incr
983 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
987 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
988 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
990 MI->eraseFromParent(); // The instruction is gone now.
996 MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI,
997 MachineBasicBlock *BB,
998 unsigned Size, unsigned BinOpcode,
1000 assert((Size == 1 || Size == 2) &&
1001 "Unsupported size for EmitAtomicBinaryPartial.");
1003 MachineFunction *MF = BB->getParent();
1004 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1005 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1006 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1007 DebugLoc DL = MI->getDebugLoc();
1008 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1009 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1011 unsigned Dest = MI->getOperand(0).getReg();
1012 unsigned Ptr = MI->getOperand(1).getReg();
1013 unsigned Incr = MI->getOperand(2).getReg();
1015 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1016 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1017 unsigned Mask = RegInfo.createVirtualRegister(RC);
1018 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1019 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1020 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1021 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1022 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1023 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1024 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1025 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1026 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1027 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1028 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1029 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1030 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1031 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1032 unsigned Success = RegInfo.createVirtualRegister(RC);
1034 // insert new blocks after the current block
1035 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1036 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1037 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1038 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1039 MachineFunction::iterator It = BB;
1041 MF->insert(It, loopMBB);
1042 MF->insert(It, sinkMBB);
1043 MF->insert(It, exitMBB);
1045 // Transfer the remainder of BB and its successor edges to exitMBB.
1046 exitMBB->splice(exitMBB->begin(), BB,
1047 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1048 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1050 BB->addSuccessor(loopMBB);
1051 loopMBB->addSuccessor(loopMBB);
1052 loopMBB->addSuccessor(sinkMBB);
1053 sinkMBB->addSuccessor(exitMBB);
1056 // addiu masklsb2,$0,-4 # 0xfffffffc
1057 // and alignedaddr,ptr,masklsb2
1058 // andi ptrlsb2,ptr,3
1059 // sll shiftamt,ptrlsb2,3
1060 // ori maskupper,$0,255 # 0xff
1061 // sll mask,maskupper,shiftamt
1062 // nor mask2,$0,mask
1063 // sll incr2,incr,shiftamt
1065 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1066 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1067 .addReg(Mips::ZERO).addImm(-4);
1068 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1069 .addReg(Ptr).addReg(MaskLSB2);
1070 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1071 if (Subtarget->isLittle()) {
1072 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1074 unsigned Off = RegInfo.createVirtualRegister(RC);
1075 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1076 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1077 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1079 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1080 .addReg(Mips::ZERO).addImm(MaskImm);
1081 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1082 .addReg(MaskUpper).addReg(ShiftAmt);
1083 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1084 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1086 // atomic.load.binop
1088 // ll oldval,0(alignedaddr)
1089 // binop binopres,oldval,incr2
1090 // and newval,binopres,mask
1091 // and maskedoldval0,oldval,mask2
1092 // or storeval,maskedoldval0,newval
1093 // sc success,storeval,0(alignedaddr)
1094 // beq success,$0,loopMBB
1098 // ll oldval,0(alignedaddr)
1099 // and newval,incr2,mask
1100 // and maskedoldval0,oldval,mask2
1101 // or storeval,maskedoldval0,newval
1102 // sc success,storeval,0(alignedaddr)
1103 // beq success,$0,loopMBB
1106 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1108 // and andres, oldval, incr2
1109 // nor binopres, $0, andres
1110 // and newval, binopres, mask
1111 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1112 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1113 .addReg(Mips::ZERO).addReg(AndRes);
1114 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1115 } else if (BinOpcode) {
1116 // <binop> binopres, oldval, incr2
1117 // and newval, binopres, mask
1118 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1119 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1120 } else {// atomic.swap
1121 // and newval, incr2, mask
1122 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1125 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1126 .addReg(OldVal).addReg(Mask2);
1127 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1128 .addReg(MaskedOldVal0).addReg(NewVal);
1129 BuildMI(BB, DL, TII->get(SC), Success)
1130 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1131 BuildMI(BB, DL, TII->get(Mips::BEQ))
1132 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1135 // and maskedoldval1,oldval,mask
1136 // srl srlres,maskedoldval1,shiftamt
1137 // sll sllres,srlres,24
1138 // sra dest,sllres,24
1140 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1142 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1143 .addReg(OldVal).addReg(Mask);
1144 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1145 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1146 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1147 .addReg(SrlRes).addImm(ShiftImm);
1148 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1149 .addReg(SllRes).addImm(ShiftImm);
1151 MI->eraseFromParent(); // The instruction is gone now.
1157 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1158 MachineBasicBlock *BB,
1159 unsigned Size) const {
1160 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1162 MachineFunction *MF = BB->getParent();
1163 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1164 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1165 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1166 DebugLoc DL = MI->getDebugLoc();
1167 unsigned LL, SC, ZERO, BNE, BEQ;
1170 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1171 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1177 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1178 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1179 ZERO = Mips::ZERO_64;
1184 unsigned Dest = MI->getOperand(0).getReg();
1185 unsigned Ptr = MI->getOperand(1).getReg();
1186 unsigned OldVal = MI->getOperand(2).getReg();
1187 unsigned NewVal = MI->getOperand(3).getReg();
1189 unsigned Success = RegInfo.createVirtualRegister(RC);
1191 // insert new blocks after the current block
1192 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1193 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1194 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1195 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1196 MachineFunction::iterator It = BB;
1198 MF->insert(It, loop1MBB);
1199 MF->insert(It, loop2MBB);
1200 MF->insert(It, exitMBB);
1202 // Transfer the remainder of BB and its successor edges to exitMBB.
1203 exitMBB->splice(exitMBB->begin(), BB,
1204 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1205 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1209 // fallthrough --> loop1MBB
1210 BB->addSuccessor(loop1MBB);
1211 loop1MBB->addSuccessor(exitMBB);
1212 loop1MBB->addSuccessor(loop2MBB);
1213 loop2MBB->addSuccessor(loop1MBB);
1214 loop2MBB->addSuccessor(exitMBB);
1218 // bne dest, oldval, exitMBB
1220 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1221 BuildMI(BB, DL, TII->get(BNE))
1222 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1225 // sc success, newval, 0(ptr)
1226 // beq success, $0, loop1MBB
1228 BuildMI(BB, DL, TII->get(SC), Success)
1229 .addReg(NewVal).addReg(Ptr).addImm(0);
1230 BuildMI(BB, DL, TII->get(BEQ))
1231 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1233 MI->eraseFromParent(); // The instruction is gone now.
1239 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1240 MachineBasicBlock *BB,
1241 unsigned Size) const {
1242 assert((Size == 1 || Size == 2) &&
1243 "Unsupported size for EmitAtomicCmpSwapPartial.");
1245 MachineFunction *MF = BB->getParent();
1246 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1247 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1248 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1249 DebugLoc DL = MI->getDebugLoc();
1250 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1251 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1253 unsigned Dest = MI->getOperand(0).getReg();
1254 unsigned Ptr = MI->getOperand(1).getReg();
1255 unsigned CmpVal = MI->getOperand(2).getReg();
1256 unsigned NewVal = MI->getOperand(3).getReg();
1258 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1259 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1260 unsigned Mask = RegInfo.createVirtualRegister(RC);
1261 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1262 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1263 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1264 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1265 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1266 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1267 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1268 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1269 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1270 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1271 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1272 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1273 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1274 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1275 unsigned Success = RegInfo.createVirtualRegister(RC);
1277 // insert new blocks after the current block
1278 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1279 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1280 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1281 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1282 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1283 MachineFunction::iterator It = BB;
1285 MF->insert(It, loop1MBB);
1286 MF->insert(It, loop2MBB);
1287 MF->insert(It, sinkMBB);
1288 MF->insert(It, exitMBB);
1290 // Transfer the remainder of BB and its successor edges to exitMBB.
1291 exitMBB->splice(exitMBB->begin(), BB,
1292 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
1293 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1295 BB->addSuccessor(loop1MBB);
1296 loop1MBB->addSuccessor(sinkMBB);
1297 loop1MBB->addSuccessor(loop2MBB);
1298 loop2MBB->addSuccessor(loop1MBB);
1299 loop2MBB->addSuccessor(sinkMBB);
1300 sinkMBB->addSuccessor(exitMBB);
1302 // FIXME: computation of newval2 can be moved to loop2MBB.
1304 // addiu masklsb2,$0,-4 # 0xfffffffc
1305 // and alignedaddr,ptr,masklsb2
1306 // andi ptrlsb2,ptr,3
1307 // sll shiftamt,ptrlsb2,3
1308 // ori maskupper,$0,255 # 0xff
1309 // sll mask,maskupper,shiftamt
1310 // nor mask2,$0,mask
1311 // andi maskedcmpval,cmpval,255
1312 // sll shiftedcmpval,maskedcmpval,shiftamt
1313 // andi maskednewval,newval,255
1314 // sll shiftednewval,maskednewval,shiftamt
1315 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1316 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1317 .addReg(Mips::ZERO).addImm(-4);
1318 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1319 .addReg(Ptr).addReg(MaskLSB2);
1320 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1321 if (Subtarget->isLittle()) {
1322 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1324 unsigned Off = RegInfo.createVirtualRegister(RC);
1325 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1326 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1327 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1329 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1330 .addReg(Mips::ZERO).addImm(MaskImm);
1331 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1332 .addReg(MaskUpper).addReg(ShiftAmt);
1333 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1334 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1335 .addReg(CmpVal).addImm(MaskImm);
1336 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1337 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1338 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1339 .addReg(NewVal).addImm(MaskImm);
1340 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1341 .addReg(MaskedNewVal).addReg(ShiftAmt);
1344 // ll oldval,0(alginedaddr)
1345 // and maskedoldval0,oldval,mask
1346 // bne maskedoldval0,shiftedcmpval,sinkMBB
1348 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1349 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1350 .addReg(OldVal).addReg(Mask);
1351 BuildMI(BB, DL, TII->get(Mips::BNE))
1352 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1355 // and maskedoldval1,oldval,mask2
1356 // or storeval,maskedoldval1,shiftednewval
1357 // sc success,storeval,0(alignedaddr)
1358 // beq success,$0,loop1MBB
1360 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1361 .addReg(OldVal).addReg(Mask2);
1362 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1363 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1364 BuildMI(BB, DL, TII->get(SC), Success)
1365 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1366 BuildMI(BB, DL, TII->get(Mips::BEQ))
1367 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1370 // srl srlres,maskedoldval0,shiftamt
1371 // sll sllres,srlres,24
1372 // sra dest,sllres,24
1374 int64_t ShiftImm = (Size == 1) ? 24 : 16;
1376 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1377 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1378 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1379 .addReg(SrlRes).addImm(ShiftImm);
1380 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1381 .addReg(SllRes).addImm(ShiftImm);
1383 MI->eraseFromParent(); // The instruction is gone now.
1388 //===----------------------------------------------------------------------===//
1389 // Misc Lower Operation implementation
1390 //===----------------------------------------------------------------------===//
1391 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1392 SDValue Chain = Op.getOperand(0);
1393 SDValue Table = Op.getOperand(1);
1394 SDValue Index = Op.getOperand(2);
1396 EVT PTy = getPointerTy();
1397 unsigned EntrySize =
1398 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout());
1400 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1401 DAG.getConstant(EntrySize, PTy));
1402 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1404 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1405 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1406 MachinePointerInfo::getJumpTable(), MemVT, false, false,
1408 Chain = Addr.getValue(1);
1410 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
1411 // For PIC, the sequence is:
1412 // BRIND(load(Jumptable + index) + RelocBase)
1413 // RelocBase can be JumpTable, GOT or some sort of global base.
1414 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1415 getPICJumpTableRelocBase(Table, DAG));
1418 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1421 SDValue MipsTargetLowering::
1422 lowerBRCOND(SDValue Op, SelectionDAG &DAG) const
1424 // The first operand is the chain, the second is the condition, the third is
1425 // the block to branch to if the condition is true.
1426 SDValue Chain = Op.getOperand(0);
1427 SDValue Dest = Op.getOperand(2);
1430 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1432 // Return if flag is not set by a floating point comparison.
1433 if (CondRes.getOpcode() != MipsISD::FPCmp)
1436 SDValue CCNode = CondRes.getOperand(2);
1438 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1439 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1440 SDValue BrCode = DAG.getConstant(Opc, MVT::i32);
1441 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1445 SDValue MipsTargetLowering::
1446 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1448 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1450 // Return if flag is not set by a floating point comparison.
1451 if (Cond.getOpcode() != MipsISD::FPCmp)
1454 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1458 SDValue MipsTargetLowering::
1459 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1462 EVT Ty = Op.getOperand(0).getValueType();
1463 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1464 getSetCCResultType(*DAG.getContext(), Ty),
1465 Op.getOperand(0), Op.getOperand(1),
1468 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1472 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1473 SDValue Cond = createFPCmp(DAG, Op);
1475 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1476 "Floating point operand expected.");
1478 SDValue True = DAG.getConstant(1, MVT::i32);
1479 SDValue False = DAG.getConstant(0, MVT::i32);
1481 return createCMovFP(DAG, Cond, True, False, SDLoc(Op));
1484 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1485 SelectionDAG &DAG) const {
1486 // FIXME there isn't actually debug info here
1488 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1490 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
1491 const MipsTargetObjectFile &TLOF =
1492 (const MipsTargetObjectFile&)getObjFileLowering();
1494 // %gp_rel relocation
1495 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1496 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
1498 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL,
1499 DAG.getVTList(MVT::i32), &GA, 1);
1500 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1501 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
1504 // %hi/%lo relocation
1505 return getAddrNonPIC(Op, DAG);
1508 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1509 return getAddrLocal(Op, DAG, HasMips64);
1512 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16,
1513 MipsII::MO_GOT_LO16);
1515 return getAddrGlobal(Op, DAG,
1516 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16);
1519 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1520 SelectionDAG &DAG) const {
1521 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1522 return getAddrNonPIC(Op, DAG);
1524 return getAddrLocal(Op, DAG, HasMips64);
1527 SDValue MipsTargetLowering::
1528 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1530 // If the relocation model is PIC, use the General Dynamic TLS Model or
1531 // Local Dynamic TLS model, otherwise use the Initial Exec or
1532 // Local Exec TLS Model.
1534 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1536 const GlobalValue *GV = GA->getGlobal();
1537 EVT PtrVT = getPointerTy();
1539 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1541 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1542 // General Dynamic and Local Dynamic TLS Model.
1543 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1546 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1547 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1548 getGlobalReg(DAG, PtrVT), TGA);
1549 unsigned PtrSize = PtrVT.getSizeInBits();
1550 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1552 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1556 Entry.Node = Argument;
1558 Args.push_back(Entry);
1560 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
1561 false, false, false, false, 0, CallingConv::C,
1562 /*IsTailCall=*/false, /*doesNotRet=*/false,
1563 /*isReturnValueUsed=*/true,
1564 TlsGetAddr, Args, DAG, DL);
1565 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1567 SDValue Ret = CallResult.first;
1569 if (model != TLSModel::LocalDynamic)
1572 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1573 MipsII::MO_DTPREL_HI);
1574 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1575 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1576 MipsII::MO_DTPREL_LO);
1577 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1578 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1579 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1583 if (model == TLSModel::InitialExec) {
1584 // Initial Exec TLS Model
1585 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1586 MipsII::MO_GOTTPREL);
1587 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1589 Offset = DAG.getLoad(PtrVT, DL,
1590 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1591 false, false, false, 0);
1593 // Local Exec TLS Model
1594 assert(model == TLSModel::LocalExec);
1595 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1596 MipsII::MO_TPREL_HI);
1597 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1598 MipsII::MO_TPREL_LO);
1599 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1600 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1601 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1604 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1605 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1608 SDValue MipsTargetLowering::
1609 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1611 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1612 return getAddrNonPIC(Op, DAG);
1614 return getAddrLocal(Op, DAG, HasMips64);
1617 SDValue MipsTargetLowering::
1618 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1620 // gp_rel relocation
1621 // FIXME: we should reference the constant pool using small data sections,
1622 // but the asm printer currently doesn't support this feature without
1623 // hacking it. This feature should come soon so we can uncomment the
1625 //if (IsInSmallSection(C->getType())) {
1626 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1627 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
1628 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1630 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64)
1631 return getAddrNonPIC(Op, DAG);
1633 return getAddrLocal(Op, DAG, HasMips64);
1636 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1637 MachineFunction &MF = DAG.getMachineFunction();
1638 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1641 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1644 // vastart just stores the address of the VarArgsFrameIndex slot into the
1645 // memory location argument.
1646 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1647 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1648 MachinePointerInfo(SV), false, false, 0);
1651 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1652 EVT TyX = Op.getOperand(0).getValueType();
1653 EVT TyY = Op.getOperand(1).getValueType();
1654 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1655 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1659 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1661 SDValue X = (TyX == MVT::f32) ?
1662 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1663 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1665 SDValue Y = (TyY == MVT::f32) ?
1666 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1667 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1671 // ext E, Y, 31, 1 ; extract bit31 of Y
1672 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1673 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1674 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1677 // srl SrlX, SllX, 1
1679 // sll SllY, SrlX, 31
1680 // or Or, SrlX, SllY
1681 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1682 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1683 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1684 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1685 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1688 if (TyX == MVT::f32)
1689 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1691 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1692 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1693 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1696 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1697 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1698 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1699 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1700 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1703 // Bitcast to integer nodes.
1704 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1705 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1708 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1709 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1710 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1711 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
1713 if (WidthX > WidthY)
1714 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1715 else if (WidthY > WidthX)
1716 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1718 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1719 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1720 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1723 // (d)sll SllX, X, 1
1724 // (d)srl SrlX, SllX, 1
1725 // (d)srl SrlY, Y, width(Y)-1
1726 // (d)sll SllY, SrlX, width(Y)-1
1727 // or Or, SrlX, SllY
1728 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1729 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1730 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1731 DAG.getConstant(WidthY - 1, MVT::i32));
1733 if (WidthX > WidthY)
1734 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1735 else if (WidthY > WidthX)
1736 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1738 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1739 DAG.getConstant(WidthX - 1, MVT::i32));
1740 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1741 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1745 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
1746 if (Subtarget->hasMips64())
1747 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
1749 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
1752 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1753 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1756 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1758 SDValue X = (Op.getValueType() == MVT::f32) ?
1759 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1760 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1765 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1766 DAG.getRegister(Mips::ZERO, MVT::i32),
1767 DAG.getConstant(31, MVT::i32), Const1, X);
1769 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1770 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1773 if (Op.getValueType() == MVT::f32)
1774 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1776 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1777 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1778 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1781 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1782 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1785 // Bitcast to integer node.
1786 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1790 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1791 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1792 DAG.getConstant(63, MVT::i32), Const1, X);
1794 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1795 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1798 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1802 MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
1803 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1804 return lowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1806 return lowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1809 SDValue MipsTargetLowering::
1810 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1812 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1813 "Frame address can only be determined for current frame.");
1815 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1816 MFI->setFrameAddressIsTaken(true);
1817 EVT VT = Op.getValueType();
1819 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL,
1820 IsN64 ? Mips::FP_64 : Mips::FP, VT);
1824 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
1825 SelectionDAG &DAG) const {
1827 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
1828 "Return address can be determined only for current frame.");
1830 MachineFunction &MF = DAG.getMachineFunction();
1831 MachineFrameInfo *MFI = MF.getFrameInfo();
1832 MVT VT = Op.getSimpleValueType();
1833 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
1834 MFI->setReturnAddressIsTaken(true);
1836 // Return RA, which contains the return address. Mark it an implicit live-in.
1837 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
1838 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
1841 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
1842 // generated from __builtin_eh_return (offset, handler)
1843 // The effect of this is to adjust the stack pointer by "offset"
1844 // and then branch to "handler".
1845 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
1847 MachineFunction &MF = DAG.getMachineFunction();
1848 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1850 MipsFI->setCallsEhReturn();
1851 SDValue Chain = Op.getOperand(0);
1852 SDValue Offset = Op.getOperand(1);
1853 SDValue Handler = Op.getOperand(2);
1855 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
1857 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
1858 // EH_RETURN nodes, so that instructions are emitted back-to-back.
1859 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
1860 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
1861 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
1862 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
1863 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
1864 DAG.getRegister(OffsetReg, Ty),
1865 DAG.getRegister(AddrReg, getPointerTy()),
1869 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
1870 SelectionDAG &DAG) const {
1871 // FIXME: Need pseudo-fence for 'singlethread' fences
1872 // FIXME: Set SType for weaker fences where supported/appropriate.
1875 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
1876 DAG.getConstant(SType, MVT::i32));
1879 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
1880 SelectionDAG &DAG) const {
1882 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1883 SDValue Shamt = Op.getOperand(2);
1886 // lo = (shl lo, shamt)
1887 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
1890 // hi = (shl lo, shamt[4:0])
1891 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1892 DAG.getConstant(-1, MVT::i32));
1893 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1894 DAG.getConstant(1, MVT::i32));
1895 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1897 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1898 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1899 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1900 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1901 DAG.getConstant(0x20, MVT::i32));
1902 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1903 DAG.getConstant(0, MVT::i32), ShiftLeftLo);
1904 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
1906 SDValue Ops[2] = {Lo, Hi};
1907 return DAG.getMergeValues(Ops, 2, DL);
1910 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
1913 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1914 SDValue Shamt = Op.getOperand(2);
1917 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
1919 // hi = (sra hi, shamt)
1921 // hi = (srl hi, shamt)
1924 // lo = (sra hi, shamt[4:0])
1925 // hi = (sra hi, 31)
1927 // lo = (srl hi, shamt[4:0])
1929 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1930 DAG.getConstant(-1, MVT::i32));
1931 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
1932 DAG.getConstant(1, MVT::i32));
1933 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
1934 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
1935 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1936 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1938 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1939 DAG.getConstant(0x20, MVT::i32));
1940 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
1941 DAG.getConstant(31, MVT::i32));
1942 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
1943 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1944 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
1947 SDValue Ops[2] = {Lo, Hi};
1948 return DAG.getMergeValues(Ops, 2, DL);
1951 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
1952 SDValue Chain, SDValue Src, unsigned Offset) {
1953 SDValue Ptr = LD->getBasePtr();
1954 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
1955 EVT BasePtrVT = Ptr.getValueType();
1957 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1960 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
1961 DAG.getConstant(Offset, BasePtrVT));
1963 SDValue Ops[] = { Chain, Ptr, Src };
1964 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
1965 LD->getMemOperand());
1968 // Expand an unaligned 32 or 64-bit integer load node.
1969 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1970 LoadSDNode *LD = cast<LoadSDNode>(Op);
1971 EVT MemVT = LD->getMemoryVT();
1973 // Return if load is aligned or if MemVT is neither i32 nor i64.
1974 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
1975 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
1978 bool IsLittle = Subtarget->isLittle();
1979 EVT VT = Op.getValueType();
1980 ISD::LoadExtType ExtType = LD->getExtensionType();
1981 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
1983 assert((VT == MVT::i32) || (VT == MVT::i64));
1986 // (set dst, (i64 (load baseptr)))
1988 // (set tmp, (ldl (add baseptr, 7), undef))
1989 // (set dst, (ldr baseptr, tmp))
1990 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
1991 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
1993 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
1997 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
1999 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2003 // (set dst, (i32 (load baseptr))) or
2004 // (set dst, (i64 (sextload baseptr))) or
2005 // (set dst, (i64 (extload baseptr)))
2007 // (set tmp, (lwl (add baseptr, 3), undef))
2008 // (set dst, (lwr baseptr, tmp))
2009 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2010 (ExtType == ISD::EXTLOAD))
2013 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2016 // (set dst, (i64 (zextload baseptr)))
2018 // (set tmp0, (lwl (add baseptr, 3), undef))
2019 // (set tmp1, (lwr baseptr, tmp0))
2020 // (set tmp2, (shl tmp1, 32))
2021 // (set dst, (srl tmp2, 32))
2023 SDValue Const32 = DAG.getConstant(32, MVT::i32);
2024 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2025 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2026 SDValue Ops[] = { SRL, LWR.getValue(1) };
2027 return DAG.getMergeValues(Ops, 2, DL);
2030 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2031 SDValue Chain, unsigned Offset) {
2032 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2033 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2035 SDVTList VTList = DAG.getVTList(MVT::Other);
2038 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2039 DAG.getConstant(Offset, BasePtrVT));
2041 SDValue Ops[] = { Chain, Value, Ptr };
2042 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT,
2043 SD->getMemOperand());
2046 // Expand an unaligned 32 or 64-bit integer store node.
2047 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2049 SDValue Value = SD->getValue(), Chain = SD->getChain();
2050 EVT VT = Value.getValueType();
2053 // (store val, baseptr) or
2054 // (truncstore val, baseptr)
2056 // (swl val, (add baseptr, 3))
2057 // (swr val, baseptr)
2058 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2059 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2061 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2064 assert(VT == MVT::i64);
2067 // (store val, baseptr)
2069 // (sdl val, (add baseptr, 7))
2070 // (sdr val, baseptr)
2071 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2072 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2075 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2076 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2077 SDValue Val = SD->getValue();
2079 if (Val.getOpcode() != ISD::FP_TO_SINT)
2082 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2083 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2086 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2087 SD->getPointerInfo(), SD->isVolatile(),
2088 SD->isNonTemporal(), SD->getAlignment());
2091 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2092 StoreSDNode *SD = cast<StoreSDNode>(Op);
2093 EVT MemVT = SD->getMemoryVT();
2095 // Lower unaligned integer stores.
2096 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2097 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2098 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle());
2100 return lowerFP_TO_SINT_STORE(SD, DAG);
2103 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2104 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2105 || cast<ConstantSDNode>
2106 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2107 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2111 // (add (frameaddr 0), (frame_to_args_offset))
2112 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2113 // (add FrameObject, 0)
2114 // where FrameObject is a fixed StackObject with offset 0 which points to
2115 // the old stack pointer.
2116 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2117 EVT ValTy = Op->getValueType(0);
2118 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2119 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2120 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2121 DAG.getConstant(0, ValTy));
2124 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2125 SelectionDAG &DAG) const {
2126 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2127 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2129 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2132 //===----------------------------------------------------------------------===//
2133 // Calling Convention Implementation
2134 //===----------------------------------------------------------------------===//
2136 //===----------------------------------------------------------------------===//
2137 // TODO: Implement a generic logic using tblgen that can support this.
2138 // Mips O32 ABI rules:
2140 // i32 - Passed in A0, A1, A2, A3 and stack
2141 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2142 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2143 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2144 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2145 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
2148 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2149 //===----------------------------------------------------------------------===//
2151 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
2152 MVT LocVT, CCValAssign::LocInfo LocInfo,
2153 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2155 static const unsigned IntRegsSize=4, FloatRegsSize=2;
2157 static const uint16_t IntRegs[] = {
2158 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2160 static const uint16_t F32Regs[] = {
2161 Mips::F12, Mips::F14
2163 static const uint16_t F64Regs[] = {
2167 // Do not process byval args here.
2168 if (ArgFlags.isByVal())
2171 // Promote i8 and i16
2172 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2174 if (ArgFlags.isSExt())
2175 LocInfo = CCValAssign::SExt;
2176 else if (ArgFlags.isZExt())
2177 LocInfo = CCValAssign::ZExt;
2179 LocInfo = CCValAssign::AExt;
2184 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2185 // is true: function is vararg, argument is 3rd or higher, there is previous
2186 // argument which is not f32 or f64.
2187 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2188 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
2189 unsigned OrigAlign = ArgFlags.getOrigAlign();
2190 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2192 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2193 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2194 // If this is the first part of an i64 arg,
2195 // the allocated register must be either A0 or A2.
2196 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2197 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2199 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2200 // Allocate int register and shadow next int register. If first
2201 // available register is Mips::A1 or Mips::A3, shadow it too.
2202 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2203 if (Reg == Mips::A1 || Reg == Mips::A3)
2204 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2205 State.AllocateReg(IntRegs, IntRegsSize);
2207 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2208 // we are guaranteed to find an available float register
2209 if (ValVT == MVT::f32) {
2210 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2211 // Shadow int register
2212 State.AllocateReg(IntRegs, IntRegsSize);
2214 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2215 // Shadow int registers
2216 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2217 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2218 State.AllocateReg(IntRegs, IntRegsSize);
2219 State.AllocateReg(IntRegs, IntRegsSize);
2222 llvm_unreachable("Cannot handle this ValVT.");
2225 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2227 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2229 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2234 #include "MipsGenCallingConv.inc"
2236 //===----------------------------------------------------------------------===//
2237 // Call Calling Convention Implementation
2238 //===----------------------------------------------------------------------===//
2240 static const unsigned O32IntRegsSize = 4;
2242 // Return next O32 integer argument register.
2243 static unsigned getNextIntArgReg(unsigned Reg) {
2244 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2245 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2249 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2250 SDValue Chain, SDValue Arg, SDLoc DL,
2251 bool IsTailCall, SelectionDAG &DAG) const {
2253 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2254 DAG.getIntPtrConstant(Offset));
2255 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2259 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2260 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2261 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2262 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2263 /*isVolatile=*/ true, false, 0);
2266 void MipsTargetLowering::
2267 getOpndList(SmallVectorImpl<SDValue> &Ops,
2268 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2269 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2270 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
2271 // Insert node "GP copy globalreg" before call to function.
2273 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2274 // in PIC mode) allow symbols to be resolved via lazy binding.
2275 // The lazy binding stub requires GP to point to the GOT.
2276 if (IsPICCall && !InternalLinkage) {
2277 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2278 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2279 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2282 // Build a sequence of copy-to-reg nodes chained together with token
2283 // chain and flag operands which copy the outgoing args into registers.
2284 // The InFlag in necessary since all emitted instructions must be
2288 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2289 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2290 RegsToPass[i].second, InFlag);
2291 InFlag = Chain.getValue(1);
2294 // Add argument registers to the end of the list so that they are
2295 // known live into the call.
2296 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2297 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2298 RegsToPass[i].second.getValueType()));
2300 // Add a register mask operand representing the call-preserved registers.
2301 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2302 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
2303 assert(Mask && "Missing call preserved mask for calling convention");
2304 if (Subtarget->inMips16HardFloat()) {
2305 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2306 llvm::StringRef Sym = G->getGlobal()->getName();
2307 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2308 if (F->hasFnAttribute("__Mips16RetHelper")) {
2309 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2313 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2315 if (InFlag.getNode())
2316 Ops.push_back(InFlag);
2319 /// LowerCall - functions arguments are copied from virtual regs to
2320 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2322 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2323 SmallVectorImpl<SDValue> &InVals) const {
2324 SelectionDAG &DAG = CLI.DAG;
2326 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2327 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2328 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2329 SDValue Chain = CLI.Chain;
2330 SDValue Callee = CLI.Callee;
2331 bool &IsTailCall = CLI.IsTailCall;
2332 CallingConv::ID CallConv = CLI.CallConv;
2333 bool IsVarArg = CLI.IsVarArg;
2335 MachineFunction &MF = DAG.getMachineFunction();
2336 MachineFrameInfo *MFI = MF.getFrameInfo();
2337 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
2338 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2340 // Analyze operands of the call, assigning locations to each operand.
2341 SmallVector<CCValAssign, 16> ArgLocs;
2342 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2343 getTargetMachine(), ArgLocs, *DAG.getContext());
2344 MipsCC::SpecialCallingConvType SpecialCallingConv =
2345 getSpecialCallingConv(Callee);
2346 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo, SpecialCallingConv);
2348 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
2349 getTargetMachine().Options.UseSoftFloat,
2350 Callee.getNode(), CLI.Args);
2352 // Get a count of how many bytes are to be pushed on the stack.
2353 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2355 // Check if it's really possible to do a tail call.
2358 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
2359 *MF.getInfo<MipsFunctionInfo>());
2364 // Chain is the output chain of the last Load/Store or CopyToReg node.
2365 // ByValChain is the output chain of the last Memcpy node created for copying
2366 // byval arguments to the stack.
2367 unsigned StackAlignment = TFL->getStackAlignment();
2368 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2369 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2372 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2374 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL,
2375 IsN64 ? Mips::SP_64 : Mips::SP,
2378 // With EABI is it possible to have 16 args on registers.
2379 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2380 SmallVector<SDValue, 8> MemOpChains;
2381 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2383 // Walk the register/memloc assignments, inserting copies/loads.
2384 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2385 SDValue Arg = OutVals[i];
2386 CCValAssign &VA = ArgLocs[i];
2387 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2388 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2391 if (Flags.isByVal()) {
2392 assert(Flags.getByValSize() &&
2393 "ByVal args of size 0 should have been ignored by front-end.");
2394 assert(ByValArg != MipsCCInfo.byval_end());
2395 assert(!IsTailCall &&
2396 "Do not tail-call optimize if there is a byval argument.");
2397 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2398 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle());
2403 // Promote the value if needed.
2404 switch (VA.getLocInfo()) {
2405 default: llvm_unreachable("Unknown loc info!");
2406 case CCValAssign::Full:
2407 if (VA.isRegLoc()) {
2408 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2409 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2410 (ValVT == MVT::i64 && LocVT == MVT::f64))
2411 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2412 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2413 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2414 Arg, DAG.getConstant(0, MVT::i32));
2415 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2416 Arg, DAG.getConstant(1, MVT::i32));
2417 if (!Subtarget->isLittle())
2419 unsigned LocRegLo = VA.getLocReg();
2420 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2421 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2422 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2427 case CCValAssign::SExt:
2428 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2430 case CCValAssign::ZExt:
2431 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2433 case CCValAssign::AExt:
2434 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2438 // Arguments that can be passed on register must be kept at
2439 // RegsToPass vector
2440 if (VA.isRegLoc()) {
2441 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2445 // Register can't get to this point...
2446 assert(VA.isMemLoc());
2448 // emit ISD::STORE whichs stores the
2449 // parameter value to a stack Location
2450 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2451 Chain, Arg, DL, IsTailCall, DAG));
2454 // Transform all store nodes into one single node because all store
2455 // nodes are independent of each other.
2456 if (!MemOpChains.empty())
2457 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2458 &MemOpChains[0], MemOpChains.size());
2460 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2461 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2462 // node so that legalize doesn't hack it.
2463 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
2464 bool GlobalOrExternal = false, InternalLinkage = false;
2467 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2469 InternalLinkage = G->getGlobal()->hasInternalLinkage();
2471 if (InternalLinkage)
2472 Callee = getAddrLocal(Callee, DAG, HasMips64);
2474 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
2475 MipsII::MO_CALL_LO16);
2477 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
2479 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
2480 MipsII::MO_NO_FLAG);
2481 GlobalOrExternal = true;
2483 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2484 if (!IsN64 && !IsPIC) // !N64 && static
2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2486 MipsII::MO_NO_FLAG);
2488 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16,
2489 MipsII::MO_CALL_LO16);
2491 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL);
2493 GlobalOrExternal = true;
2496 SmallVector<SDValue, 8> Ops(1, Chain);
2497 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2499 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2500 CLI, Callee, Chain);
2503 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
2505 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
2506 SDValue InFlag = Chain.getValue(1);
2508 // Create the CALLSEQ_END node.
2509 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2510 DAG.getIntPtrConstant(0, true), InFlag, DL);
2511 InFlag = Chain.getValue(1);
2513 // Handle result values, copying them out of physregs into vregs that we
2515 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg,
2516 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy);
2519 /// LowerCallResult - Lower the result values of a call into the
2520 /// appropriate copies out of appropriate physical registers.
2522 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2523 CallingConv::ID CallConv, bool IsVarArg,
2524 const SmallVectorImpl<ISD::InputArg> &Ins,
2525 SDLoc DL, SelectionDAG &DAG,
2526 SmallVectorImpl<SDValue> &InVals,
2527 const SDNode *CallNode,
2528 const Type *RetTy) const {
2529 // Assign locations to each value returned by this call.
2530 SmallVector<CCValAssign, 16> RVLocs;
2531 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2532 getTargetMachine(), RVLocs, *DAG.getContext());
2533 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
2535 MipsCCInfo.analyzeCallResult(Ins, getTargetMachine().Options.UseSoftFloat,
2538 // Copy all of the result registers out of their specified physreg.
2539 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2540 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2541 RVLocs[i].getLocVT(), InFlag);
2542 Chain = Val.getValue(1);
2543 InFlag = Val.getValue(2);
2545 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2546 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
2548 InVals.push_back(Val);
2554 //===----------------------------------------------------------------------===//
2555 // Formal Arguments Calling Convention Implementation
2556 //===----------------------------------------------------------------------===//
2557 /// LowerFormalArguments - transform physical registers into virtual registers
2558 /// and generate load operations for arguments places on the stack.
2560 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2561 CallingConv::ID CallConv,
2563 const SmallVectorImpl<ISD::InputArg> &Ins,
2564 SDLoc DL, SelectionDAG &DAG,
2565 SmallVectorImpl<SDValue> &InVals)
2567 MachineFunction &MF = DAG.getMachineFunction();
2568 MachineFrameInfo *MFI = MF.getFrameInfo();
2569 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2571 MipsFI->setVarArgsFrameIndex(0);
2573 // Used with vargs to acumulate store chains.
2574 std::vector<SDValue> OutChains;
2576 // Assign locations to all of the incoming arguments.
2577 SmallVector<CCValAssign, 16> ArgLocs;
2578 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2579 getTargetMachine(), ArgLocs, *DAG.getContext());
2580 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
2581 Function::const_arg_iterator FuncArg =
2582 DAG.getMachineFunction().getFunction()->arg_begin();
2583 bool UseSoftFloat = getTargetMachine().Options.UseSoftFloat;
2585 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
2586 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2587 MipsCCInfo.hasByValArg());
2589 unsigned CurArgIdx = 0;
2590 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
2592 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2593 CCValAssign &VA = ArgLocs[i];
2594 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx);
2595 CurArgIdx = Ins[i].OrigArgIndex;
2596 EVT ValVT = VA.getValVT();
2597 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2598 bool IsRegLoc = VA.isRegLoc();
2600 if (Flags.isByVal()) {
2601 assert(Flags.getByValSize() &&
2602 "ByVal args of size 0 should have been ignored by front-end.");
2603 assert(ByValArg != MipsCCInfo.byval_end());
2604 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2605 MipsCCInfo, *ByValArg);
2610 // Arguments stored on registers
2612 EVT RegVT = VA.getLocVT();
2613 unsigned ArgReg = VA.getLocReg();
2614 const TargetRegisterClass *RC;
2616 if (RegVT == MVT::i32)
2617 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
2618 &Mips::CPURegsRegClass;
2619 else if (RegVT == MVT::i64)
2620 RC = &Mips::CPU64RegsRegClass;
2621 else if (RegVT == MVT::f32)
2622 RC = &Mips::FGR32RegClass;
2623 else if (RegVT == MVT::f64)
2624 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
2626 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
2628 // Transform the arguments stored on
2629 // physical registers into virtual ones
2630 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
2631 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2633 // If this is an 8 or 16-bit value, it has been passed promoted
2634 // to 32 bits. Insert an assert[sz]ext to capture this, then
2635 // truncate to the right size.
2636 if (VA.getLocInfo() != CCValAssign::Full) {
2637 unsigned Opcode = 0;
2638 if (VA.getLocInfo() == CCValAssign::SExt)
2639 Opcode = ISD::AssertSext;
2640 else if (VA.getLocInfo() == CCValAssign::ZExt)
2641 Opcode = ISD::AssertZext;
2643 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
2644 DAG.getValueType(ValVT));
2645 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
2648 // Handle floating point arguments passed in integer registers and
2649 // long double arguments passed in floating point registers.
2650 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2651 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
2652 (RegVT == MVT::f64 && ValVT == MVT::i64))
2653 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2654 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2655 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
2656 getNextIntArgReg(ArgReg), RC);
2657 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
2658 if (!Subtarget->isLittle())
2659 std::swap(ArgValue, ArgValue2);
2660 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
2661 ArgValue, ArgValue2);
2664 InVals.push_back(ArgValue);
2665 } else { // VA.isRegLoc()
2668 assert(VA.isMemLoc());
2670 // The stack pointer offset is relative to the caller stack frame.
2671 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2672 VA.getLocMemOffset(), true);
2674 // Create load nodes to retrieve arguments from the stack
2675 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2676 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN,
2677 MachinePointerInfo::getFixedStack(FI),
2678 false, false, false, 0));
2682 // The mips ABIs for returning structs by value requires that we copy
2683 // the sret argument into $v0 for the return. Save the argument into
2684 // a virtual register so that we can access it from the return points.
2685 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2686 unsigned Reg = MipsFI->getSRetReturnReg();
2688 Reg = MF.getRegInfo().
2689 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
2690 MipsFI->setSRetReturnReg(Reg);
2692 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]);
2693 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
2697 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG);
2699 // All stores are grouped in one node to allow the matching between
2700 // the size of Ins and InVals. This only happens when on varg functions
2701 if (!OutChains.empty()) {
2702 OutChains.push_back(Chain);
2703 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2704 &OutChains[0], OutChains.size());
2710 //===----------------------------------------------------------------------===//
2711 // Return Value Calling Convention Implementation
2712 //===----------------------------------------------------------------------===//
2715 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2716 MachineFunction &MF, bool IsVarArg,
2717 const SmallVectorImpl<ISD::OutputArg> &Outs,
2718 LLVMContext &Context) const {
2719 SmallVector<CCValAssign, 16> RVLocs;
2720 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(),
2722 return CCInfo.CheckReturn(Outs, RetCC_Mips);
2726 MipsTargetLowering::LowerReturn(SDValue Chain,
2727 CallingConv::ID CallConv, bool IsVarArg,
2728 const SmallVectorImpl<ISD::OutputArg> &Outs,
2729 const SmallVectorImpl<SDValue> &OutVals,
2730 SDLoc DL, SelectionDAG &DAG) const {
2731 // CCValAssign - represent the assignment of
2732 // the return value to a location
2733 SmallVector<CCValAssign, 16> RVLocs;
2734 MachineFunction &MF = DAG.getMachineFunction();
2736 // CCState - Info about the registers and stack slot.
2737 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
2739 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo);
2741 // Analyze return values.
2742 MipsCCInfo.analyzeReturn(Outs, getTargetMachine().Options.UseSoftFloat,
2743 MF.getFunction()->getReturnType());
2746 SmallVector<SDValue, 4> RetOps(1, Chain);
2748 // Copy the result values into the output registers.
2749 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2750 SDValue Val = OutVals[i];
2751 CCValAssign &VA = RVLocs[i];
2752 assert(VA.isRegLoc() && "Can only return in registers!");
2754 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT())
2755 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
2757 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
2759 // Guarantee that all emitted copies are stuck together with flags.
2760 Flag = Chain.getValue(1);
2761 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2764 // The mips ABIs for returning structs by value requires that we copy
2765 // the sret argument into $v0 for the return. We saved the argument into
2766 // a virtual register in the entry block, so now we copy the value out
2768 if (MF.getFunction()->hasStructRetAttr()) {
2769 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2770 unsigned Reg = MipsFI->getSRetReturnReg();
2773 llvm_unreachable("sret virtual register not created in the entry block");
2774 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
2775 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
2777 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
2778 Flag = Chain.getValue(1);
2779 RetOps.push_back(DAG.getRegister(V0, getPointerTy()));
2782 RetOps[0] = Chain; // Update chain.
2784 // Add the flag if we have it.
2786 RetOps.push_back(Flag);
2788 // Return on Mips is always a "jr $ra"
2789 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size());
2792 //===----------------------------------------------------------------------===//
2793 // Mips Inline Assembly Support
2794 //===----------------------------------------------------------------------===//
2796 /// getConstraintType - Given a constraint letter, return the type of
2797 /// constraint it is for this target.
2798 MipsTargetLowering::ConstraintType MipsTargetLowering::
2799 getConstraintType(const std::string &Constraint) const
2801 // Mips specific constrainy
2802 // GCC config/mips/constraints.md
2804 // 'd' : An address register. Equivalent to r
2805 // unless generating MIPS16 code.
2806 // 'y' : Equivalent to r; retained for
2807 // backwards compatibility.
2808 // 'c' : A register suitable for use in an indirect
2809 // jump. This will always be $25 for -mabicalls.
2810 // 'l' : The lo register. 1 word storage.
2811 // 'x' : The hilo register pair. Double word storage.
2812 if (Constraint.size() == 1) {
2813 switch (Constraint[0]) {
2821 return C_RegisterClass;
2826 return TargetLowering::getConstraintType(Constraint);
2829 /// Examine constraint type and operand type and determine a weight value.
2830 /// This object must already have been set up with the operand type
2831 /// and the current alternative constraint selected.
2832 TargetLowering::ConstraintWeight
2833 MipsTargetLowering::getSingleConstraintMatchWeight(
2834 AsmOperandInfo &info, const char *constraint) const {
2835 ConstraintWeight weight = CW_Invalid;
2836 Value *CallOperandVal = info.CallOperandVal;
2837 // If we don't have a value, we can't do a match,
2838 // but allow it at the lowest weight.
2839 if (CallOperandVal == NULL)
2841 Type *type = CallOperandVal->getType();
2842 // Look at the constraint type.
2843 switch (*constraint) {
2845 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2849 if (type->isIntegerTy())
2850 weight = CW_Register;
2853 if (type->isFloatTy())
2854 weight = CW_Register;
2856 case 'c': // $25 for indirect jumps
2857 case 'l': // lo register
2858 case 'x': // hilo register pair
2859 if (type->isIntegerTy())
2860 weight = CW_SpecificReg;
2862 case 'I': // signed 16 bit immediate
2863 case 'J': // integer zero
2864 case 'K': // unsigned 16 bit immediate
2865 case 'L': // signed 32 bit immediate where lower 16 bits are 0
2866 case 'N': // immediate in the range of -65535 to -1 (inclusive)
2867 case 'O': // signed 15 bit immediate (+- 16383)
2868 case 'P': // immediate in the range of 65535 to 1 (inclusive)
2869 if (isa<ConstantInt>(CallOperandVal))
2870 weight = CW_Constant;
2879 /// Given a register class constraint, like 'r', if this corresponds directly
2880 /// to an LLVM register class, return a register of 0 and the register class
2882 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
2883 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
2885 if (Constraint.size() == 1) {
2886 switch (Constraint[0]) {
2887 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
2888 case 'y': // Same as 'r'. Exists for compatibility.
2890 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
2891 if (Subtarget->inMips16Mode())
2892 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
2893 return std::make_pair(0U, &Mips::CPURegsRegClass);
2895 if (VT == MVT::i64 && !HasMips64)
2896 return std::make_pair(0U, &Mips::CPURegsRegClass);
2897 if (VT == MVT::i64 && HasMips64)
2898 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
2899 // This will generate an error message
2900 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2903 return std::make_pair(0U, &Mips::FGR32RegClass);
2904 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
2905 if (Subtarget->isFP64bit())
2906 return std::make_pair(0U, &Mips::FGR64RegClass);
2907 return std::make_pair(0U, &Mips::AFGR64RegClass);
2910 case 'c': // register suitable for indirect jump
2912 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
2913 assert(VT == MVT::i64 && "Unexpected type.");
2914 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
2915 case 'l': // register suitable for indirect jump
2917 return std::make_pair((unsigned)Mips::LO, &Mips::LORegsRegClass);
2918 return std::make_pair((unsigned)Mips::LO64, &Mips::LORegs64RegClass);
2919 case 'x': // register suitable for indirect jump
2920 // Fixme: Not triggering the use of both hi and low
2921 // This will generate an error message
2922 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2925 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2928 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2929 /// vector. If it is invalid, don't add anything to Ops.
2930 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2931 std::string &Constraint,
2932 std::vector<SDValue>&Ops,
2933 SelectionDAG &DAG) const {
2934 SDValue Result(0, 0);
2936 // Only support length 1 constraints for now.
2937 if (Constraint.length() > 1) return;
2939 char ConstraintLetter = Constraint[0];
2940 switch (ConstraintLetter) {
2941 default: break; // This will fall through to the generic implementation
2942 case 'I': // Signed 16 bit constant
2943 // If this fails, the parent routine will give an error
2944 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2945 EVT Type = Op.getValueType();
2946 int64_t Val = C->getSExtValue();
2947 if (isInt<16>(Val)) {
2948 Result = DAG.getTargetConstant(Val, Type);
2953 case 'J': // integer zero
2954 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2955 EVT Type = Op.getValueType();
2956 int64_t Val = C->getZExtValue();
2958 Result = DAG.getTargetConstant(0, Type);
2963 case 'K': // unsigned 16 bit immediate
2964 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2965 EVT Type = Op.getValueType();
2966 uint64_t Val = (uint64_t)C->getZExtValue();
2967 if (isUInt<16>(Val)) {
2968 Result = DAG.getTargetConstant(Val, Type);
2973 case 'L': // signed 32 bit immediate where lower 16 bits are 0
2974 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2975 EVT Type = Op.getValueType();
2976 int64_t Val = C->getSExtValue();
2977 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
2978 Result = DAG.getTargetConstant(Val, Type);
2983 case 'N': // immediate in the range of -65535 to -1 (inclusive)
2984 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2985 EVT Type = Op.getValueType();
2986 int64_t Val = C->getSExtValue();
2987 if ((Val >= -65535) && (Val <= -1)) {
2988 Result = DAG.getTargetConstant(Val, Type);
2993 case 'O': // signed 15 bit immediate
2994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2995 EVT Type = Op.getValueType();
2996 int64_t Val = C->getSExtValue();
2997 if ((isInt<15>(Val))) {
2998 Result = DAG.getTargetConstant(Val, Type);
3003 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3005 EVT Type = Op.getValueType();
3006 int64_t Val = C->getSExtValue();
3007 if ((Val <= 65535) && (Val >= 1)) {
3008 Result = DAG.getTargetConstant(Val, Type);
3015 if (Result.getNode()) {
3016 Ops.push_back(Result);
3020 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3024 MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
3025 // No global is ever allowed as a base.
3030 case 0: // "r+i" or just "i", depending on HasBaseReg.
3033 if (!AM.HasBaseReg) // allow "r+i".
3035 return false; // disallow "r+r" or "r+r+i".
3044 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3045 // The Mips target isn't yet aware of offsets.
3049 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3051 bool IsMemset, bool ZeroMemset,
3053 MachineFunction &MF) const {
3054 if (Subtarget->hasMips64())
3060 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3061 if (VT != MVT::f32 && VT != MVT::f64)
3063 if (Imm.isNegZero())
3065 return Imm.isZero();
3068 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3070 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3072 return TargetLowering::getJumpTableEncoding();
3075 /// This function returns true if CallSym is a long double emulation routine.
3076 static bool isF128SoftLibCall(const char *CallSym) {
3077 const char *const LibCalls[] =
3078 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2",
3079 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi",
3080 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf",
3081 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2",
3082 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3",
3083 "__trunctfdf2", "__trunctfsf2", "__unordtf2",
3084 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl",
3085 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl",
3088 const char * const *End = LibCalls + array_lengthof(LibCalls);
3090 // Check that LibCalls is sorted alphabetically.
3091 MipsTargetLowering::LTStr Comp;
3094 for (const char * const *I = LibCalls; I < End - 1; ++I)
3095 assert(Comp(*I, *(I + 1)));
3098 return std::binary_search(LibCalls, End, CallSym, Comp);
3101 /// This function returns true if Ty is fp128 or i128 which was originally a
3103 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) {
3104 if (Ty->isFP128Ty())
3107 const ExternalSymbolSDNode *ES =
3108 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode);
3110 // If the Ty is i128 and the function being called is a long double emulation
3111 // routine, then the original type is f128.
3112 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol()));
3115 MipsTargetLowering::MipsCC::SpecialCallingConvType
3116 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
3117 MipsCC::SpecialCallingConvType SpecialCallingConv =
3118 MipsCC::NoSpecialCallingConv;;
3119 if (Subtarget->inMips16HardFloat()) {
3120 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3121 llvm::StringRef Sym = G->getGlobal()->getName();
3122 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3123 if (F->hasFnAttribute("__Mips16RetHelper")) {
3124 SpecialCallingConv = MipsCC::Mips16RetHelperConv;
3128 return SpecialCallingConv;
3131 MipsTargetLowering::MipsCC::MipsCC(
3132 CallingConv::ID CC, bool IsO32_, CCState &Info,
3133 MipsCC::SpecialCallingConvType SpecialCallingConv_)
3134 : CCInfo(Info), CallConv(CC), IsO32(IsO32_),
3135 SpecialCallingConv(SpecialCallingConv_){
3136 // Pre-allocate reserved argument area.
3137 CCInfo.AllocateStack(reservedArgArea(), 1);
3141 void MipsTargetLowering::MipsCC::
3142 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
3143 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode,
3144 std::vector<ArgListEntry> &FuncArgs) {
3145 assert((CallConv != CallingConv::Fast || !IsVarArg) &&
3146 "CallingConv::Fast shouldn't be used for vararg functions.");
3148 unsigned NumOpnds = Args.size();
3149 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn();
3151 for (unsigned I = 0; I != NumOpnds; ++I) {
3152 MVT ArgVT = Args[I].VT;
3153 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3156 if (ArgFlags.isByVal()) {
3157 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3161 if (IsVarArg && !Args[I].IsFixed)
3162 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3164 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
3166 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo);
3171 dbgs() << "Call operand #" << I << " has unhandled type "
3172 << EVT(ArgVT).getEVTString();
3174 llvm_unreachable(0);
3179 void MipsTargetLowering::MipsCC::
3180 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
3181 bool IsSoftFloat, Function::const_arg_iterator FuncArg) {
3182 unsigned NumArgs = Args.size();
3183 llvm::CCAssignFn *FixedFn = fixedArgFn();
3184 unsigned CurArgIdx = 0;
3186 for (unsigned I = 0; I != NumArgs; ++I) {
3187 MVT ArgVT = Args[I].VT;
3188 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3189 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
3190 CurArgIdx = Args[I].OrigArgIndex;
3192 if (ArgFlags.isByVal()) {
3193 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags);
3197 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat);
3199 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo))
3203 dbgs() << "Formal Arg #" << I << " has unhandled type "
3204 << EVT(ArgVT).getEVTString();
3206 llvm_unreachable(0);
3210 template<typename Ty>
3211 void MipsTargetLowering::MipsCC::
3212 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
3213 const SDNode *CallNode, const Type *RetTy) const {
3216 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode))
3217 Fn = RetCC_F128Soft;
3221 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) {
3222 MVT VT = RetVals[I].VT;
3223 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
3224 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat);
3226 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) {
3228 dbgs() << "Call result #" << I << " has unhandled type "
3229 << EVT(VT).getEVTString() << '\n';
3231 llvm_unreachable(0);
3236 void MipsTargetLowering::MipsCC::
3237 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
3238 const SDNode *CallNode, const Type *RetTy) const {
3239 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy);
3242 void MipsTargetLowering::MipsCC::
3243 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
3244 const Type *RetTy) const {
3245 analyzeReturn(Outs, IsSoftFloat, 0, RetTy);
3249 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
3251 CCValAssign::LocInfo LocInfo,
3252 ISD::ArgFlagsTy ArgFlags) {
3253 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
3255 struct ByValArgInfo ByVal;
3256 unsigned RegSize = regSize();
3257 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize);
3258 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize),
3261 if (useRegsForByval())
3262 allocateRegs(ByVal, ByValSize, Align);
3264 // Allocate space on caller's stack.
3265 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs,
3267 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT,
3269 ByValArgs.push_back(ByVal);
3272 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
3273 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs);
3276 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
3277 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
3280 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
3281 return IsO32 ? O32IntRegs : Mips64IntRegs;
3284 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
3285 if (CallConv == CallingConv::Fast)
3286 return CC_Mips_FastCC;
3288 if (SpecialCallingConv == Mips16RetHelperConv)
3289 return CC_Mips16RetHelper;
3290 return IsO32 ? CC_MipsO32 : CC_MipsN;
3293 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const {
3294 return IsO32 ? CC_MipsO32 : CC_MipsN_VarArg;
3297 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
3298 return IsO32 ? O32IntRegs : Mips64DPRegs;
3301 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
3304 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
3305 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
3306 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
3307 "Byval argument's size and alignment should be a multiple of"
3310 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
3312 // If Align > RegSize, the first arg register must be even.
3313 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) {
3314 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
3318 // Mark the registers allocated.
3319 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
3320 ByValSize -= RegSize, ++I, ++ByVal.NumRegs)
3321 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3324 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
3325 const SDNode *CallNode,
3326 bool IsSoftFloat) const {
3327 if (IsSoftFloat || IsO32)
3330 // Check if the original type was fp128.
3331 if (originalTypeIsF128(OrigTy, CallNode)) {
3332 assert(VT == MVT::i64);
3339 void MipsTargetLowering::
3340 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
3341 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3342 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
3343 const MipsCC &CC, const ByValArgInfo &ByVal) const {
3344 MachineFunction &MF = DAG.getMachineFunction();
3345 MachineFrameInfo *MFI = MF.getFrameInfo();
3346 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize();
3347 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3351 FrameObjOffset = (int)CC.reservedArgArea() -
3352 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize());
3354 FrameObjOffset = ByVal.Address;
3356 // Create frame object.
3357 EVT PtrTy = getPointerTy();
3358 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3359 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3360 InVals.push_back(FIN);
3365 // Copy arg registers.
3366 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8);
3367 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3369 for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
3370 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
3371 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3372 unsigned Offset = I * CC.regSize();
3373 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3374 DAG.getConstant(Offset, PtrTy));
3375 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3376 StorePtr, MachinePointerInfo(FuncArg, Offset),
3378 OutChains.push_back(Store);
3382 // Copy byVal arg to registers and stack.
3383 void MipsTargetLowering::
3384 passByValArg(SDValue Chain, SDLoc DL,
3385 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
3386 SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
3387 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
3388 const MipsCC &CC, const ByValArgInfo &ByVal,
3389 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3390 unsigned ByValSize = Flags.getByValSize();
3391 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
3392 unsigned RegSize = CC.regSize();
3393 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize);
3394 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
3396 if (ByVal.NumRegs) {
3397 const uint16_t *ArgRegs = CC.intArgRegs();
3398 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
3401 // Copy words to registers.
3402 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) {
3403 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3404 DAG.getConstant(Offset, PtrTy));
3405 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3406 MachinePointerInfo(), false, false, false,
3408 MemOpChains.push_back(LoadVal.getValue(1));
3409 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3410 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3413 // Return if the struct has been fully copied.
3414 if (ByValSize == Offset)
3417 // Copy the remainder of the byval argument with sub-word loads and shifts.
3418 if (LeftoverBytes) {
3419 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) &&
3420 "Size of the remainder should be smaller than RegSize.");
3423 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0;
3424 Offset < ByValSize; LoadSize /= 2) {
3425 unsigned RemSize = ByValSize - Offset;
3427 if (RemSize < LoadSize)
3431 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3432 DAG.getConstant(Offset, PtrTy));
3434 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3435 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
3436 false, false, Alignment);
3437 MemOpChains.push_back(LoadVal.getValue(1));
3439 // Shift the loaded value.
3443 Shamt = TotalSizeLoaded;
3445 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8;
3447 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3448 DAG.getConstant(Shamt, MVT::i32));
3451 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3456 TotalSizeLoaded += LoadSize;
3457 Alignment = std::min(Alignment, LoadSize);
3460 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
3461 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3466 // Copy remainder of byval arg to it with memcpy.
3467 unsigned MemCpySize = ByValSize - Offset;
3468 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3469 DAG.getConstant(Offset, PtrTy));
3470 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3471 DAG.getIntPtrConstant(ByVal.Address));
3472 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3473 DAG.getConstant(MemCpySize, PtrTy), Alignment,
3474 /*isVolatile=*/false, /*AlwaysInline=*/false,
3475 MachinePointerInfo(0), MachinePointerInfo(0));
3476 MemOpChains.push_back(Chain);
3480 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3481 const MipsCC &CC, SDValue Chain,
3482 SDLoc DL, SelectionDAG &DAG) const {
3483 unsigned NumRegs = CC.numIntArgRegs();
3484 const uint16_t *ArgRegs = CC.intArgRegs();
3485 const CCState &CCInfo = CC.getCCInfo();
3486 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
3487 unsigned RegSize = CC.regSize();
3488 MVT RegTy = MVT::getIntegerVT(RegSize * 8);
3489 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3490 MachineFunction &MF = DAG.getMachineFunction();
3491 MachineFrameInfo *MFI = MF.getFrameInfo();
3492 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3494 // Offset of the first variable argument from stack pointer.
3498 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize);
3501 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx));
3503 // Record the frame index of the first variable argument
3504 // which is a value necessary to VASTART.
3505 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3506 MipsFI->setVarArgsFrameIndex(FI);
3508 // Copy the integer registers that have not been used for argument passing
3509 // to the argument register save area. For O32, the save area is allocated
3510 // in the caller's stack frame, while for N32/64, it is allocated in the
3511 // callee's stack frame.
3512 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) {
3513 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3514 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3515 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true);
3516 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
3517 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3518 MachinePointerInfo(), false, false, 0);
3519 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0);
3520 OutChains.push_back(Store);