1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
17 #include "MipsISelLowering.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsTargetMachine.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
39 const char *MipsTargetLowering::
40 getTargetNodeName(unsigned Opcode) const
44 case MipsISD::JmpLink : return "MipsISD::JmpLink";
45 case MipsISD::Hi : return "MipsISD::Hi";
46 case MipsISD::Lo : return "MipsISD::Lo";
47 case MipsISD::GPRel : return "MipsISD::GPRel";
48 case MipsISD::Ret : return "MipsISD::Ret";
49 case MipsISD::SelectCC : return "MipsISD::SelectCC";
50 case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
51 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
52 case MipsISD::FPCmp : return "MipsISD::FPCmp";
53 default : return NULL;
58 MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
60 Subtarget = &TM.getSubtarget<MipsSubtarget>();
62 // Mips does not have i1 type, so use i32 for
63 // setcc operations results (slt, sgt, ...).
64 setSetCCResultContents(ZeroOrOneSetCCResult);
66 // JumpTable targets must use GOT when using PIC_
67 setUsesGlobalOffsetTable(true);
69 // Set up the register classes
70 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 // When dealing with single precision only, use libcalls
73 if (!Subtarget->isSingleFloat()) {
74 addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
75 if (!Subtarget->isFP64bit())
76 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
78 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
81 addLegalFPImmediate(APFloat(+0.0f));
83 // Load extented operations for i1 types must be promoted
84 setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
85 setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote);
86 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 // Mips Custom Operations
89 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
90 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
91 setOperationAction(ISD::RET, MVT::Other, Custom);
92 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
93 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
94 setOperationAction(ISD::SELECT, MVT::f32, Custom);
95 setOperationAction(ISD::SELECT, MVT::i32, Custom);
96 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
97 setOperationAction(ISD::SETCC, MVT::f32, Custom);
98 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
100 // Operations not directly supported by Mips.
101 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
102 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
103 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
104 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
105 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
107 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
108 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
109 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
110 setOperationAction(ISD::ROTL, MVT::i32, Expand);
111 setOperationAction(ISD::ROTR, MVT::i32, Expand);
112 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
113 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
114 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
115 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
117 // We don't have line number support yet.
118 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
119 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
120 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
121 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
123 // Use the default for now
124 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
125 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
126 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
128 if (Subtarget->isSingleFloat())
129 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
131 if (!Subtarget->hasSEInReg()) {
132 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
133 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
136 setStackPointerRegisterToSaveRestore(Mips::SP);
137 computeRegisterProperties();
141 MVT MipsTargetLowering::getSetCCResultType(const SDValue &) const {
146 SDValue MipsTargetLowering::
147 LowerOperation(SDValue Op, SelectionDAG &DAG)
149 switch (Op.getOpcode())
151 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
152 case ISD::CALL: return LowerCALL(Op, DAG);
153 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
154 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
155 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
156 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
157 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
158 case ISD::RET: return LowerRET(Op, DAG);
159 case ISD::SELECT: return LowerSELECT(Op, DAG);
160 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
161 case ISD::SETCC: return LowerSETCC(Op, DAG);
166 //===----------------------------------------------------------------------===//
167 // Lower helper functions
168 //===----------------------------------------------------------------------===//
170 // AddLiveIn - This helper function adds the specified physical register to the
171 // MachineFunction as a live in value. It also creates a corresponding
172 // virtual register for it.
174 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
176 assert(RC->contains(PReg) && "Not the correct regclass!");
177 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
178 MF.getRegInfo().addLiveIn(PReg, VReg);
182 // A address must be loaded from a small section if its size is less than the
183 // small section size threshold. Data in this section must be addressed using
185 bool MipsTargetLowering::IsInSmallSection(unsigned Size) {
186 return (Size > 0 && (Size <= Subtarget->getSSectionThreshold()));
189 // Discover if this global address can be placed into small data/bss section.
190 bool MipsTargetLowering::IsGlobalInSmallSection(GlobalValue *GV)
192 const TargetData *TD = getTargetData();
193 const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV);
198 const Type *Ty = GV->getType()->getElementType();
199 unsigned Size = TD->getABITypeSize(Ty);
201 // if this is a internal constant string, there is a special
202 // section for it, but not in small data/bss.
203 if (GVA->hasInitializer() && GV->hasInternalLinkage()) {
204 Constant *C = GVA->getInitializer();
205 const ConstantArray *CVA = dyn_cast<ConstantArray>(C);
206 if (CVA && CVA->isCString())
210 return IsInSmallSection(Size);
213 // Get fp branch code (not opcode) from condition code.
214 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
215 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
216 return Mips::BRANCH_T;
218 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
219 return Mips::BRANCH_F;
221 return Mips::BRANCH_INVALID;
224 static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
227 assert(0 && "Unknown branch code");
228 case Mips::BRANCH_T : return Mips::BC1T;
229 case Mips::BRANCH_F : return Mips::BC1F;
230 case Mips::BRANCH_TL : return Mips::BC1TL;
231 case Mips::BRANCH_FL : return Mips::BC1FL;
235 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
237 default: assert(0 && "Unknown fp condition code!");
239 case ISD::SETOEQ: return Mips::FCOND_EQ;
240 case ISD::SETUNE: return Mips::FCOND_OGL;
242 case ISD::SETOLT: return Mips::FCOND_OLT;
244 case ISD::SETOGT: return Mips::FCOND_OGT;
246 case ISD::SETOLE: return Mips::FCOND_OLE;
248 case ISD::SETOGE: return Mips::FCOND_OGE;
249 case ISD::SETULT: return Mips::FCOND_ULT;
250 case ISD::SETULE: return Mips::FCOND_ULE;
251 case ISD::SETUGT: return Mips::FCOND_UGT;
252 case ISD::SETUGE: return Mips::FCOND_UGE;
253 case ISD::SETUO: return Mips::FCOND_UN;
254 case ISD::SETO: return Mips::FCOND_OR;
256 case ISD::SETONE: return Mips::FCOND_NEQ;
257 case ISD::SETUEQ: return Mips::FCOND_UEQ;
262 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
263 MachineBasicBlock *BB)
265 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
266 bool isFPCmp = false;
268 switch (MI->getOpcode()) {
269 default: assert(false && "Unexpected instr type to insert");
270 case Mips::Select_FCC:
271 case Mips::Select_FCC_SO32:
272 case Mips::Select_FCC_AS32:
273 case Mips::Select_FCC_D32:
274 isFPCmp = true; // FALL THROUGH
275 case Mips::Select_CC:
276 case Mips::Select_CC_SO32:
277 case Mips::Select_CC_AS32:
278 case Mips::Select_CC_D32: {
279 // To "insert" a SELECT_CC instruction, we actually have to insert the
280 // diamond control-flow pattern. The incoming instruction knows the
281 // destination vreg to set, the condition code register to branch on, the
282 // true/false values to select between, and a branch opcode to use.
283 const BasicBlock *LLVM_BB = BB->getBasicBlock();
284 MachineFunction::iterator It = BB;
291 // bNE r1, r0, copy1MBB
292 // fallthrough --> copy0MBB
293 MachineBasicBlock *thisMBB = BB;
294 MachineFunction *F = BB->getParent();
295 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
296 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
298 // Emit the right instruction according to the type of the operands compared
300 // Find the condiction code present in the setcc operation.
301 Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
302 // Get the branch opcode from the branch code.
303 unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
304 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
306 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
307 .addReg(Mips::ZERO).addMBB(sinkMBB);
309 F->insert(It, copy0MBB);
310 F->insert(It, sinkMBB);
311 // Update machine-CFG edges by first adding all successors of the current
312 // block to the new block which will contain the Phi node for the select.
313 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
314 e = BB->succ_end(); i != e; ++i)
315 sinkMBB->addSuccessor(*i);
316 // Next, remove all successors of the current block, and add the true
317 // and fallthrough blocks as its successors.
318 while(!BB->succ_empty())
319 BB->removeSuccessor(BB->succ_begin());
320 BB->addSuccessor(copy0MBB);
321 BB->addSuccessor(sinkMBB);
325 // # fallthrough to sinkMBB
328 // Update machine-CFG edges
329 BB->addSuccessor(sinkMBB);
332 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
335 BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
336 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
337 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
339 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
345 //===----------------------------------------------------------------------===//
346 // Misc Lower Operation implementation
347 //===----------------------------------------------------------------------===//
349 SDValue MipsTargetLowering::
350 LowerBRCOND(SDValue Op, SelectionDAG &DAG)
352 // The first operand is the chain, the second is the condition, the third is
353 // the block to branch to if the condition is true.
354 SDValue Chain = Op.getOperand(0);
355 SDValue Dest = Op.getOperand(2);
358 if (Op.getOperand(1).getOpcode() == ISD::AND) {
359 CondRes = Op.getOperand(1).getOperand(0);
360 if (CondRes.getOpcode() != MipsISD::FPCmp)
362 } else if (Op.getOperand(1).getOpcode() == MipsISD::FPCmp)
363 CondRes = Op.getOperand(1);
367 SDValue CCNode = CondRes.getOperand(2);
368 Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getValue();
369 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
371 return DAG.getNode(MipsISD::FPBrcond, Op.getValueType(), Chain, BrCode,
375 SDValue MipsTargetLowering::
376 LowerSETCC(SDValue Op, SelectionDAG &DAG)
378 // The operands to this are the left and right operands to compare (ops #0,
379 // and #1) and the condition code to compare them with (op #2) as a
381 SDValue LHS = Op.getOperand(0);
382 SDValue RHS = Op.getOperand(1);
384 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
386 return DAG.getNode(MipsISD::FPCmp, Op.getValueType(), LHS, RHS,
387 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
390 SDValue MipsTargetLowering::
391 LowerSELECT(SDValue Op, SelectionDAG &DAG)
393 SDValue Cond = Op.getOperand(0);
394 SDValue True = Op.getOperand(1);
395 SDValue False = Op.getOperand(2);
397 // this can be a fp select but with a setcc comming from a
399 if (Cond.getOpcode() == ISD::SETCC)
400 if (Cond.getOperand(0).getValueType().isInteger())
401 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
404 // Otherwise we're dealing with floating point compare.
406 if (Cond.getOpcode() == ISD::AND)
407 CondRes = Cond.getOperand(0);
408 else if (Cond.getOpcode() == MipsISD::FPCmp)
411 assert(0 && "Incoming condition flag unknown");
413 SDValue CCNode = CondRes.getOperand(2);
414 return DAG.getNode(MipsISD::FPSelectCC, True.getValueType(),
415 CondRes, True, False, CCNode);
418 SDValue MipsTargetLowering::
419 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
421 SDValue LHS = Op.getOperand(0);
422 SDValue RHS = Op.getOperand(1);
423 SDValue True = Op.getOperand(2);
424 SDValue False = Op.getOperand(3);
425 SDValue CC = Op.getOperand(4);
427 SDValue SetCCRes = DAG.getNode(ISD::SETCC, LHS.getValueType(), LHS, RHS, CC);
428 return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
429 SetCCRes, True, False);
432 SDValue MipsTargetLowering::
433 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
435 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
436 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
438 if (!Subtarget->hasABICall()) {
439 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
440 SDValue Ops[] = { GA };
441 // %gp_rel relocation
442 if (!isa<Function>(GV) && IsGlobalInSmallSection(GV)) {
443 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, VTs, 1, Ops, 1);
444 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
445 return DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
447 // %hi/%lo relocation
448 SDValue HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
449 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
450 return DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
452 } else { // Abicall relocations, TODO: make this cleaner.
453 SDValue ResNode = DAG.getLoad(MVT::i32, DAG.getEntryNode(), GA, NULL, 0);
454 // On functions and global targets not internal linked only
455 // a load from got/GP is necessary for PIC to work.
456 if (!GV->hasInternalLinkage() || isa<Function>(GV))
458 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, GA);
459 return DAG.getNode(ISD::ADD, MVT::i32, ResNode, Lo);
462 assert(0 && "Dont know how to handle GlobalAddress");
466 SDValue MipsTargetLowering::
467 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
469 assert(0 && "TLS not implemented for MIPS.");
470 return SDValue(); // Not reached
473 SDValue MipsTargetLowering::
474 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
479 MVT PtrVT = Op.getValueType();
480 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
481 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
483 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
484 const MVT *VTs = DAG.getNodeValueTypes(MVT::i32);
485 SDValue Ops[] = { JTI };
486 HiPart = DAG.getNode(MipsISD::Hi, VTs, 1, Ops, 1);
487 } else // Emit Load from Global Pointer
488 HiPart = DAG.getLoad(MVT::i32, DAG.getEntryNode(), JTI, NULL, 0);
490 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, JTI);
491 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
496 SDValue MipsTargetLowering::
497 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
500 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
501 Constant *C = N->getConstVal();
502 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
505 // FIXME: we should reference the constant pool using small data sections,
506 // but the asm printer currently doens't support this feature without
507 // hacking it. This feature should come soon so we can uncomment the
509 //if (!Subtarget->hasABICall() &&
510 // IsInSmallSection(getTargetData()->getABITypeSize(C->getType()))) {
511 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
512 // SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i32);
513 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
514 //} else { // %hi/%lo relocation
515 SDValue HiPart = DAG.getNode(MipsISD::Hi, MVT::i32, CP);
516 SDValue Lo = DAG.getNode(MipsISD::Lo, MVT::i32, CP);
517 ResNode = DAG.getNode(ISD::ADD, MVT::i32, HiPart, Lo);
523 //===----------------------------------------------------------------------===//
524 // Calling Convention Implementation
526 // The lower operations present on calling convention works on this order:
527 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
528 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
529 // LowerRET (virt regs --> phys regs)
530 // LowerCALL (phys regs --> virt regs)
532 //===----------------------------------------------------------------------===//
534 #include "MipsGenCallingConv.inc"
536 //===----------------------------------------------------------------------===//
537 // CALL Calling Convention Implementation
538 //===----------------------------------------------------------------------===//
540 /// Mips custom CALL implementation
541 SDValue MipsTargetLowering::
542 LowerCALL(SDValue Op, SelectionDAG &DAG)
544 unsigned CallingConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
546 // By now, only CallingConv::C implemented
547 switch (CallingConv) {
549 assert(0 && "Unsupported calling convention");
550 case CallingConv::Fast:
552 return LowerCCCCallTo(Op, DAG, CallingConv);
556 /// LowerCCCCallTo - functions arguments are copied from virtual
557 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
558 /// CALLSEQ_END are emitted.
559 /// TODO: isVarArg, isTailCall.
560 SDValue MipsTargetLowering::
561 LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
563 MachineFunction &MF = DAG.getMachineFunction();
565 SDValue Chain = Op.getOperand(0);
566 SDValue Callee = Op.getOperand(4);
567 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
569 MachineFrameInfo *MFI = MF.getFrameInfo();
571 // Analyze operands of the call, assigning locations to each operand.
572 SmallVector<CCValAssign, 16> ArgLocs;
573 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
575 // To meet O32 ABI, Mips must always allocate 16 bytes on
576 // the stack (even if less than 4 are used as arguments)
577 if (Subtarget->isABI_O32()) {
578 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
579 MFI->CreateFixedObject(VTsize, (VTsize*3));
582 CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
584 // Get a count of how many bytes are to be pushed on the stack.
585 unsigned NumBytes = CCInfo.getNextStackOffset();
586 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
589 // With EABI is it possible to have 16 args on registers.
590 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
591 SmallVector<SDValue, 8> MemOpChains;
593 // First/LastArgStackLoc contains the first/last
594 // "at stack" argument location.
595 int LastArgStackLoc = 0;
596 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
598 // Walk the register/memloc assignments, inserting copies/loads.
599 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
600 CCValAssign &VA = ArgLocs[i];
602 // Arguments start after the 5 first operands of ISD::CALL
603 SDValue Arg = Op.getOperand(5+2*VA.getValNo());
605 // Promote the value if needed.
606 switch (VA.getLocInfo()) {
607 default: assert(0 && "Unknown loc info!");
608 case CCValAssign::Full: break;
609 case CCValAssign::SExt:
610 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
612 case CCValAssign::ZExt:
613 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
615 case CCValAssign::AExt:
616 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
620 // Arguments that can be passed on register must be kept at
623 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
627 // Register cant get to this point...
628 assert(VA.isMemLoc());
630 // Create the frame index object for this incoming parameter
631 // This guarantees that when allocating Local Area the firsts
632 // 16 bytes which are alwayes reserved won't be overwritten
633 // if O32 ABI is used. For EABI the first address is zero.
634 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
635 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
638 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
640 // emit ISD::STORE whichs stores the
641 // parameter value to a stack Location
642 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
645 // Transform all store nodes into one single node because all store
646 // nodes are independent of each other.
647 if (!MemOpChains.empty())
648 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
649 &MemOpChains[0], MemOpChains.size());
651 // Build a sequence of copy-to-reg nodes chained together with token
652 // chain and flag operands which copy the outgoing args into registers.
653 // The InFlag in necessary since all emited instructions must be
656 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
657 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first,
658 RegsToPass[i].second, InFlag);
659 InFlag = Chain.getValue(1);
662 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
663 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
664 // node so that legalize doesn't hack it.
665 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
666 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
667 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
668 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
671 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
672 // = Chain, Callee, Reg#1, Reg#2, ...
674 // Returns a chain & a flag for retval copy to use.
675 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
676 SmallVector<SDValue, 8> Ops;
677 Ops.push_back(Chain);
678 Ops.push_back(Callee);
680 // Add argument registers to the end of the list so that they are
681 // known live into the call.
682 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
683 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
684 RegsToPass[i].second.getValueType()));
687 Ops.push_back(InFlag);
689 Chain = DAG.getNode(MipsISD::JmpLink, NodeTys, &Ops[0], Ops.size());
690 InFlag = Chain.getValue(1);
692 // Create the CALLSEQ_END node.
693 Chain = DAG.getCALLSEQ_END(Chain,
694 DAG.getConstant(NumBytes, getPointerTy()),
695 DAG.getConstant(0, getPointerTy()),
697 InFlag = Chain.getValue(1);
699 // Create a stack location to hold GP when PIC is used. This stack
700 // location is used on function prologue to save GP and also after all
701 // emited CALL's to restore GP.
702 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
703 // Function can have an arbitrary number of calls, so
704 // hold the LastArgStackLoc with the biggest offset.
706 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
707 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
708 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
709 // Create the frame index only once. SPOffset here can be anything
710 // (this will be fixed on processFunctionBeforeFrameFinalized)
711 if (MipsFI->getGPStackOffset() == -1) {
712 FI = MFI->CreateFixedObject(4, 0);
715 MipsFI->setGPStackOffset(LastArgStackLoc);
719 FI = MipsFI->getGPFI();
720 SDValue FIN = DAG.getFrameIndex(FI,getPointerTy());
721 SDValue GPLoad = DAG.getLoad(MVT::i32, Chain, FIN, NULL, 0);
722 Chain = GPLoad.getValue(1);
723 Chain = DAG.getCopyToReg(Chain, DAG.getRegister(Mips::GP, MVT::i32),
724 GPLoad, SDValue(0,0));
725 InFlag = Chain.getValue(1);
728 // Handle result values, copying them out of physregs into vregs that we
730 return SDValue(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
733 /// LowerCallResult - Lower the result values of an ISD::CALL into the
734 /// appropriate copies out of appropriate physical registers. This assumes that
735 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
736 /// being lowered. Returns a SDNode with the same number of values as the
738 SDNode *MipsTargetLowering::
739 LowerCallResult(SDValue Chain, SDValue InFlag, SDNode *TheCall,
740 unsigned CallingConv, SelectionDAG &DAG) {
742 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
744 // Assign locations to each value returned by this call.
745 SmallVector<CCValAssign, 16> RVLocs;
746 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
748 CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
749 SmallVector<SDValue, 8> ResultVals;
751 // Copy all of the result registers out of their specified physreg.
752 for (unsigned i = 0; i != RVLocs.size(); ++i) {
753 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
754 RVLocs[i].getValVT(), InFlag).getValue(1);
755 InFlag = Chain.getValue(2);
756 ResultVals.push_back(Chain.getValue(0));
759 ResultVals.push_back(Chain);
761 // Merge everything together with a MERGE_VALUES node.
762 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
763 ResultVals.size()).Val;
766 //===----------------------------------------------------------------------===//
767 // FORMAL_ARGUMENTS Calling Convention Implementation
768 //===----------------------------------------------------------------------===//
770 /// Mips custom FORMAL_ARGUMENTS implementation
771 SDValue MipsTargetLowering::
772 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
774 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
778 assert(0 && "Unsupported calling convention");
780 return LowerCCCArguments(Op, DAG);
784 /// LowerCCCArguments - transform physical registers into
785 /// virtual registers and generate load operations for
786 /// arguments places on the stack.
788 SDValue MipsTargetLowering::
789 LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
791 SDValue Root = Op.getOperand(0);
792 MachineFunction &MF = DAG.getMachineFunction();
793 MachineFrameInfo *MFI = MF.getFrameInfo();
794 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
796 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
797 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
799 unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
801 // GP must be live into PIC and non-PIC call target.
802 AddLiveIn(MF, Mips::GP, Mips::CPURegsRegisterClass);
804 // Assign locations to all of the incoming arguments.
805 SmallVector<CCValAssign, 16> ArgLocs;
806 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
808 CCInfo.AnalyzeFormalArguments(Op.Val, CC_Mips);
809 SmallVector<SDValue, 16> ArgValues;
812 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
814 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
816 CCValAssign &VA = ArgLocs[i];
818 // Arguments stored on registers
820 MVT RegVT = VA.getLocVT();
821 TargetRegisterClass *RC = 0;
823 if (RegVT == MVT::i32)
824 RC = Mips::CPURegsRegisterClass;
825 else if (RegVT == MVT::f32) {
826 if (Subtarget->isSingleFloat())
827 RC = Mips::FGR32RegisterClass;
829 RC = Mips::AFGR32RegisterClass;
830 } else if (RegVT == MVT::f64) {
831 if (!Subtarget->isSingleFloat())
832 RC = Mips::AFGR64RegisterClass;
834 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
836 // Transform the arguments stored on
837 // physical registers into virtual ones
838 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
839 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
841 // If this is an 8 or 16-bit value, it is really passed promoted
842 // to 32 bits. Insert an assert[sz]ext to capture this, then
843 // truncate to the right size.
844 if (VA.getLocInfo() == CCValAssign::SExt)
845 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
846 DAG.getValueType(VA.getValVT()));
847 else if (VA.getLocInfo() == CCValAssign::ZExt)
848 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
849 DAG.getValueType(VA.getValVT()));
851 if (VA.getLocInfo() != CCValAssign::Full)
852 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
854 ArgValues.push_back(ArgValue);
856 // To meet ABI, when VARARGS are passed on registers, the registers
857 // must have their values written to the caller stack frame.
858 if ((isVarArg) && (Subtarget->isABI_O32())) {
859 if (StackPtr.Val == 0)
860 StackPtr = DAG.getRegister(StackReg, getPointerTy());
862 // The stack pointer offset is relative to the caller stack frame.
863 // Since the real stack size is unknown here, a negative SPOffset
864 // is used so there's a way to adjust these offsets when the stack
865 // size get known (on EliminateFrameIndex). A dummy SPOffset is
866 // used instead of a direct negative address (which is recorded to
867 // be used on emitPrologue) to avoid mis-calc of the first stack
868 // offset on PEI::calculateFrameObjectOffsets.
869 // Arguments are always 32-bit.
870 int FI = MFI->CreateFixedObject(4, 0);
871 MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
872 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
874 // emit ISD::STORE whichs stores the
875 // parameter value to a stack Location
876 ArgValues.push_back(DAG.getStore(Root, ArgValue, PtrOff, NULL, 0));
879 } else { // VA.isRegLoc()
882 assert(VA.isMemLoc());
884 // The stack pointer offset is relative to the caller stack frame.
885 // Since the real stack size is unknown here, a negative SPOffset
886 // is used so there's a way to adjust these offsets when the stack
887 // size get known (on EliminateFrameIndex). A dummy SPOffset is
888 // used instead of a direct negative address (which is recorded to
889 // be used on emitPrologue) to avoid mis-calc of the first stack
890 // offset on PEI::calculateFrameObjectOffsets.
891 // Arguments are always 32-bit.
892 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
893 int FI = MFI->CreateFixedObject(ArgSize, 0);
894 MipsFI->recordLoadArgsFI(FI, -(ArgSize+
895 (FirstStackArgLoc + VA.getLocMemOffset())));
897 // Create load nodes to retrieve arguments from the stack
898 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
899 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
903 // The mips ABIs for returning structs by value requires that we copy
904 // the sret argument into $v0 for the return. Save the argument into
905 // a virtual register so that we can access it from the return points.
906 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
907 unsigned Reg = MipsFI->getSRetReturnReg();
909 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
910 MipsFI->setSRetReturnReg(Reg);
912 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
913 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
916 ArgValues.push_back(Root);
918 // Return the new list of results.
919 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
920 ArgValues.size()).getValue(Op.ResNo);
923 //===----------------------------------------------------------------------===//
924 // Return Value Calling Convention Implementation
925 //===----------------------------------------------------------------------===//
927 SDValue MipsTargetLowering::
928 LowerRET(SDValue Op, SelectionDAG &DAG)
930 // CCValAssign - represent the assignment of
931 // the return value to a location
932 SmallVector<CCValAssign, 16> RVLocs;
933 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
934 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
936 // CCState - Info about the registers and stack slot.
937 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
939 // Analize return values of ISD::RET
940 CCInfo.AnalyzeReturn(Op.Val, RetCC_Mips);
942 // If this is the first return lowered for this function, add
943 // the regs to the liveout set for the function.
944 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
945 for (unsigned i = 0; i != RVLocs.size(); ++i)
946 if (RVLocs[i].isRegLoc())
947 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
950 // The chain is always operand #0
951 SDValue Chain = Op.getOperand(0);
954 // Copy the result values into the output registers.
955 for (unsigned i = 0; i != RVLocs.size(); ++i) {
956 CCValAssign &VA = RVLocs[i];
957 assert(VA.isRegLoc() && "Can only return in registers!");
959 // ISD::RET => ret chain, (regnum1,val1), ...
960 // So i*2+1 index only the regnums
961 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
963 // guarantee that all emitted copies are
964 // stuck together, avoiding something bad
965 Flag = Chain.getValue(1);
968 // The mips ABIs for returning structs by value requires that we copy
969 // the sret argument into $v0 for the return. We saved the argument into
970 // a virtual register in the entry block, so now we copy the value out
972 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
973 MachineFunction &MF = DAG.getMachineFunction();
974 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
975 unsigned Reg = MipsFI->getSRetReturnReg();
978 assert(0 && "sret virtual register not created in the entry block");
979 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
981 Chain = DAG.getCopyToReg(Chain, Mips::V0, Val, Flag);
982 Flag = Chain.getValue(1);
985 // Return on Mips is always a "jr $ra"
987 return DAG.getNode(MipsISD::Ret, MVT::Other,
988 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
990 return DAG.getNode(MipsISD::Ret, MVT::Other,
991 Chain, DAG.getRegister(Mips::RA, MVT::i32));
994 //===----------------------------------------------------------------------===//
995 // Mips Inline Assembly Support
996 //===----------------------------------------------------------------------===//
998 /// getConstraintType - Given a constraint letter, return the type of
999 /// constraint it is for this target.
1000 MipsTargetLowering::ConstraintType MipsTargetLowering::
1001 getConstraintType(const std::string &Constraint) const
1003 // Mips specific constrainy
1004 // GCC config/mips/constraints.md
1006 // 'd' : An address register. Equivalent to r
1007 // unless generating MIPS16 code.
1008 // 'y' : Equivalent to r; retained for
1009 // backwards compatibility.
1010 // 'f' : Floating Point registers.
1011 if (Constraint.size() == 1) {
1012 switch (Constraint[0]) {
1017 return C_RegisterClass;
1021 return TargetLowering::getConstraintType(Constraint);
1024 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1025 /// return a list of registers that can be used to satisfy the constraint.
1026 /// This should only be used for C_RegisterClass constraints.
1027 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1028 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
1030 if (Constraint.size() == 1) {
1031 switch (Constraint[0]) {
1033 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1035 if (VT == MVT::f32) {
1036 if (Subtarget->isSingleFloat())
1037 return std::make_pair(0U, Mips::FGR32RegisterClass);
1039 return std::make_pair(0U, Mips::AFGR32RegisterClass);
1042 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1043 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1046 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1049 /// Given a register class constraint, like 'r', if this corresponds directly
1050 /// to an LLVM register class, return a register of 0 and the register class
1052 std::vector<unsigned> MipsTargetLowering::
1053 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1056 if (Constraint.size() != 1)
1057 return std::vector<unsigned>();
1059 switch (Constraint[0]) {
1062 // GCC Mips Constraint Letters
1065 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1066 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1067 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1071 if (VT == MVT::f32) {
1072 if (Subtarget->isSingleFloat())
1073 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1074 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1075 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1076 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1077 Mips::F30, Mips::F31, 0);
1079 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1080 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1081 Mips::F28, Mips::F30, 0);
1085 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1086 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1087 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1088 Mips::D14, Mips::D15, 0);
1090 return std::vector<unsigned>();