1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "mips-lower"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsTargetObjectFile.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
37 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
39 case MipsISD::JmpLink : return "MipsISD::JmpLink";
40 case MipsISD::Hi : return "MipsISD::Hi";
41 case MipsISD::Lo : return "MipsISD::Lo";
42 case MipsISD::GPRel : return "MipsISD::GPRel";
43 case MipsISD::Ret : return "MipsISD::Ret";
44 case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
45 case MipsISD::FPCmp : return "MipsISD::FPCmp";
46 case MipsISD::CMovFP_T : return "MipsISD::CMovFP_T";
47 case MipsISD::CMovFP_F : return "MipsISD::CMovFP_F";
48 case MipsISD::FPRound : return "MipsISD::FPRound";
49 case MipsISD::MAdd : return "MipsISD::MAdd";
50 case MipsISD::MAddu : return "MipsISD::MAddu";
51 case MipsISD::MSub : return "MipsISD::MSub";
52 case MipsISD::MSubu : return "MipsISD::MSubu";
53 case MipsISD::DivRem : return "MipsISD::DivRem";
54 case MipsISD::DivRemU : return "MipsISD::DivRemU";
55 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
56 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
57 default : return NULL;
62 MipsTargetLowering(MipsTargetMachine &TM)
63 : TargetLowering(TM, new MipsTargetObjectFile()) {
64 Subtarget = &TM.getSubtarget<MipsSubtarget>();
66 // Mips does not have i1 type, so use i32 for
67 // setcc operations results (slt, sgt, ...).
68 setBooleanContents(ZeroOrOneBooleanContent);
70 // Set up the register classes
71 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
72 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
74 // When dealing with single precision only, use libcalls
75 if (!Subtarget->isSingleFloat())
76 if (!Subtarget->isFP64bit())
77 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
79 // Load extented operations for i1 types must be promoted
80 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 // MIPS doesn't have extending float->double load/store
85 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // Used by legalize types to correctly generate the setcc result.
89 // Without this, every float setcc comes with a AND/OR with the result,
90 // we don't want this, since the fpcmp result goes to a flag register,
91 // which is used implicitly by brcond and select operations.
92 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
94 // Mips Custom Operations
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
97 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
98 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
99 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
100 setOperationAction(ISD::SELECT, MVT::f32, Custom);
101 setOperationAction(ISD::SELECT, MVT::f64, Custom);
102 setOperationAction(ISD::SELECT, MVT::i32, Custom);
103 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
104 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
105 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
106 setOperationAction(ISD::VASTART, MVT::Other, Custom);
108 setOperationAction(ISD::SDIV, MVT::i32, Expand);
109 setOperationAction(ISD::SREM, MVT::i32, Expand);
110 setOperationAction(ISD::UDIV, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
113 // Operations not directly supported by Mips.
114 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
115 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
117 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
120 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
121 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
122 setOperationAction(ISD::ROTL, MVT::i32, Expand);
124 if (!Subtarget->isMips32r2())
125 setOperationAction(ISD::ROTR, MVT::i32, Expand);
127 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
128 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
129 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
130 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
131 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
132 setOperationAction(ISD::FSIN, MVT::f32, Expand);
133 setOperationAction(ISD::FSIN, MVT::f64, Expand);
134 setOperationAction(ISD::FCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FCOS, MVT::f64, Expand);
136 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
137 setOperationAction(ISD::FPOW, MVT::f32, Expand);
138 setOperationAction(ISD::FLOG, MVT::f32, Expand);
139 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
140 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
141 setOperationAction(ISD::FEXP, MVT::f32, Expand);
143 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
145 setOperationAction(ISD::VAARG, MVT::Other, Expand);
146 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
147 setOperationAction(ISD::VAEND, MVT::Other, Expand);
149 // Use the default for now
150 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
151 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
152 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
154 if (Subtarget->isSingleFloat())
155 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
157 if (!Subtarget->hasSEInReg()) {
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
162 if (!Subtarget->hasBitCount())
163 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
165 if (!Subtarget->hasSwap())
166 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
168 setTargetDAGCombine(ISD::ADDE);
169 setTargetDAGCombine(ISD::SUBE);
170 setTargetDAGCombine(ISD::SDIVREM);
171 setTargetDAGCombine(ISD::UDIVREM);
172 setTargetDAGCombine(ISD::SETCC);
174 setMinFunctionAlignment(2);
176 setStackPointerRegisterToSaveRestore(Mips::SP);
177 computeRegisterProperties();
180 MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
185 // Transforms a subgraph in CurDAG if the following pattern is found:
186 // (addc multLo, Lo0), (adde multHi, Hi0),
188 // multHi/Lo: product of multiplication
189 // Lo0: initial value of Lo register
190 // Hi0: initial value of Hi register
191 // Return true if pattern matching was successful.
192 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
193 // ADDENode's second operand must be a flag output of an ADDC node in order
194 // for the matching to be successful.
195 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
197 if (ADDCNode->getOpcode() != ISD::ADDC)
200 SDValue MultHi = ADDENode->getOperand(0);
201 SDValue MultLo = ADDCNode->getOperand(0);
202 SDNode* MultNode = MultHi.getNode();
203 unsigned MultOpc = MultHi.getOpcode();
205 // MultHi and MultLo must be generated by the same node,
206 if (MultLo.getNode() != MultNode)
209 // and it must be a multiplication.
210 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
213 // MultLo amd MultHi must be the first and second output of MultNode
215 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
218 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
219 // of the values of MultNode, in which case MultNode will be removed in later
221 // If there exist users other than ADDENode or ADDCNode, this function returns
222 // here, which will result in MultNode being mapped to a single MULT
223 // instruction node rather than a pair of MULT and MADD instructions being
225 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
228 SDValue Chain = CurDAG->getEntryNode();
229 DebugLoc dl = ADDENode->getDebugLoc();
231 // create MipsMAdd(u) node
232 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
234 SDValue MAdd = CurDAG->getNode(MultOpc, dl,
236 MultNode->getOperand(0),// Factor 0
237 MultNode->getOperand(1),// Factor 1
238 ADDCNode->getOperand(1),// Lo0
239 ADDENode->getOperand(1));// Hi0
241 // create CopyFromReg nodes
242 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
244 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
246 CopyFromLo.getValue(2));
248 // replace uses of adde and addc here
249 if (!SDValue(ADDCNode, 0).use_empty())
250 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
252 if (!SDValue(ADDENode, 0).use_empty())
253 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
259 // Transforms a subgraph in CurDAG if the following pattern is found:
260 // (addc Lo0, multLo), (sube Hi0, multHi),
262 // multHi/Lo: product of multiplication
263 // Lo0: initial value of Lo register
264 // Hi0: initial value of Hi register
265 // Return true if pattern matching was successful.
266 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
267 // SUBENode's second operand must be a flag output of an SUBC node in order
268 // for the matching to be successful.
269 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
271 if (SUBCNode->getOpcode() != ISD::SUBC)
274 SDValue MultHi = SUBENode->getOperand(1);
275 SDValue MultLo = SUBCNode->getOperand(1);
276 SDNode* MultNode = MultHi.getNode();
277 unsigned MultOpc = MultHi.getOpcode();
279 // MultHi and MultLo must be generated by the same node,
280 if (MultLo.getNode() != MultNode)
283 // and it must be a multiplication.
284 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
287 // MultLo amd MultHi must be the first and second output of MultNode
289 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
292 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
293 // of the values of MultNode, in which case MultNode will be removed in later
295 // If there exist users other than SUBENode or SUBCNode, this function returns
296 // here, which will result in MultNode being mapped to a single MULT
297 // instruction node rather than a pair of MULT and MSUB instructions being
299 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
302 SDValue Chain = CurDAG->getEntryNode();
303 DebugLoc dl = SUBENode->getDebugLoc();
305 // create MipsSub(u) node
306 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
308 SDValue MSub = CurDAG->getNode(MultOpc, dl,
310 MultNode->getOperand(0),// Factor 0
311 MultNode->getOperand(1),// Factor 1
312 SUBCNode->getOperand(0),// Lo0
313 SUBENode->getOperand(0));// Hi0
315 // create CopyFromReg nodes
316 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
318 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
320 CopyFromLo.getValue(2));
322 // replace uses of sube and subc here
323 if (!SDValue(SUBCNode, 0).use_empty())
324 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
326 if (!SDValue(SUBENode, 0).use_empty())
327 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
332 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
333 TargetLowering::DAGCombinerInfo &DCI,
334 const MipsSubtarget* Subtarget) {
335 if (DCI.isBeforeLegalize())
338 if (Subtarget->isMips32() && SelectMadd(N, &DAG))
339 return SDValue(N, 0);
344 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
345 TargetLowering::DAGCombinerInfo &DCI,
346 const MipsSubtarget* Subtarget) {
347 if (DCI.isBeforeLegalize())
350 if (Subtarget->isMips32() && SelectMsub(N, &DAG))
351 return SDValue(N, 0);
356 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
357 TargetLowering::DAGCombinerInfo &DCI,
358 const MipsSubtarget* Subtarget) {
359 if (DCI.isBeforeLegalizeOps())
362 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
364 DebugLoc dl = N->getDebugLoc();
366 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
367 N->getOperand(0), N->getOperand(1));
368 SDValue InChain = DAG.getEntryNode();
369 SDValue InGlue = DivRem;
372 if (N->hasAnyUseOfValue(0)) {
373 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, Mips::LO, MVT::i32,
375 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
376 InChain = CopyFromLo.getValue(1);
377 InGlue = CopyFromLo.getValue(2);
381 if (N->hasAnyUseOfValue(1)) {
382 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
383 Mips::HI, MVT::i32, InGlue);
384 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
390 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
392 default: llvm_unreachable("Unknown fp condition code!");
394 case ISD::SETOEQ: return Mips::FCOND_OEQ;
395 case ISD::SETUNE: return Mips::FCOND_UNE;
397 case ISD::SETOLT: return Mips::FCOND_OLT;
399 case ISD::SETOGT: return Mips::FCOND_OGT;
401 case ISD::SETOLE: return Mips::FCOND_OLE;
403 case ISD::SETOGE: return Mips::FCOND_OGE;
404 case ISD::SETULT: return Mips::FCOND_ULT;
405 case ISD::SETULE: return Mips::FCOND_ULE;
406 case ISD::SETUGT: return Mips::FCOND_UGT;
407 case ISD::SETUGE: return Mips::FCOND_UGE;
408 case ISD::SETUO: return Mips::FCOND_UN;
409 case ISD::SETO: return Mips::FCOND_OR;
411 case ISD::SETONE: return Mips::FCOND_ONE;
412 case ISD::SETUEQ: return Mips::FCOND_UEQ;
417 // Returns true if condition code has to be inverted.
418 static bool InvertFPCondCode(Mips::CondCode CC) {
419 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
422 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
425 assert(false && "Illegal Condition Code");
429 // Creates and returns an FPCmp node from a setcc node.
430 // Returns Op if setcc is not a floating point comparison.
431 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
432 // must be a SETCC node
433 if (Op.getOpcode() != ISD::SETCC)
436 SDValue LHS = Op.getOperand(0);
438 if (!LHS.getValueType().isFloatingPoint())
441 SDValue RHS = Op.getOperand(1);
442 DebugLoc dl = Op.getDebugLoc();
444 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
445 // node if necessary.
446 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
448 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
449 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
452 // Creates and returns a CMovFPT/F node.
453 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
454 SDValue False, DebugLoc DL) {
455 bool invert = InvertFPCondCode((Mips::CondCode)
456 cast<ConstantSDNode>(Cond.getOperand(2))
459 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
460 True.getValueType(), True, False, Cond);
463 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG,
464 TargetLowering::DAGCombinerInfo &DCI,
465 const MipsSubtarget* Subtarget) {
466 if (DCI.isBeforeLegalizeOps())
469 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0));
471 if (Cond.getOpcode() != MipsISD::FPCmp)
474 SDValue True = DAG.getConstant(1, MVT::i32);
475 SDValue False = DAG.getConstant(0, MVT::i32);
477 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc());
480 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
482 SelectionDAG &DAG = DCI.DAG;
483 unsigned opc = N->getOpcode();
488 return PerformADDECombine(N, DAG, DCI, Subtarget);
490 return PerformSUBECombine(N, DAG, DCI, Subtarget);
493 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
495 return PerformSETCCCombine(N, DAG, DCI, Subtarget);
501 SDValue MipsTargetLowering::
502 LowerOperation(SDValue Op, SelectionDAG &DAG) const
504 switch (Op.getOpcode())
506 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
507 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
508 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
509 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
510 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
511 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
512 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
513 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
514 case ISD::SELECT: return LowerSELECT(Op, DAG);
515 case ISD::VASTART: return LowerVASTART(Op, DAG);
520 //===----------------------------------------------------------------------===//
521 // Lower helper functions
522 //===----------------------------------------------------------------------===//
524 // AddLiveIn - This helper function adds the specified physical register to the
525 // MachineFunction as a live in value. It also creates a corresponding
526 // virtual register for it.
528 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
530 assert(RC->contains(PReg) && "Not the correct regclass!");
531 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
532 MF.getRegInfo().addLiveIn(PReg, VReg);
536 // Get fp branch code (not opcode) from condition code.
537 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
538 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
539 return Mips::BRANCH_T;
541 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
542 return Mips::BRANCH_F;
544 return Mips::BRANCH_INVALID;
548 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
549 MachineBasicBlock *BB) const {
550 // There is no need to expand CMov instructions if target has
551 // conditional moves.
552 if (Subtarget->hasCondMov())
555 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
556 bool isFPCmp = false;
557 DebugLoc dl = MI->getDebugLoc();
560 switch (MI->getOpcode()) {
561 default: assert(false && "Unexpected instr type to insert");
586 // To "insert" a SELECT_CC instruction, we actually have to insert the
587 // diamond control-flow pattern. The incoming instruction knows the
588 // destination vreg to set, the condition code register to branch on, the
589 // true/false values to select between, and a branch opcode to use.
590 const BasicBlock *LLVM_BB = BB->getBasicBlock();
591 MachineFunction::iterator It = BB;
598 // bNE r1, r0, copy1MBB
599 // fallthrough --> copy0MBB
600 MachineBasicBlock *thisMBB = BB;
601 MachineFunction *F = BB->getParent();
602 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
603 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
604 F->insert(It, copy0MBB);
605 F->insert(It, sinkMBB);
607 // Transfer the remainder of BB and its successor edges to sinkMBB.
608 sinkMBB->splice(sinkMBB->begin(), BB,
609 llvm::next(MachineBasicBlock::iterator(MI)),
611 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
613 // Next, add the true and fallthrough blocks as its successors.
614 BB->addSuccessor(copy0MBB);
615 BB->addSuccessor(sinkMBB);
617 // Emit the right instruction according to the type of the operands compared
619 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
621 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
622 .addReg(Mips::ZERO).addMBB(sinkMBB);
627 // # fallthrough to sinkMBB
630 // Update machine-CFG edges
631 BB->addSuccessor(sinkMBB);
634 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
639 BuildMI(*BB, BB->begin(), dl,
640 TII->get(Mips::PHI), MI->getOperand(0).getReg())
641 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
642 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
644 BuildMI(*BB, BB->begin(), dl,
645 TII->get(Mips::PHI), MI->getOperand(0).getReg())
646 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
647 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
649 MI->eraseFromParent(); // The pseudo instruction is gone now.
653 //===----------------------------------------------------------------------===//
654 // Misc Lower Operation implementation
655 //===----------------------------------------------------------------------===//
657 SDValue MipsTargetLowering::
658 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
660 if (!Subtarget->isMips1())
663 MachineFunction &MF = DAG.getMachineFunction();
664 unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
666 SDValue Chain = DAG.getEntryNode();
667 DebugLoc dl = Op.getDebugLoc();
668 SDValue Src = Op.getOperand(0);
670 // Set the condition register
671 SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
672 CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
673 CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
675 SDValue Cst = DAG.getConstant(3, MVT::i32);
676 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
677 Cst = DAG.getConstant(2, MVT::i32);
678 SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
680 SDValue InFlag(0, 0);
681 CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
683 // Emit the round instruction and bit convert to integer
684 SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
685 Src, CondReg.getValue(1));
686 SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
690 SDValue MipsTargetLowering::
691 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
693 SDValue Chain = Op.getOperand(0);
694 SDValue Size = Op.getOperand(1);
695 DebugLoc dl = Op.getDebugLoc();
697 // Get a reference from Mips stack pointer
698 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
700 // Subtract the dynamic size from the actual stack size to
701 // obtain the new stack size.
702 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
704 // The Sub result contains the new stack start address, so it
705 // must be placed in the stack pointer register.
706 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
708 // This node always has two return values: a new stack pointer
710 SDValue Ops[2] = { Sub, Chain };
711 return DAG.getMergeValues(Ops, 2, dl);
714 SDValue MipsTargetLowering::
715 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
717 // The first operand is the chain, the second is the condition, the third is
718 // the block to branch to if the condition is true.
719 SDValue Chain = Op.getOperand(0);
720 SDValue Dest = Op.getOperand(2);
721 DebugLoc dl = Op.getDebugLoc();
723 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
725 // Return if flag is not set by a floating point comparison.
726 if (CondRes.getOpcode() != MipsISD::FPCmp)
729 SDValue CCNode = CondRes.getOperand(2);
731 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
732 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
734 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
738 SDValue MipsTargetLowering::
739 LowerSELECT(SDValue Op, SelectionDAG &DAG) const
741 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
743 // Return if flag is not set by a floating point comparison.
744 if (Cond.getOpcode() != MipsISD::FPCmp)
747 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
751 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
752 SelectionDAG &DAG) const {
753 // FIXME there isn't actually debug info here
754 DebugLoc dl = Op.getDebugLoc();
755 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
757 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
758 SDVTList VTs = DAG.getVTList(MVT::i32);
760 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
762 // %gp_rel relocation
763 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
764 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
766 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
767 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
768 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
770 // %hi/%lo relocation
771 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
773 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
775 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
776 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
777 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
779 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
781 SDValue ResNode = DAG.getLoad(MVT::i32, dl,
782 DAG.getEntryNode(), GA, MachinePointerInfo(),
784 // On functions and global targets not internal linked only
785 // a load from got/GP is necessary for PIC to work.
786 if (!GV->hasInternalLinkage() &&
787 (!GV->hasLocalLinkage() || isa<Function>(GV)))
789 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
791 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
792 return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
795 llvm_unreachable("Dont know how to handle GlobalAddress");
799 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
800 SelectionDAG &DAG) const {
801 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
802 // FIXME there isn't actually debug info here
803 DebugLoc dl = Op.getDebugLoc();
805 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
806 // %hi/%lo relocation
807 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true,
809 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true,
811 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
812 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
813 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
816 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true,
818 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true,
820 SDValue Load = DAG.getLoad(MVT::i32, dl,
821 DAG.getEntryNode(), BAGOTOffset,
822 MachinePointerInfo(), false, false, 0);
823 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset);
824 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
827 SDValue MipsTargetLowering::
828 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
830 llvm_unreachable("TLS not implemented for MIPS.");
831 return SDValue(); // Not reached
834 SDValue MipsTargetLowering::
835 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
839 // FIXME there isn't actually debug info here
840 DebugLoc dl = Op.getDebugLoc();
841 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
842 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI;
844 EVT PtrVT = Op.getValueType();
845 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
847 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
850 SDValue Ops[] = { JTI };
851 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
852 } else // Emit Load from Global Pointer
853 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
854 MachinePointerInfo(),
857 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
859 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo);
860 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
865 SDValue MipsTargetLowering::
866 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
869 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
870 const Constant *C = N->getConstVal();
871 // FIXME there isn't actually debug info here
872 DebugLoc dl = Op.getDebugLoc();
875 // FIXME: we should reference the constant pool using small data sections,
876 // but the asm printer currently doesn't support this feature without
877 // hacking it. This feature should come soon so we can uncomment the
879 //if (IsInSmallSection(C->getType())) {
880 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
881 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
882 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
884 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
885 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
886 N->getOffset(), MipsII::MO_ABS_HI);
887 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
888 N->getOffset(), MipsII::MO_ABS_LO);
889 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
890 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
891 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
893 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
894 N->getOffset(), MipsII::MO_GOT);
895 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
896 CP, MachinePointerInfo::getConstantPool(),
898 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
899 N->getOffset(), MipsII::MO_ABS_LO);
900 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
901 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
907 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
908 MachineFunction &MF = DAG.getMachineFunction();
909 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
911 DebugLoc dl = Op.getDebugLoc();
912 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
915 // vastart just stores the address of the VarArgsFrameIndex slot into the
916 // memory location argument.
917 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
918 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
919 MachinePointerInfo(SV),
923 //===----------------------------------------------------------------------===//
924 // Calling Convention Implementation
925 //===----------------------------------------------------------------------===//
927 #include "MipsGenCallingConv.inc"
929 //===----------------------------------------------------------------------===//
930 // TODO: Implement a generic logic using tblgen that can support this.
931 // Mips O32 ABI rules:
933 // i32 - Passed in A0, A1, A2, A3 and stack
934 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
935 // an argument. Otherwise, passed in A1, A2, A3 and stack.
936 // f64 - Only passed in two aliased f32 registers if no int reg has been used
937 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
938 // not used, it must be shadowed. If only A3 is avaiable, shadow it and
941 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
942 //===----------------------------------------------------------------------===//
944 static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
945 MVT LocVT, CCValAssign::LocInfo LocInfo,
946 ISD::ArgFlagsTy ArgFlags, CCState &State) {
948 static const unsigned IntRegsSize=4, FloatRegsSize=2;
950 static const unsigned IntRegs[] = {
951 Mips::A0, Mips::A1, Mips::A2, Mips::A3
953 static const unsigned F32Regs[] = {
956 static const unsigned F64Regs[] = {
960 // Promote i8 and i16
961 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
963 if (ArgFlags.isSExt())
964 LocInfo = CCValAssign::SExt;
965 else if (ArgFlags.isZExt())
966 LocInfo = CCValAssign::ZExt;
968 LocInfo = CCValAssign::AExt;
973 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
974 // is true: function is vararg, argument is 3rd or higher, there is previous
975 // argument which is not f32 or f64.
976 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
977 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
979 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
980 Reg = State.AllocateReg(IntRegs, IntRegsSize);
982 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
983 // Allocate int register and shadow next int register. If first
984 // available register is Mips::A1 or Mips::A3, shadow it too.
985 Reg = State.AllocateReg(IntRegs, IntRegsSize);
986 if (Reg == Mips::A1 || Reg == Mips::A3)
987 Reg = State.AllocateReg(IntRegs, IntRegsSize);
988 State.AllocateReg(IntRegs, IntRegsSize);
990 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
991 // we are guaranteed to find an available float register
992 if (ValVT == MVT::f32) {
993 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
994 // Shadow int register
995 State.AllocateReg(IntRegs, IntRegsSize);
997 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
998 // Shadow int registers
999 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
1000 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
1001 State.AllocateReg(IntRegs, IntRegsSize);
1002 State.AllocateReg(IntRegs, IntRegsSize);
1005 llvm_unreachable("Cannot handle this ValVT.");
1008 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
1009 unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
1010 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
1012 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1014 return false; // CC must always match
1017 //===----------------------------------------------------------------------===//
1018 // Call Calling Convention Implementation
1019 //===----------------------------------------------------------------------===//
1021 /// LowerCall - functions arguments are copied from virtual regs to
1022 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
1023 /// TODO: isTailCall.
1025 MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1026 CallingConv::ID CallConv, bool isVarArg,
1028 const SmallVectorImpl<ISD::OutputArg> &Outs,
1029 const SmallVectorImpl<SDValue> &OutVals,
1030 const SmallVectorImpl<ISD::InputArg> &Ins,
1031 DebugLoc dl, SelectionDAG &DAG,
1032 SmallVectorImpl<SDValue> &InVals) const {
1033 // MIPs target does not yet support tail call optimization.
1036 MachineFunction &MF = DAG.getMachineFunction();
1037 MachineFrameInfo *MFI = MF.getFrameInfo();
1038 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1040 // Analyze operands of the call, assigning locations to each operand.
1041 SmallVector<CCValAssign, 16> ArgLocs;
1042 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1045 // To meet O32 ABI, Mips must always allocate 16 bytes on
1046 // the stack (even if less than 4 are used as arguments)
1047 if (Subtarget->isABI_O32()) {
1048 int VTsize = MVT(MVT::i32).getSizeInBits()/8;
1049 MFI->CreateFixedObject(VTsize, (VTsize*3), true);
1050 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
1052 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
1054 // Get a count of how many bytes are to be pushed on the stack.
1055 unsigned NumBytes = CCInfo.getNextStackOffset();
1056 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1058 // With EABI is it possible to have 16 args on registers.
1059 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
1060 SmallVector<SDValue, 8> MemOpChains;
1062 // First/LastArgStackLoc contains the first/last
1063 // "at stack" argument location.
1064 int LastArgStackLoc = 0;
1065 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1067 // Walk the register/memloc assignments, inserting copies/loads.
1068 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1069 SDValue Arg = OutVals[i];
1070 CCValAssign &VA = ArgLocs[i];
1072 // Promote the value if needed.
1073 switch (VA.getLocInfo()) {
1074 default: llvm_unreachable("Unknown loc info!");
1075 case CCValAssign::Full:
1076 if (Subtarget->isABI_O32() && VA.isRegLoc()) {
1077 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
1078 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1079 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
1080 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1081 Arg, DAG.getConstant(0, MVT::i32));
1082 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
1083 Arg, DAG.getConstant(1, MVT::i32));
1084 if (!Subtarget->isLittle())
1086 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
1087 RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
1092 case CCValAssign::SExt:
1093 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1095 case CCValAssign::ZExt:
1096 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1098 case CCValAssign::AExt:
1099 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1103 // Arguments that can be passed on register must be kept at
1104 // RegsToPass vector
1105 if (VA.isRegLoc()) {
1106 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1110 // Register can't get to this point...
1111 assert(VA.isMemLoc());
1113 // Create the frame index object for this incoming parameter
1114 // This guarantees that when allocating Local Area the firsts
1115 // 16 bytes which are alwayes reserved won't be overwritten
1116 // if O32 ABI is used. For EABI the first address is zero.
1117 LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
1118 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1119 LastArgStackLoc, true);
1121 SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
1123 // emit ISD::STORE whichs stores the
1124 // parameter value to a stack Location
1125 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
1126 MachinePointerInfo(),
1130 // Transform all store nodes into one single node because all store
1131 // nodes are independent of each other.
1132 if (!MemOpChains.empty())
1133 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1134 &MemOpChains[0], MemOpChains.size());
1136 // Build a sequence of copy-to-reg nodes chained together with token
1137 // chain and flag operands which copy the outgoing args into registers.
1138 // The InFlag in necessary since all emitted instructions must be
1141 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1142 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1143 RegsToPass[i].second, InFlag);
1144 InFlag = Chain.getValue(1);
1147 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1148 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1149 // node so that legalize doesn't hack it.
1150 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
1151 bool LoadSymAddr = false;
1154 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1155 if (IsPIC && G->getGlobal()->hasInternalLinkage()) {
1156 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1157 getPointerTy(), 0,MipsII:: MO_GOT);
1158 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
1159 0, MipsII::MO_ABS_LO);
1161 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
1162 getPointerTy(), 0, OpFlag);
1167 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1168 Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
1169 getPointerTy(), OpFlag);
1173 // Create nodes that load address of callee and copy it to T9
1176 // Load callee address
1177 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee,
1178 MachinePointerInfo::getGOT(),
1181 // Use GOT+LO if callee has internal linkage.
1182 if (CalleeLo.getNode()) {
1183 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo);
1184 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
1188 // Use chain output from LoadValue
1189 Chain = LoadValue.getValue(1);
1193 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
1194 InFlag = Chain.getValue(1);
1195 Callee = DAG.getRegister(Mips::T9, MVT::i32);
1198 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
1199 // = Chain, Callee, Reg#1, Reg#2, ...
1201 // Returns a chain & a flag for retval copy to use.
1202 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1203 SmallVector<SDValue, 8> Ops;
1204 Ops.push_back(Chain);
1205 Ops.push_back(Callee);
1207 // Add argument registers to the end of the list so that they are
1208 // known live into the call.
1209 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1210 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1211 RegsToPass[i].second.getValueType()));
1213 if (InFlag.getNode())
1214 Ops.push_back(InFlag);
1216 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
1217 InFlag = Chain.getValue(1);
1219 // Create a stack location to hold GP when PIC is used. This stack
1220 // location is used on function prologue to save GP and also after all
1221 // emitted CALL's to restore GP.
1223 // Function can have an arbitrary number of calls, so
1224 // hold the LastArgStackLoc with the biggest offset.
1226 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1227 if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
1228 LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
1229 // Create the frame index only once. SPOffset here can be anything
1230 // (this will be fixed on processFunctionBeforeFrameFinalized)
1231 if (MipsFI->getGPStackOffset() == -1) {
1232 FI = MFI->CreateFixedObject(4, 0, true);
1233 MipsFI->setGPFI(FI);
1235 MipsFI->setGPStackOffset(LastArgStackLoc);
1239 // Create the CALLSEQ_END node.
1240 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1241 DAG.getIntPtrConstant(0, true), InFlag);
1242 InFlag = Chain.getValue(1);
1244 // Handle result values, copying them out of physregs into vregs that we
1246 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1247 Ins, dl, DAG, InVals);
1250 /// LowerCallResult - Lower the result values of a call into the
1251 /// appropriate copies out of appropriate physical registers.
1253 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1254 CallingConv::ID CallConv, bool isVarArg,
1255 const SmallVectorImpl<ISD::InputArg> &Ins,
1256 DebugLoc dl, SelectionDAG &DAG,
1257 SmallVectorImpl<SDValue> &InVals) const {
1259 // Assign locations to each value returned by this call.
1260 SmallVector<CCValAssign, 16> RVLocs;
1261 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1262 RVLocs, *DAG.getContext());
1264 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
1266 // Copy all of the result registers out of their specified physreg.
1267 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1268 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1269 RVLocs[i].getValVT(), InFlag).getValue(1);
1270 InFlag = Chain.getValue(2);
1271 InVals.push_back(Chain.getValue(0));
1277 //===----------------------------------------------------------------------===//
1278 // Formal Arguments Calling Convention Implementation
1279 //===----------------------------------------------------------------------===//
1281 /// LowerFormalArguments - transform physical registers into virtual registers
1282 /// and generate load operations for arguments places on the stack.
1284 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
1285 CallingConv::ID CallConv,
1287 const SmallVectorImpl<ISD::InputArg>
1289 DebugLoc dl, SelectionDAG &DAG,
1290 SmallVectorImpl<SDValue> &InVals)
1293 MachineFunction &MF = DAG.getMachineFunction();
1294 MachineFrameInfo *MFI = MF.getFrameInfo();
1295 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1297 MipsFI->setVarArgsFrameIndex(0);
1299 // Used with vargs to acumulate store chains.
1300 std::vector<SDValue> OutChains;
1302 // Keep track of the last register used for arguments
1303 unsigned ArgRegEnd = 0;
1305 // Assign locations to all of the incoming arguments.
1306 SmallVector<CCValAssign, 16> ArgLocs;
1307 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1308 ArgLocs, *DAG.getContext());
1310 if (Subtarget->isABI_O32())
1311 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
1313 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
1315 unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
1316 unsigned LastStackArgEndOffset = 0;
1317 EVT LastRegArgValVT;
1319 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1320 CCValAssign &VA = ArgLocs[i];
1322 // Arguments stored on registers
1323 if (VA.isRegLoc()) {
1324 EVT RegVT = VA.getLocVT();
1325 ArgRegEnd = VA.getLocReg();
1326 LastRegArgValVT = VA.getValVT();
1327 TargetRegisterClass *RC = 0;
1329 if (RegVT == MVT::i32)
1330 RC = Mips::CPURegsRegisterClass;
1331 else if (RegVT == MVT::f32)
1332 RC = Mips::FGR32RegisterClass;
1333 else if (RegVT == MVT::f64) {
1334 if (!Subtarget->isSingleFloat())
1335 RC = Mips::AFGR64RegisterClass;
1337 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
1339 // Transform the arguments stored on
1340 // physical registers into virtual ones
1341 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1342 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1344 // If this is an 8 or 16-bit value, it has been passed promoted
1345 // to 32 bits. Insert an assert[sz]ext to capture this, then
1346 // truncate to the right size.
1347 if (VA.getLocInfo() != CCValAssign::Full) {
1348 unsigned Opcode = 0;
1349 if (VA.getLocInfo() == CCValAssign::SExt)
1350 Opcode = ISD::AssertSext;
1351 else if (VA.getLocInfo() == CCValAssign::ZExt)
1352 Opcode = ISD::AssertZext;
1354 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
1355 DAG.getValueType(VA.getValVT()));
1356 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1359 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
1360 if (Subtarget->isABI_O32()) {
1361 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
1362 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
1363 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
1364 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
1365 VA.getLocReg()+1, RC);
1366 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
1367 if (!Subtarget->isLittle())
1368 std::swap(ArgValue, ArgValue2);
1369 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
1370 ArgValue, ArgValue2);
1374 InVals.push_back(ArgValue);
1375 } else { // VA.isRegLoc()
1378 assert(VA.isMemLoc());
1380 // The last argument is not a register anymore
1383 // The stack pointer offset is relative to the caller stack frame.
1384 // Since the real stack size is unknown here, a negative SPOffset
1385 // is used so there's a way to adjust these offsets when the stack
1386 // size get known (on EliminateFrameIndex). A dummy SPOffset is
1387 // used instead of a direct negative address (which is recorded to
1388 // be used on emitPrologue) to avoid mis-calc of the first stack
1389 // offset on PEI::calculateFrameObjectOffsets.
1390 unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
1391 LastStackArgEndOffset = FirstStackArgLoc + VA.getLocMemOffset() + ArgSize;
1392 int FI = MFI->CreateFixedObject(ArgSize, 0, true);
1393 MipsFI->recordLoadArgsFI(FI, -(4 +
1394 (FirstStackArgLoc + VA.getLocMemOffset())));
1396 // Create load nodes to retrieve arguments from the stack
1397 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1398 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1399 MachinePointerInfo::getFixedStack(FI),
1404 // The mips ABIs for returning structs by value requires that we copy
1405 // the sret argument into $v0 for the return. Save the argument into
1406 // a virtual register so that we can access it from the return points.
1407 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1408 unsigned Reg = MipsFI->getSRetReturnReg();
1410 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
1411 MipsFI->setSRetReturnReg(Reg);
1413 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1414 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1417 // To meet ABI, when VARARGS are passed on registers, the registers
1418 // must have their values written to the caller stack frame. If the last
1419 // argument was placed in the stack, there's no need to save any register.
1420 if (isVarArg && Subtarget->isABI_O32()) {
1422 // Last named formal argument is passed in register.
1424 // The last register argument that must be saved is Mips::A3
1425 TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
1426 if (LastRegArgValVT == MVT::f64)
1429 if (ArgRegEnd < Mips::A3) {
1430 // Both the last named formal argument and the first variable
1431 // argument are passed in registers.
1432 for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd) {
1433 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
1434 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
1436 int FI = MFI->CreateFixedObject(4, 0, true);
1437 MipsFI->recordStoreVarArgsFI(FI, -(4+(ArgRegEnd-Mips::A0)*4));
1438 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
1439 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
1440 MachinePointerInfo(),
1443 // Record the frame index of the first variable argument
1444 // which is a value necessary to VASTART.
1445 if (!MipsFI->getVarArgsFrameIndex()) {
1446 MFI->setObjectAlignment(FI, 4);
1447 MipsFI->setVarArgsFrameIndex(FI);
1451 // Last named formal argument is in register Mips::A3, and the first
1452 // variable argument is on stack. Record the frame index of the first
1453 // variable argument.
1454 int FI = MFI->CreateFixedObject(4, 0, true);
1455 MFI->setObjectAlignment(FI, 4);
1456 MipsFI->recordStoreVarArgsFI(FI, -20);
1457 MipsFI->setVarArgsFrameIndex(FI);
1460 // Last named formal argument and all the variable arguments are passed
1461 // on stack. Record the frame index of the first variable argument.
1462 int FI = MFI->CreateFixedObject(4, 0, true);
1463 MFI->setObjectAlignment(FI, 4);
1464 MipsFI->recordStoreVarArgsFI(FI, -(4+LastStackArgEndOffset));
1465 MipsFI->setVarArgsFrameIndex(FI);
1469 // All stores are grouped in one node to allow the matching between
1470 // the size of Ins and InVals. This only happens when on varg functions
1471 if (!OutChains.empty()) {
1472 OutChains.push_back(Chain);
1473 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1474 &OutChains[0], OutChains.size());
1480 //===----------------------------------------------------------------------===//
1481 // Return Value Calling Convention Implementation
1482 //===----------------------------------------------------------------------===//
1485 MipsTargetLowering::LowerReturn(SDValue Chain,
1486 CallingConv::ID CallConv, bool isVarArg,
1487 const SmallVectorImpl<ISD::OutputArg> &Outs,
1488 const SmallVectorImpl<SDValue> &OutVals,
1489 DebugLoc dl, SelectionDAG &DAG) const {
1491 // CCValAssign - represent the assignment of
1492 // the return value to a location
1493 SmallVector<CCValAssign, 16> RVLocs;
1495 // CCState - Info about the registers and stack slot.
1496 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1497 RVLocs, *DAG.getContext());
1499 // Analize return values.
1500 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
1502 // If this is the first return lowered for this function, add
1503 // the regs to the liveout set for the function.
1504 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1505 for (unsigned i = 0; i != RVLocs.size(); ++i)
1506 if (RVLocs[i].isRegLoc())
1507 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1512 // Copy the result values into the output registers.
1513 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1514 CCValAssign &VA = RVLocs[i];
1515 assert(VA.isRegLoc() && "Can only return in registers!");
1517 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1520 // guarantee that all emitted copies are
1521 // stuck together, avoiding something bad
1522 Flag = Chain.getValue(1);
1525 // The mips ABIs for returning structs by value requires that we copy
1526 // the sret argument into $v0 for the return. We saved the argument into
1527 // a virtual register in the entry block, so now we copy the value out
1529 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1530 MachineFunction &MF = DAG.getMachineFunction();
1531 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
1532 unsigned Reg = MipsFI->getSRetReturnReg();
1535 llvm_unreachable("sret virtual register not created in the entry block");
1536 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1538 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
1539 Flag = Chain.getValue(1);
1542 // Return on Mips is always a "jr $ra"
1544 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1545 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
1547 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
1548 Chain, DAG.getRegister(Mips::RA, MVT::i32));
1551 //===----------------------------------------------------------------------===//
1552 // Mips Inline Assembly Support
1553 //===----------------------------------------------------------------------===//
1555 /// getConstraintType - Given a constraint letter, return the type of
1556 /// constraint it is for this target.
1557 MipsTargetLowering::ConstraintType MipsTargetLowering::
1558 getConstraintType(const std::string &Constraint) const
1560 // Mips specific constrainy
1561 // GCC config/mips/constraints.md
1563 // 'd' : An address register. Equivalent to r
1564 // unless generating MIPS16 code.
1565 // 'y' : Equivalent to r; retained for
1566 // backwards compatibility.
1567 // 'f' : Floating Point registers.
1568 if (Constraint.size() == 1) {
1569 switch (Constraint[0]) {
1574 return C_RegisterClass;
1578 return TargetLowering::getConstraintType(Constraint);
1581 /// Examine constraint type and operand type and determine a weight value.
1582 /// This object must already have been set up with the operand type
1583 /// and the current alternative constraint selected.
1584 TargetLowering::ConstraintWeight
1585 MipsTargetLowering::getSingleConstraintMatchWeight(
1586 AsmOperandInfo &info, const char *constraint) const {
1587 ConstraintWeight weight = CW_Invalid;
1588 Value *CallOperandVal = info.CallOperandVal;
1589 // If we don't have a value, we can't do a match,
1590 // but allow it at the lowest weight.
1591 if (CallOperandVal == NULL)
1593 const Type *type = CallOperandVal->getType();
1594 // Look at the constraint type.
1595 switch (*constraint) {
1597 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
1601 if (type->isIntegerTy())
1602 weight = CW_Register;
1605 if (type->isFloatTy())
1606 weight = CW_Register;
1612 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1613 /// return a list of registers that can be used to satisfy the constraint.
1614 /// This should only be used for C_RegisterClass constraints.
1615 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
1616 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
1618 if (Constraint.size() == 1) {
1619 switch (Constraint[0]) {
1621 return std::make_pair(0U, Mips::CPURegsRegisterClass);
1624 return std::make_pair(0U, Mips::FGR32RegisterClass);
1626 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1627 return std::make_pair(0U, Mips::AFGR64RegisterClass);
1630 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1633 /// Given a register class constraint, like 'r', if this corresponds directly
1634 /// to an LLVM register class, return a register of 0 and the register class
1636 std::vector<unsigned> MipsTargetLowering::
1637 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1640 if (Constraint.size() != 1)
1641 return std::vector<unsigned>();
1643 switch (Constraint[0]) {
1646 // GCC Mips Constraint Letters
1649 return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
1650 Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
1651 Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
1655 if (VT == MVT::f32) {
1656 if (Subtarget->isSingleFloat())
1657 return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
1658 Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
1659 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
1660 Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
1661 Mips::F30, Mips::F31, 0);
1663 return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
1664 Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
1665 Mips::F28, Mips::F30, 0);
1669 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
1670 return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
1671 Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
1672 Mips::D14, Mips::D15, 0);
1674 return std::vector<unsigned>();
1678 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1679 // The Mips target isn't yet aware of offsets.
1683 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
1684 if (VT != MVT::f32 && VT != MVT::f64)
1686 if (Imm.isNegZero())
1688 return Imm.isZero();