1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsISelLowering.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/GlobalValue.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
39 //===----------------------------------------------------------------------===//
40 // Instruction Selector Implementation
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
44 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
45 // instructions for SelectionDAG operations.
46 //===----------------------------------------------------------------------===//
49 class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
51 /// TM - Keep a reference to MipsTargetMachine.
52 MipsTargetMachine &TM;
54 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
55 /// make the right decision when generating code for different targets.
56 const MipsSubtarget &Subtarget;
59 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
61 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
63 virtual void InstructionSelect();
66 virtual const char *getPassName() const {
67 return "MIPS DAG->DAG Pattern Instruction Selection";
72 // Include the pieces autogenerated from the target description.
73 #include "MipsGenDAGISel.inc"
75 /// getTargetMachine - Return a reference to the TargetMachine, casted
76 /// to the target-specific type.
77 const MipsTargetMachine &getTargetMachine() {
78 return static_cast<const MipsTargetMachine &>(TM);
81 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
82 /// to the target-specific type.
83 const MipsInstrInfo *getInstrInfo() {
84 return getTargetMachine().getInstrInfo();
87 SDNode *getGlobalBaseReg();
88 SDNode *Select(SDValue N);
91 bool SelectAddr(SDValue Op, SDValue N,
92 SDValue &Base, SDValue &Offset);
95 // getI32Imm - Return a target constant with the specified
96 // value, of type i32.
97 inline SDValue getI32Imm(unsigned Imm) {
98 return CurDAG->getTargetConstant(Imm, MVT::i32);
109 /// InstructionSelect - This callback is invoked by
110 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
111 void MipsDAGToDAGISel::
115 // Codegen the basic block.
117 DOUT << "===== Instruction selection begins:\n";
121 // Select target instructions for the DAG.
125 DOUT << "===== Instruction selection ends:\n";
128 CurDAG->RemoveDeadNodes();
131 /// getGlobalBaseReg - Output the instructions required to put the
132 /// GOT address into a register.
133 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
134 MachineFunction *MF = BB->getParent();
135 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
136 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
139 /// ComplexPattern used on MipsInstrInfo
140 /// Used on Mips Load/Store instructions
141 bool MipsDAGToDAGISel::
142 SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base)
144 // if Address is FI, get the TargetFrameIndex.
145 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
146 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
147 Offset = CurDAG->getTargetConstant(0, MVT::i32);
151 // on PIC code Load GA
152 if (TM.getRelocationModel() == Reloc::PIC_) {
153 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
154 (Addr.getOpcode() == ISD::TargetJumpTable)){
155 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
160 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
161 Addr.getOpcode() == ISD::TargetGlobalAddress))
165 // Operand is a result from an ADD.
166 if (Addr.getOpcode() == ISD::ADD) {
167 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
168 if (Predicate_immSExt16(CN)) {
170 // If the first operand is a FI, get the TargetFI Node
171 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
172 (Addr.getOperand(0))) {
173 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
175 Base = Addr.getOperand(0);
178 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
185 Offset = CurDAG->getTargetConstant(0, MVT::i32);
189 /// Select instructions not customized! Used for
190 /// expanded, promoted and normal instructions
191 SDNode* MipsDAGToDAGISel::
194 SDNode *Node = N.getNode();
195 unsigned Opcode = Node->getOpcode();
196 DebugLoc dl = Node->getDebugLoc();
198 // Dump information about the Node being selected
200 DOUT << std::string(Indent, ' ') << "Selecting: ";
201 DEBUG(Node->dump(CurDAG));
206 // If we have a custom node, we already have selected!
207 if (Node->isMachineOpcode()) {
209 DOUT << std::string(Indent-2, ' ') << "== ";
210 DEBUG(Node->dump(CurDAG));
218 // Instruction Selection not handled by the auto-generated
219 // tablegen selection should be handled here.
227 SDValue InFlag = Node->getOperand(2), CmpLHS;
228 unsigned Opc = InFlag.getOpcode(); Opc=Opc;
229 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
230 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
231 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
234 if (Opcode == ISD::ADDE) {
235 CmpLHS = InFlag.getValue(0);
238 CmpLHS = InFlag.getOperand(0);
242 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
244 SDValue LHS = Node->getOperand(0);
245 SDValue RHS = Node->getOperand(1);
247 MVT VT = LHS.getValueType();
248 SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, dl, VT, Ops, 2);
249 SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT,
250 SDValue(Carry,0), RHS);
252 return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag,
253 LHS, SDValue(AddCarry,0));
256 /// Mul/Div with two results
260 case ISD::UMUL_LOHI: {
261 SDValue Op1 = Node->getOperand(0);
262 SDValue Op2 = Node->getOperand(1);
265 if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
266 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
268 Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
270 SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
272 SDValue InFlag = SDValue(Node, 0);
273 SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32,
275 InFlag = SDValue(Lo,1);
276 SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
278 if (!N.getValue(0).use_empty())
279 ReplaceUses(N.getValue(0), SDValue(Lo,0));
281 if (!N.getValue(1).use_empty())
282 ReplaceUses(N.getValue(1), SDValue(Hi,0));
291 SDValue MulOp1 = Node->getOperand(0);
292 SDValue MulOp2 = Node->getOperand(1);
294 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
295 SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl,
296 MVT::Flag, MulOp1, MulOp2);
298 SDValue InFlag = SDValue(MulNode, 0);
300 if (MulOp == ISD::MUL)
301 return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag);
303 return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag);
306 /// Div/Rem operations
311 SDValue Op1 = Node->getOperand(0);
312 SDValue Op2 = Node->getOperand(1);
315 if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
316 Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
319 Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
322 SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2);
324 SDValue InFlag = SDValue(Node, 0);
325 return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag);
328 // Get target GOT address.
329 case ISD::GLOBAL_OFFSET_TABLE:
330 return getGlobalBaseReg();
332 /// Handle direct and indirect calls when using PIC. On PIC, when
333 /// GOT is smaller than about 64k (small code) the GA target is
334 /// loaded with only one instruction. Otherwise GA's target must
335 /// be loaded with 3 instructions.
336 case MipsISD::JmpLink: {
337 if (TM.getRelocationModel() == Reloc::PIC_) {
338 //bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large);
339 SDValue Chain = Node->getOperand(0);
340 SDValue Callee = Node->getOperand(1);
341 SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32);
342 SDValue InFlag(0, 0);
344 if ( (isa<GlobalAddressSDNode>(Callee)) ||
345 (isa<ExternalSymbolSDNode>(Callee)) )
347 /// Direct call for global addresses and external symbols
348 SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
350 // Use load to get GOT target
351 SDValue Ops[] = { Callee, GPReg, Chain };
352 SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32,
353 MVT::Other, Ops, 3), 0);
354 Chain = Load.getValue(1);
356 // Call target must be on T9
357 Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Load, InFlag);
360 Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag);
362 // Emit Jump and Link Register
363 SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other,
364 MVT::Flag, T9Reg, Chain);
365 Chain = SDValue(ResNode, 0);
366 InFlag = SDValue(ResNode, 1);
367 ReplaceUses(SDValue(Node, 0), Chain);
368 ReplaceUses(SDValue(Node, 1), InFlag);
374 // Select the default instruction
375 SDNode *ResNode = SelectCode(N);
378 DOUT << std::string(Indent-2, ' ') << "=> ";
379 if (ResNode == NULL || ResNode == N.getNode())
380 DEBUG(N.getNode()->dump(CurDAG));
382 DEBUG(ResNode->dump(CurDAG));
390 /// createMipsISelDag - This pass converts a legalized DAG into a
391 /// MIPS-specific DAG, ready for instruction scheduling.
392 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
393 return new MipsDAGToDAGISel(TM);