1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
87 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
89 SDNode *SelectLoadFp64(SDNode *N);
90 SDNode *SelectStoreFp64(SDNode *N);
92 // getI32Imm - Return a target constant with the specified
93 // value, of type i32.
94 inline SDValue getI32Imm(unsigned Imm) {
95 return CurDAG->getTargetConstant(Imm, MVT::i32);
102 /// getGlobalBaseReg - Output the instructions required to put the
103 /// GOT address into a register.
104 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
105 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
106 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
109 /// ComplexPattern used on MipsInstrInfo
110 /// Used on Mips Load/Store instructions
111 bool MipsDAGToDAGISel::
112 SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
113 // if Address is FI, get the TargetFrameIndex.
114 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
115 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
116 Offset = CurDAG->getTargetConstant(0, MVT::i32);
120 // on PIC code Load GA
121 if (TM.getRelocationModel() == Reloc::PIC_) {
122 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
123 (Addr.getOpcode() == ISD::TargetConstantPool) ||
124 (Addr.getOpcode() == ISD::TargetJumpTable)){
125 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
130 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
131 Addr.getOpcode() == ISD::TargetGlobalAddress))
135 // Operand is a result from an ADD.
136 if (Addr.getOpcode() == ISD::ADD) {
137 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
138 if (isInt<16>(CN->getSExtValue())) {
140 // If the first operand is a FI, get the TargetFI Node
141 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
142 (Addr.getOperand(0))) {
143 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
145 Base = Addr.getOperand(0);
148 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
153 // When loading from constant pools, load the lower address part in
154 // the instruction itself. Example, instead of:
155 // lui $2, %hi($CPI1_0)
156 // addiu $2, $2, %lo($CPI1_0)
159 // lui $2, %hi($CPI1_0)
160 // lwc1 $f0, %lo($CPI1_0)($2)
161 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
162 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
163 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
164 SDValue LoVal = Addr.getOperand(1);
165 if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
166 Base = Addr.getOperand(0);
167 Offset = LoVal.getOperand(0);
174 Offset = CurDAG->getTargetConstant(0, MVT::i32);
178 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
179 MVT::SimpleValueType NVT =
180 N->getValueType(0).getSimpleVT().SimpleTy;
182 if (!Subtarget.isMips1() || NVT != MVT::f64)
185 LoadSDNode *LN = cast<LoadSDNode>(N);
186 if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
187 LN->getAddressingMode() != ISD::UNINDEXED)
190 SDValue Chain = N->getOperand(0);
191 SDValue N1 = N->getOperand(1);
192 SDValue Offset0, Offset1, Base;
194 if (!SelectAddr(N1, Offset0, Base) ||
195 N1.getValueType() != MVT::i32)
198 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
199 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
200 DebugLoc dl = N->getDebugLoc();
202 // The second load should start after for 4 bytes.
203 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
204 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
205 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
206 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
210 CP->getTargetFlags());
214 // Choose the offsets depending on the endianess
215 if (TM.getTargetData()->isBigEndian())
216 std::swap(Offset0, Offset1);
223 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
224 MVT::Other, Offset0, Base, Chain);
225 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
227 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
228 MVT::f64, Undef, SDValue(LD0, 0));
230 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
231 MVT::Other, Offset1, Base, SDValue(LD0, 1));
232 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
233 MVT::f64, I0, SDValue(LD1, 0));
235 ReplaceUses(SDValue(N, 0), I1);
236 ReplaceUses(SDValue(N, 1), Chain);
237 cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
238 cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
242 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
244 if (!Subtarget.isMips1() ||
245 N->getOperand(1).getValueType() != MVT::f64)
248 SDValue Chain = N->getOperand(0);
250 StoreSDNode *SN = cast<StoreSDNode>(N);
251 if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
254 SDValue N1 = N->getOperand(1);
255 SDValue N2 = N->getOperand(2);
256 SDValue Offset0, Offset1, Base;
258 if (!SelectAddr(N2, Offset0, Base) ||
259 N1.getValueType() != MVT::f64 ||
260 N2.getValueType() != MVT::i32)
263 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
264 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
265 DebugLoc dl = N->getDebugLoc();
267 // Get the even and odd part from the f64 register
268 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
270 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
273 // The second store should start after for 4 bytes.
274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
275 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
279 // Choose the offsets depending on the endianess
280 if (TM.getTargetData()->isBigEndian())
281 std::swap(Offset0, Offset1);
288 SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
289 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
290 MVT::Other, Ops0, 4), 0);
291 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
293 SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
294 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
295 MVT::Other, Ops1, 4), 0);
296 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
298 ReplaceUses(SDValue(N, 0), Chain);
299 return Chain.getNode();
302 /// Select instructions not customized! Used for
303 /// expanded, promoted and normal instructions
304 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
305 unsigned Opcode = Node->getOpcode();
306 DebugLoc dl = Node->getDebugLoc();
308 // Dump information about the Node being selected
309 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
311 // If we have a custom node, we already have selected!
312 if (Node->isMachineOpcode()) {
313 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
318 // Instruction Selection not handled by the auto-generated
319 // tablegen selection should be handled here.
327 SDValue InFlag = Node->getOperand(2), CmpLHS;
328 unsigned Opc = InFlag.getOpcode(); Opc=Opc;
329 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
330 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
331 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
334 if (Opcode == ISD::ADDE) {
335 CmpLHS = InFlag.getValue(0);
338 CmpLHS = InFlag.getOperand(0);
342 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
344 SDValue LHS = Node->getOperand(0);
345 SDValue RHS = Node->getOperand(1);
347 EVT VT = LHS.getValueType();
348 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
349 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
350 SDValue(Carry,0), RHS);
352 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Flag,
353 LHS, SDValue(AddCarry,0));
356 /// Mul/Div with two results
360 case ISD::UMUL_LOHI: {
361 SDValue Op1 = Node->getOperand(0);
362 SDValue Op2 = Node->getOperand(1);
365 if (Opcode == ISD::UMUL_LOHI || Opcode == ISD::SMUL_LOHI)
366 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
368 Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV);
370 SDNode *MulDiv = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
372 SDValue InFlag = SDValue(MulDiv, 0);
373 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
375 InFlag = SDValue(Lo,1);
376 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
378 if (!SDValue(Node, 0).use_empty())
379 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
381 if (!SDValue(Node, 1).use_empty())
382 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
389 if (Subtarget.isMips32())
393 SDValue MulOp1 = Node->getOperand(0);
394 SDValue MulOp2 = Node->getOperand(1);
396 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
397 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
398 MVT::Flag, MulOp1, MulOp2);
400 SDValue InFlag = SDValue(MulNode, 0);
402 if (Opcode == ISD::MUL)
403 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
405 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
408 /// Div/Rem operations
413 SDValue Op1 = Node->getOperand(0);
414 SDValue Op2 = Node->getOperand(1);
417 if (Opcode == ISD::SDIV || Opcode == ISD::UDIV) {
418 Op = (Opcode == ISD::SDIV ? Mips::DIV : Mips::DIVu);
421 Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu);
424 SDNode *Node = CurDAG->getMachineNode(Op, dl, MVT::Flag, Op1, Op2);
426 SDValue InFlag = SDValue(Node, 0);
427 return CurDAG->getMachineNode(MOp, dl, MVT::i32, InFlag);
430 // Get target GOT address.
431 case ISD::GLOBAL_OFFSET_TABLE:
432 return getGlobalBaseReg();
434 case ISD::ConstantFP: {
435 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
436 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
437 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
438 Mips::ZERO, MVT::i32);
439 SDValue Undef = SDValue(
440 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
441 SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
442 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
443 MVT::f64, Undef, SDValue(MTC, 0));
444 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
445 MVT::f64, I0, SDValue(MTC, 0));
446 ReplaceUses(SDValue(Node, 0), I1);
453 if (SDNode *ResNode = SelectLoadFp64(Node))
455 // Other cases are autogenerated.
459 if (SDNode *ResNode = SelectStoreFp64(Node))
461 // Other cases are autogenerated.
464 /// Handle direct and indirect calls when using PIC. On PIC, when
465 /// GOT is smaller than about 64k (small code) the GA target is
466 /// loaded with only one instruction. Otherwise GA's target must
467 /// be loaded with 3 instructions.
468 case MipsISD::JmpLink: {
469 if (TM.getRelocationModel() == Reloc::PIC_) {
470 unsigned LastOpNum = Node->getNumOperands()-1;
472 SDValue Chain = Node->getOperand(0);
473 SDValue Callee = Node->getOperand(1);
476 // Skip the incomming flag if present
477 if (Node->getOperand(LastOpNum).getValueType() == MVT::Flag)
480 if ( (isa<GlobalAddressSDNode>(Callee)) ||
481 (isa<ExternalSymbolSDNode>(Callee)) )
483 /// Direct call for global addresses and external symbols
484 SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
486 // Use load to get GOT target
487 SDValue Ops[] = { Callee, GPReg, Chain };
488 SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
489 MVT::Other, Ops, 3), 0);
490 Chain = Load.getValue(1);
492 // Call target must be on T9
493 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
496 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
498 // Map the JmpLink operands to JALR
499 SDVTList NodeTys = CurDAG->getVTList(MVT::Other, MVT::Flag);
500 SmallVector<SDValue, 8> Ops;
501 Ops.push_back(CurDAG->getRegister(Mips::T9, MVT::i32));
503 for (unsigned i = 2, e = LastOpNum+1; i != e; ++i)
504 Ops.push_back(Node->getOperand(i));
505 Ops.push_back(Chain);
506 Ops.push_back(Chain.getValue(1));
508 // Emit Jump and Link Register
509 SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
510 &Ops[0], Ops.size());
512 // Replace Chain and InFlag
513 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
514 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
520 // Select the default instruction
521 SDNode *ResNode = SelectCode(Node);
523 DEBUG(errs() << "=> ");
524 if (ResNode == NULL || ResNode == Node)
525 DEBUG(Node->dump(CurDAG));
527 DEBUG(ResNode->dump(CurDAG));
528 DEBUG(errs() << "\n");
532 /// createMipsISelDag - This pass converts a legalized DAG into a
533 /// MIPS-specific DAG, ready for instruction scheduling.
534 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
535 return new MipsDAGToDAGISel(TM);