1 //===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MIPS target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mips-isel"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsSubtarget.h"
19 #include "MipsTargetMachine.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/Support/CFG.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGISel.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
37 //===----------------------------------------------------------------------===//
38 // Instruction Selector Implementation
39 //===----------------------------------------------------------------------===//
41 //===----------------------------------------------------------------------===//
42 // MipsDAGToDAGISel - MIPS specific code to select MIPS machine
43 // instructions for SelectionDAG operations.
44 //===----------------------------------------------------------------------===//
47 class MipsDAGToDAGISel : public SelectionDAGISel {
49 /// TM - Keep a reference to MipsTargetMachine.
50 MipsTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const MipsSubtarget &Subtarget;
57 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
62 virtual const char *getPassName() const {
63 return "MIPS DAG->DAG Pattern Instruction Selection";
68 // Include the pieces autogenerated from the target description.
69 #include "MipsGenDAGISel.inc"
71 /// getTargetMachine - Return a reference to the TargetMachine, casted
72 /// to the target-specific type.
73 const MipsTargetMachine &getTargetMachine() {
74 return static_cast<const MipsTargetMachine &>(TM);
77 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
78 /// to the target-specific type.
79 const MipsInstrInfo *getInstrInfo() {
80 return getTargetMachine().getInstrInfo();
83 SDNode *getGlobalBaseReg();
84 SDNode *Select(SDNode *N);
87 bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
89 SDNode *SelectLoadFp64(SDNode *N);
90 SDNode *SelectStoreFp64(SDNode *N);
92 // getI32Imm - Return a target constant with the specified
93 // value, of type i32.
94 inline SDValue getI32Imm(unsigned Imm) {
95 return CurDAG->getTargetConstant(Imm, MVT::i32);
102 /// getGlobalBaseReg - Output the instructions required to put the
103 /// GOT address into a register.
104 SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
105 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
106 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
109 /// ComplexPattern used on MipsInstrInfo
110 /// Used on Mips Load/Store instructions
111 bool MipsDAGToDAGISel::
112 SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
113 // if Address is FI, get the TargetFrameIndex.
114 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
115 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
116 Offset = CurDAG->getTargetConstant(0, MVT::i32);
120 // on PIC code Load GA
121 if (TM.getRelocationModel() == Reloc::PIC_) {
122 if (Addr.getOpcode() == MipsISD::WrapperPIC) {
123 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
124 Offset = Addr.getOperand(0);
128 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
129 Addr.getOpcode() == ISD::TargetGlobalAddress))
133 // Operand is a result from an ADD.
134 if (Addr.getOpcode() == ISD::ADD) {
135 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
136 if (isInt<16>(CN->getSExtValue())) {
138 // If the first operand is a FI, get the TargetFI Node
139 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
140 (Addr.getOperand(0))) {
141 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
143 Base = Addr.getOperand(0);
146 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
151 // When loading from constant pools, load the lower address part in
152 // the instruction itself. Example, instead of:
153 // lui $2, %hi($CPI1_0)
154 // addiu $2, $2, %lo($CPI1_0)
157 // lui $2, %hi($CPI1_0)
158 // lwc1 $f0, %lo($CPI1_0)($2)
159 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
160 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
161 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
162 SDValue LoVal = Addr.getOperand(1);
163 if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
164 Base = Addr.getOperand(0);
165 Offset = LoVal.getOperand(0);
172 Offset = CurDAG->getTargetConstant(0, MVT::i32);
176 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
177 MVT::SimpleValueType NVT =
178 N->getValueType(0).getSimpleVT().SimpleTy;
180 if (!Subtarget.isMips1() || NVT != MVT::f64)
183 LoadSDNode *LN = cast<LoadSDNode>(N);
184 if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
185 LN->getAddressingMode() != ISD::UNINDEXED)
188 SDValue Chain = N->getOperand(0);
189 SDValue N1 = N->getOperand(1);
190 SDValue Offset0, Offset1, Base;
192 if (!SelectAddr(N1, Offset0, Base) ||
193 N1.getValueType() != MVT::i32)
196 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
197 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
198 DebugLoc dl = N->getDebugLoc();
200 // The second load should start after for 4 bytes.
201 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
202 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
203 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
204 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
208 CP->getTargetFlags());
212 // Choose the offsets depending on the endianess
213 if (TM.getTargetData()->isBigEndian())
214 std::swap(Offset0, Offset1);
221 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
222 MVT::Other, Offset0, Base, Chain);
223 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
225 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
226 MVT::f64, Undef, SDValue(LD0, 0));
228 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
229 MVT::Other, Offset1, Base, SDValue(LD0, 1));
230 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
231 MVT::f64, I0, SDValue(LD1, 0));
233 ReplaceUses(SDValue(N, 0), I1);
234 ReplaceUses(SDValue(N, 1), Chain);
235 cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
236 cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
240 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
242 if (!Subtarget.isMips1() ||
243 N->getOperand(1).getValueType() != MVT::f64)
246 SDValue Chain = N->getOperand(0);
248 StoreSDNode *SN = cast<StoreSDNode>(N);
249 if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
252 SDValue N1 = N->getOperand(1);
253 SDValue N2 = N->getOperand(2);
254 SDValue Offset0, Offset1, Base;
256 if (!SelectAddr(N2, Offset0, Base) ||
257 N1.getValueType() != MVT::f64 ||
258 N2.getValueType() != MVT::i32)
261 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
262 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
263 DebugLoc dl = N->getDebugLoc();
265 // Get the even and odd part from the f64 register
266 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
268 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
271 // The second store should start after for 4 bytes.
272 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
273 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
277 // Choose the offsets depending on the endianess
278 if (TM.getTargetData()->isBigEndian())
279 std::swap(Offset0, Offset1);
286 SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
287 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
288 MVT::Other, Ops0, 4), 0);
289 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
291 SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
292 Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
293 MVT::Other, Ops1, 4), 0);
294 cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
296 ReplaceUses(SDValue(N, 0), Chain);
297 return Chain.getNode();
300 /// Select instructions not customized! Used for
301 /// expanded, promoted and normal instructions
302 SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
303 unsigned Opcode = Node->getOpcode();
304 DebugLoc dl = Node->getDebugLoc();
306 // Dump information about the Node being selected
307 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
309 // If we have a custom node, we already have selected!
310 if (Node->isMachineOpcode()) {
311 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
316 // Instruction Selection not handled by the auto-generated
317 // tablegen selection should be handled here.
325 SDValue InFlag = Node->getOperand(2), CmpLHS;
326 unsigned Opc = InFlag.getOpcode(); (void)Opc;
327 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
328 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
329 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
332 if (Opcode == ISD::ADDE) {
333 CmpLHS = InFlag.getValue(0);
336 CmpLHS = InFlag.getOperand(0);
340 SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
342 SDValue LHS = Node->getOperand(0);
343 SDValue RHS = Node->getOperand(1);
345 EVT VT = LHS.getValueType();
346 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
347 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
348 SDValue(Carry,0), RHS);
350 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
351 LHS, SDValue(AddCarry,0));
354 /// Mul/Div with two results
359 case ISD::UMUL_LOHI: {
360 SDValue Op1 = Node->getOperand(0);
361 SDValue Op2 = Node->getOperand(1);
364 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
366 SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
368 SDValue InFlag = SDValue(Mul, 0);
369 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
371 InFlag = SDValue(Lo,1);
372 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
374 if (!SDValue(Node, 0).use_empty())
375 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
377 if (!SDValue(Node, 1).use_empty())
378 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
385 if (Subtarget.isMips32())
389 SDValue MulOp1 = Node->getOperand(0);
390 SDValue MulOp2 = Node->getOperand(1);
392 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
393 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
394 MVT::Glue, MulOp1, MulOp2);
396 SDValue InFlag = SDValue(MulNode, 0);
398 if (Opcode == ISD::MUL)
399 return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
401 return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
404 /// Div/Rem operations
411 // Get target GOT address.
412 case ISD::GLOBAL_OFFSET_TABLE:
413 return getGlobalBaseReg();
415 case ISD::ConstantFP: {
416 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
417 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
418 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
419 Mips::ZERO, MVT::i32);
420 SDValue Undef = SDValue(
421 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
422 SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
423 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
424 MVT::f64, Undef, SDValue(MTC, 0));
425 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
426 MVT::f64, I0, SDValue(MTC, 0));
427 ReplaceUses(SDValue(Node, 0), I1);
434 if (SDNode *ResNode = SelectLoadFp64(Node))
436 // Other cases are autogenerated.
440 if (SDNode *ResNode = SelectStoreFp64(Node))
442 // Other cases are autogenerated.
446 // Select the default instruction
447 SDNode *ResNode = SelectCode(Node);
449 DEBUG(errs() << "=> ");
450 if (ResNode == NULL || ResNode == Node)
451 DEBUG(Node->dump(CurDAG));
453 DEBUG(ResNode->dump(CurDAG));
454 DEBUG(errs() << "\n");
458 /// createMipsISelDag - This pass converts a legalized DAG into a
459 /// MIPS-specific DAG, ready for instruction scheduling.
460 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
461 return new MipsDAGToDAGISel(TM);