1 //=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "MipsFrameLowering.h"
15 #include "MipsInstrInfo.h"
16 #include "MipsMachineFunction.h"
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Support/CommandLine.h"
31 //===----------------------------------------------------------------------===//
33 // Stack Frame Processing methods
34 // +----------------------------+
36 // The stack is allocated decrementing the stack pointer on
37 // the first instruction of a function prologue. Once decremented,
38 // all stack references are done thought a positive offset
39 // from the stack/frame pointer, so the stack is considering
40 // to grow up! Otherwise terrible hacks would have to be made
41 // to get this stack ABI compliant :)
43 // The stack frame required by the ABI (after call):
48 // . saved $GP (used in PIC)
49 // . Alloca allocations
51 // . CPU "Callee Saved" Registers
54 // . FPU "Callee Saved" Registers
55 // StackSize -----------
57 // Offset - offset from sp after stack allocation on function prologue
59 // The sp is the stack pointer subtracted/added from the stack size
60 // at the Prologue/Epilogue
62 // References to the previous stack (to obtain arguments) are done
63 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
66 // - reference to the actual stack frame
67 // for any local area var there is smt like : FI >= 0, StackOffset: 4
70 // - reference to previous stack frame
71 // suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
72 // The emitted instruction will be something like:
73 // lw REGX, 16+StackSize(SP)
75 // Since the total stack size is unknown on LowerFormalArguments, all
76 // stack references (ObjectOffset) created to reference the function
77 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
78 // possible to detect those references and the offsets are adjusted to
79 // their real location.
81 //===----------------------------------------------------------------------===//
83 // hasFP - Return true if the specified function should have a dedicated frame
84 // pointer register. This is true if the function has variable sized allocas or
85 // if frame pointer elimination is disabled.
86 bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
87 const MachineFrameInfo *MFI = MF.getFrameInfo();
88 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()
89 || MFI->isFrameAddressTaken();
92 bool MipsFrameLowering::targetHandlesStackFrameRounding() const {
96 static unsigned AlignOffset(unsigned Offset, unsigned Align) {
97 return (Offset + Align - 1) / Align * Align;
100 // expand pair of register and immediate if the immediate doesn't fit in the
101 // 16-bit offset field.
103 // if OrigImm = 0x10000, OrigReg = $sp:
104 // generate the following sequence of instrs:
105 // lui $at, hi(0x10000)
106 // addu $at, $sp, $at
108 // (NewReg, NewImm) = ($at, lo(Ox10000))
110 static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm,
111 unsigned& NewReg, int& NewImm,
112 MachineBasicBlock& MBB,
113 MachineBasicBlock::iterator I) {
114 // OrigImm fits in the 16-bit field
115 if (OrigImm < 0x8000 && OrigImm >= -0x8000) {
121 MachineFunction* MF = MBB.getParent();
122 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
123 DebugLoc DL = I->getDebugLoc();
124 int ImmLo = (short)(OrigImm & 0xffff);
125 int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) +
126 ((OrigImm & 0x8000) != 0);
128 // FIXME: change this when mips goes MC".
129 BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
130 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
131 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
139 void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
140 MachineBasicBlock &MBB = MF.front();
141 MachineFrameInfo *MFI = MF.getFrameInfo();
142 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
143 const MipsRegisterInfo *RegInfo =
144 static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
145 const MipsInstrInfo &TII =
146 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
147 MachineBasicBlock::iterator MBBI = MBB.begin();
148 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
149 bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
153 unsigned GP = STI.isABI_N64() ? Mips::GP_64 : Mips::GP;
154 unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
155 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
156 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
157 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
159 // First, compute final stack size.
160 unsigned RegSize = STI.isGP32bit() ? 4 : 8;
161 unsigned StackAlign = getStackAlignment();
162 unsigned LocalVarAreaOffset = MipsFI->needGPSaveRestore() ?
163 (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) :
164 MipsFI->getMaxCallFrameSize();
165 unsigned StackSize = AlignOffset(LocalVarAreaOffset, StackAlign) +
166 AlignOffset(MipsFI->getRegSaveAreaSize(), StackAlign) +
167 AlignOffset(MFI->getStackSize(), StackAlign);
170 MFI->setStackSize(StackSize);
172 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
174 // Emit instructions that set $gp using the the value of $t9.
175 // O32 uses the directive .cpload while N32/64 requires three instructions to
177 // TODO: Do not emit these instructions if no instructions use $gp.
178 if (isPIC && STI.isABI_O32())
179 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
180 .addReg(RegInfo->getPICCallReg());
181 else if (STI.isABI_N64() || (isPIC && STI.isABI_N32())) {
182 // lui $28,%hi(%neg(%gp_rel(fname)))
184 // addiu $28,$28,%lo(%neg(%gp_rel(fname)))
185 const GlobalValue *FName = MF.getFunction();
186 BuildMI(MBB, MBBI, dl, TII.get(LUi), GP)
187 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
188 BuildMI(MBB, MBBI, dl, TII.get(ADDu), GP).addReg(GP).addReg(T9);
189 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), GP).addReg(GP)
190 .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
193 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
195 // No need to allocate space on the stack.
196 if (StackSize == 0 && !MFI->adjustsStack()) return;
198 MachineModuleInfo &MMI = MF.getMMI();
199 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
200 MachineLocation DstML, SrcML;
202 // Adjust stack : addi sp, sp, (-imm)
203 ATUsed = expandRegLargeImmPair(Mips::SP, -StackSize, NewReg, NewImm, MBB,
205 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
206 .addReg(NewReg).addImm(NewImm);
208 // FIXME: change this when mips goes MC".
210 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
212 // emit ".cfi_def_cfa_offset StackSize"
213 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
214 BuildMI(MBB, MBBI, dl,
215 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
216 DstML = MachineLocation(MachineLocation::VirtualFP);
217 SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
218 Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
220 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
223 // Find the instruction past the last instruction that saves a callee-saved
224 // register to the stack.
225 for (unsigned i = 0; i < CSI.size(); ++i)
228 // Iterate over list of callee-saved registers and emit .cfi_offset
230 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
231 BuildMI(MBB, MBBI, dl,
232 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
234 for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
235 E = CSI.end(); I != E; ++I) {
236 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
237 unsigned Reg = I->getReg();
239 // If Reg is a double precision register, emit two cfa_offsets,
240 // one for each of the paired single precision registers.
241 if (Mips::AFGR64RegisterClass->contains(Reg)) {
242 const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
243 MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
244 MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
245 MachineLocation SrcML0(*SubRegs);
246 MachineLocation SrcML1(*(SubRegs + 1));
249 std::swap(SrcML0, SrcML1);
251 Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
252 Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
255 // Reg is either in CPURegs or FGR32.
256 DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
257 SrcML = MachineLocation(Reg);
258 Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
263 // if framepointer enabled, set it to point to the stack pointer.
265 // Insert instruction "move $fp, $sp" at this location.
266 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
267 .addReg(Mips::SP).addReg(Mips::ZERO);
269 // emit ".cfi_def_cfa_register $fp"
270 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
271 BuildMI(MBB, MBBI, dl,
272 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
273 DstML = MachineLocation(Mips::FP);
274 SrcML = MachineLocation(MachineLocation::VirtualFP);
275 Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
278 // Restore GP from the saved stack location
279 if (MipsFI->needGPSaveRestore()) {
280 unsigned Offset = MFI->getObjectOffset(MipsFI->getGPFI());
281 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)).addImm(Offset);
283 if (Offset >= 0x8000) {
284 BuildMI(MBB, llvm::prior(MBBI), dl, TII.get(Mips::MACRO));
285 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
290 void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
291 MachineBasicBlock &MBB) const {
292 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
293 MachineFrameInfo *MFI = MF.getFrameInfo();
294 const MipsInstrInfo &TII =
295 *static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
296 DebugLoc dl = MBBI->getDebugLoc();
298 // Get the number of bytes from FrameInfo
299 unsigned StackSize = MFI->getStackSize();
305 // if framepointer enabled, restore the stack pointer.
307 // Find the first instruction that restores a callee-saved register.
308 MachineBasicBlock::iterator I = MBBI;
310 for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
313 // Insert instruction "move $sp, $fp" at this location.
314 BuildMI(MBB, I, dl, TII.get(Mips::ADDu), Mips::SP)
315 .addReg(Mips::FP).addReg(Mips::ZERO);
318 // adjust stack : insert addi sp, sp, (imm)
320 ATUsed = expandRegLargeImmPair(Mips::SP, StackSize, NewReg, NewImm, MBB,
322 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
323 .addReg(NewReg).addImm(NewImm);
325 // FIXME: change this when mips goes MC".
327 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO));
331 void MipsFrameLowering::
332 processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
333 RegScavenger *RS) const {
334 MachineRegisterInfo& MRI = MF.getRegInfo();
336 // FIXME: remove this code if register allocator can correctly mark
337 // $fp and $ra used or unused.
339 // Mark $fp and $ra as used or unused.
341 MRI.setPhysRegUsed(Mips::FP);
343 // The register allocator might determine $ra is used after seeing
344 // instruction "jr $ra", but we do not want PrologEpilogInserter to insert
345 // instructions to save/restore $ra unless there is a function call.
346 // To correct this, $ra is explicitly marked unused if there is no
348 if (MF.getFrameInfo()->hasCalls())
349 MRI.setPhysRegUsed(Mips::RA);
351 MRI.setPhysRegUnused(Mips::RA);