1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "llvm/CodeGen/FunctionLoweringInfo.h"
5 #include "MipsCCState.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/MachineInstrBuilder.h"
14 #include "llvm/IR/GlobalAlias.h"
15 #include "llvm/IR/GlobalVariable.h"
16 #include "llvm/Target/TargetInstrInfo.h"
22 class MipsFastISel final : public FastISel {
24 // All possible address modes.
27 typedef enum { RegBase, FrameIndexBase } BaseKind;
38 const GlobalValue *GV;
41 // Innocuous defaults for our address.
42 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
43 void setKind(BaseKind K) { Kind = K; }
44 BaseKind getKind() const { return Kind; }
45 bool isRegBase() const { return Kind == RegBase; }
46 void setReg(unsigned Reg) {
47 assert(isRegBase() && "Invalid base register access!");
50 unsigned getReg() const {
51 assert(isRegBase() && "Invalid base register access!");
54 void setOffset(int64_t Offset_) { Offset = Offset_; }
55 int64_t getOffset() const { return Offset; }
56 void setGlobalValue(const GlobalValue *G) { GV = G; }
57 const GlobalValue *getGlobalValue() { return GV; }
60 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
61 /// make the right decision when generating code for different targets.
62 const TargetMachine &TM;
63 const MipsSubtarget *Subtarget;
64 const TargetInstrInfo &TII;
65 const TargetLowering &TLI;
66 MipsFunctionInfo *MFI;
68 // Convenience variables to avoid some queries.
71 bool fastLowerCall(CallLoweringInfo &CLI) override;
74 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
75 // floating point but not reject doing fast-isel in other
79 // Selection routines.
80 bool selectLoad(const Instruction *I);
81 bool selectStore(const Instruction *I);
82 bool selectBranch(const Instruction *I);
83 bool selectCmp(const Instruction *I);
84 bool selectFPExt(const Instruction *I);
85 bool selectFPTrunc(const Instruction *I);
86 bool selectFPToInt(const Instruction *I, bool IsSigned);
87 bool selectRet(const Instruction *I);
88 bool selectTrunc(const Instruction *I);
89 bool selectIntExt(const Instruction *I);
91 // Utility helper routines.
92 bool isTypeLegal(Type *Ty, MVT &VT);
93 bool isLoadTypeLegal(Type *Ty, MVT &VT);
94 bool computeAddress(const Value *Obj, Address &Addr);
95 bool computeCallAddress(const Value *V, Address &Addr);
97 // Emit helper routines.
98 bool emitCmp(unsigned DestReg, const CmpInst *CI);
99 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
100 unsigned Alignment = 0);
101 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
102 MachineMemOperand *MMO = nullptr);
103 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
104 unsigned Alignment = 0);
105 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
106 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
109 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
111 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
112 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
114 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
117 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
119 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
120 unsigned materializeGV(const GlobalValue *GV, MVT VT);
121 unsigned materializeInt(const Constant *C, MVT VT);
122 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
124 MachineInstrBuilder emitInst(unsigned Opc) {
125 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
127 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
128 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
131 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
132 unsigned MemReg, int64_t MemOffset) {
133 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
135 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
136 unsigned MemReg, int64_t MemOffset) {
137 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
139 // for some reason, this default is not generated by tablegen
140 // so we explicitly generate it here.
142 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
143 unsigned Op0, bool Op0IsKill, uint64_t imm1,
144 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
148 // Call handling routines.
150 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
151 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
153 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
156 // Backend specific FastISel code.
157 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
158 const TargetLibraryInfo *libInfo)
159 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
161 &static_cast<const MipsSubtarget &>(funcInfo.MF->getSubtarget())),
162 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
163 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
164 Context = &funcInfo.Fn->getContext();
166 ((TM.getRelocationModel() == Reloc::PIC_) &&
167 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
168 (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
169 UnsupportedFPMode = Subtarget->isFP64bit();
172 unsigned fastMaterializeConstant(const Constant *C) override;
173 bool fastSelectInstruction(const Instruction *I) override;
175 #include "MipsGenFastISel.inc"
177 } // end anonymous namespace.
179 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
180 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
181 CCState &State) LLVM_ATTRIBUTE_UNUSED;
183 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
184 CCValAssign::LocInfo LocInfo,
185 ISD::ArgFlagsTy ArgFlags, CCState &State) {
186 llvm_unreachable("should not be called");
189 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
190 CCValAssign::LocInfo LocInfo,
191 ISD::ArgFlagsTy ArgFlags, CCState &State) {
192 llvm_unreachable("should not be called");
195 #include "MipsGenCallingConv.inc"
197 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
201 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
202 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
204 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
205 const ConstantInt *CI = cast<ConstantInt>(C);
207 if ((VT != MVT::i1) && CI->isNegative())
208 Imm = CI->getSExtValue();
210 Imm = CI->getZExtValue();
211 return materialize32BitInt(Imm, RC);
214 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
215 const TargetRegisterClass *RC) {
216 unsigned ResultReg = createResultReg(RC);
218 if (isInt<16>(Imm)) {
219 unsigned Opc = Mips::ADDiu;
220 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
222 } else if (isUInt<16>(Imm)) {
223 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
226 unsigned Lo = Imm & 0xFFFF;
227 unsigned Hi = (Imm >> 16) & 0xFFFF;
229 // Both Lo and Hi have nonzero bits.
230 unsigned TmpReg = createResultReg(RC);
231 emitInst(Mips::LUi, TmpReg).addImm(Hi);
232 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
234 emitInst(Mips::LUi, ResultReg).addImm(Hi);
239 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
240 if (UnsupportedFPMode)
242 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
243 if (VT == MVT::f32) {
244 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
245 unsigned DestReg = createResultReg(RC);
246 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
247 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
249 } else if (VT == MVT::f64) {
250 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
251 unsigned DestReg = createResultReg(RC);
252 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
254 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
255 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
261 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
262 // For now 32-bit only.
265 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
266 unsigned DestReg = createResultReg(RC);
267 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
268 bool IsThreadLocal = GVar && GVar->isThreadLocal();
269 // TLS not supported at this time.
272 emitInst(Mips::LW, DestReg)
273 .addReg(MFI->getGlobalBaseReg())
274 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
275 if ((GV->hasInternalLinkage() ||
276 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
277 unsigned TempReg = createResultReg(RC);
278 emitInst(Mips::ADDiu, TempReg)
280 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
286 // Materialize a constant into a register, and return the register
287 // number (or zero if we failed to handle it).
288 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
289 EVT CEVT = TLI.getValueType(C->getType(), true);
291 // Only handle simple types.
292 if (!CEVT.isSimple())
294 MVT VT = CEVT.getSimpleVT();
296 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
297 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
298 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
299 return materializeGV(GV, VT);
300 else if (isa<ConstantInt>(C))
301 return materializeInt(C, VT);
306 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
307 // This construct looks a big awkward but it is how other ports handle this
308 // and as this function is more fully completed, these cases which
309 // return false will have additional code in them.
311 if (isa<Instruction>(Obj))
313 else if (isa<ConstantExpr>(Obj))
315 Addr.setReg(getRegForValue(Obj));
316 return Addr.getReg() != 0;
319 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
320 const GlobalValue *GV = dyn_cast<GlobalValue>(V);
321 if (GV && isa<Function>(GV) && dyn_cast<Function>(GV)->isIntrinsic())
325 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
326 Addr.setGlobalValue(GV);
332 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
333 EVT evt = TLI.getValueType(Ty, true);
334 // Only handle simple types.
335 if (evt == MVT::Other || !evt.isSimple())
337 VT = evt.getSimpleVT();
339 // Handle all legal types, i.e. a register that will directly hold this
341 return TLI.isTypeLegal(VT);
344 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
345 if (isTypeLegal(Ty, VT))
347 // We will extend this in a later patch:
348 // If this is a type than can be sign or zero-extended to a basic operation
349 // go ahead and accept it now.
350 if (VT == MVT::i8 || VT == MVT::i16)
354 // Because of how EmitCmp is called with fast-isel, you can
355 // end up with redundant "andi" instructions after the sequences emitted below.
356 // We should try and solve this issue in the future.
358 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
359 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
360 bool IsUnsigned = CI->isUnsigned();
361 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
364 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
367 CmpInst::Predicate P = CI->getPredicate();
372 case CmpInst::ICMP_EQ: {
373 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
374 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
375 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
378 case CmpInst::ICMP_NE: {
379 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
380 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
381 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
384 case CmpInst::ICMP_UGT: {
385 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
388 case CmpInst::ICMP_ULT: {
389 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
392 case CmpInst::ICMP_UGE: {
393 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
394 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
395 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
398 case CmpInst::ICMP_ULE: {
399 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
400 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
401 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
404 case CmpInst::ICMP_SGT: {
405 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
408 case CmpInst::ICMP_SLT: {
409 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
412 case CmpInst::ICMP_SGE: {
413 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
414 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
415 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
418 case CmpInst::ICMP_SLE: {
419 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
420 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
421 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
424 case CmpInst::FCMP_OEQ:
425 case CmpInst::FCMP_UNE:
426 case CmpInst::FCMP_OLT:
427 case CmpInst::FCMP_OLE:
428 case CmpInst::FCMP_OGT:
429 case CmpInst::FCMP_OGE: {
430 if (UnsupportedFPMode)
432 bool IsFloat = Left->getType()->isFloatTy();
433 bool IsDouble = Left->getType()->isDoubleTy();
434 if (!IsFloat && !IsDouble)
436 unsigned Opc, CondMovOpc;
438 case CmpInst::FCMP_OEQ:
439 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
440 CondMovOpc = Mips::MOVT_I;
442 case CmpInst::FCMP_UNE:
443 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
444 CondMovOpc = Mips::MOVF_I;
446 case CmpInst::FCMP_OLT:
447 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
448 CondMovOpc = Mips::MOVT_I;
450 case CmpInst::FCMP_OLE:
451 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
452 CondMovOpc = Mips::MOVT_I;
454 case CmpInst::FCMP_OGT:
455 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
456 CondMovOpc = Mips::MOVF_I;
458 case CmpInst::FCMP_OGE:
459 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
460 CondMovOpc = Mips::MOVF_I;
463 llvm_unreachable("Only switching of a subset of CCs.");
465 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
466 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
467 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
468 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
469 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
470 Mips::FCC0, RegState::ImplicitDefine);
471 MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
474 .addReg(RegWithZero, RegState::Implicit);
475 MI->tieOperands(0, 3);
481 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
482 unsigned Alignment) {
484 // more cases will be handled here in following patches.
487 switch (VT.SimpleTy) {
489 ResultReg = createResultReg(&Mips::GPR32RegClass);
494 ResultReg = createResultReg(&Mips::GPR32RegClass);
499 ResultReg = createResultReg(&Mips::GPR32RegClass);
504 if (UnsupportedFPMode)
506 ResultReg = createResultReg(&Mips::FGR32RegClass);
511 if (UnsupportedFPMode)
513 ResultReg = createResultReg(&Mips::AFGR64RegClass);
520 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
524 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
525 unsigned Alignment) {
527 // more cases will be handled here in following patches.
530 switch (VT.SimpleTy) {
541 if (UnsupportedFPMode)
546 if (UnsupportedFPMode)
553 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
557 bool MipsFastISel::selectLoad(const Instruction *I) {
558 // Atomic loads need special handling.
559 if (cast<LoadInst>(I)->isAtomic())
562 // Verify we have a legal type before going any further.
564 if (!isLoadTypeLegal(I->getType(), VT))
567 // See if we can handle this address.
569 if (!computeAddress(I->getOperand(0), Addr))
573 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
575 updateValueMap(I, ResultReg);
579 bool MipsFastISel::selectStore(const Instruction *I) {
580 Value *Op0 = I->getOperand(0);
583 // Atomic stores need special handling.
584 if (cast<StoreInst>(I)->isAtomic())
587 // Verify we have a legal type before going any further.
589 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
592 // Get the value to be stored into a register.
593 SrcReg = getRegForValue(Op0);
597 // See if we can handle this address.
599 if (!computeAddress(I->getOperand(1), Addr))
602 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
608 // This can cause a redundant sltiu to be generated.
609 // FIXME: try and eliminate this in a future patch.
611 bool MipsFastISel::selectBranch(const Instruction *I) {
612 const BranchInst *BI = cast<BranchInst>(I);
613 MachineBasicBlock *BrBB = FuncInfo.MBB;
615 // TBB is the basic block for the case where the comparison is true.
616 // FBB is the basic block for the case where the comparison is false.
617 // if (cond) goto TBB
621 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
622 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
624 // For now, just try the simplest case where it's fed by a compare.
625 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
626 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
627 if (!emitCmp(CondReg, CI))
629 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
632 fastEmitBranch(FBB, DbgLoc);
633 FuncInfo.MBB->addSuccessor(TBB);
639 bool MipsFastISel::selectCmp(const Instruction *I) {
640 const CmpInst *CI = cast<CmpInst>(I);
641 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
642 if (!emitCmp(ResultReg, CI))
644 updateValueMap(I, ResultReg);
648 // Attempt to fast-select a floating-point extend instruction.
649 bool MipsFastISel::selectFPExt(const Instruction *I) {
650 if (UnsupportedFPMode)
652 Value *Src = I->getOperand(0);
653 EVT SrcVT = TLI.getValueType(Src->getType(), true);
654 EVT DestVT = TLI.getValueType(I->getType(), true);
656 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
660 getRegForValue(Src); // his must be a 32 bit floating point register class
661 // maybe we should handle this differently
665 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
666 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
667 updateValueMap(I, DestReg);
671 // Attempt to fast-select a floating-point truncate instruction.
672 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
673 if (UnsupportedFPMode)
675 Value *Src = I->getOperand(0);
676 EVT SrcVT = TLI.getValueType(Src->getType(), true);
677 EVT DestVT = TLI.getValueType(I->getType(), true);
679 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
682 unsigned SrcReg = getRegForValue(Src);
686 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
690 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
691 updateValueMap(I, DestReg);
695 // Attempt to fast-select a floating-point-to-integer conversion.
696 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
697 if (UnsupportedFPMode)
701 return false; // We don't handle this case yet. There is no native
702 // instruction for this but it can be synthesized.
703 Type *DstTy = I->getType();
704 if (!isTypeLegal(DstTy, DstVT))
707 if (DstVT != MVT::i32)
710 Value *Src = I->getOperand(0);
711 Type *SrcTy = Src->getType();
712 if (!isTypeLegal(SrcTy, SrcVT))
715 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
718 unsigned SrcReg = getRegForValue(Src);
722 // Determine the opcode for the conversion, which takes place
723 // entirely within FPRs.
724 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
725 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
728 if (SrcVT == MVT::f32)
729 Opc = Mips::TRUNC_W_S;
731 Opc = Mips::TRUNC_W_D32;
733 // Generate the convert.
734 emitInst(Opc, TempReg).addReg(SrcReg);
736 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
738 updateValueMap(I, DestReg);
742 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
743 SmallVectorImpl<MVT> &OutVTs,
744 unsigned &NumBytes) {
745 CallingConv::ID CC = CLI.CallConv;
746 SmallVector<CCValAssign, 16> ArgLocs;
747 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
748 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
749 // Get a count of how many bytes are to be pushed on the stack.
750 NumBytes = CCInfo.getNextStackOffset();
751 // This is the minimum argument area used for A0-A3.
755 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
758 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
759 CCValAssign &VA = ArgLocs[i];
760 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
761 MVT ArgVT = OutVTs[VA.getValNo()];
765 if (ArgVT == MVT::f32) {
766 VA.convertToReg(Mips::F12);
767 } else if (ArgVT == MVT::f64) {
768 VA.convertToReg(Mips::D6);
771 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
772 if (ArgVT == MVT::f32) {
773 VA.convertToReg(Mips::F14);
774 } else if (ArgVT == MVT::f64) {
775 VA.convertToReg(Mips::D7);
779 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) {
780 switch (VA.getLocMemOffset()) {
782 VA.convertToReg(Mips::A0);
785 VA.convertToReg(Mips::A1);
788 VA.convertToReg(Mips::A2);
791 VA.convertToReg(Mips::A3);
797 unsigned ArgReg = getRegForValue(ArgVal);
801 // Handle arg promotion: SExt, ZExt, AExt.
802 switch (VA.getLocInfo()) {
803 case CCValAssign::Full:
805 case CCValAssign::AExt:
806 case CCValAssign::SExt: {
807 MVT DestVT = VA.getLocVT();
809 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
814 case CCValAssign::ZExt: {
815 MVT DestVT = VA.getLocVT();
817 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
823 llvm_unreachable("Unknown arg promotion!");
826 // Now copy/store arg to correct locations.
827 if (VA.isRegLoc() && !VA.needsCustom()) {
828 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
829 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
830 CLI.OutRegs.push_back(VA.getLocReg());
831 } else if (VA.needsCustom()) {
832 llvm_unreachable("Mips does not use custom args.");
836 // FIXME: This path will currently return false. It was copied
837 // from the AArch64 port and should be essentially fine for Mips too.
838 // The work to finish up this path will be done in a follow-on patch.
840 assert(VA.isMemLoc() && "Assuming store on stack.");
841 // Don't emit stores for undef values.
842 if (isa<UndefValue>(ArgVal))
845 // Need to store on the stack.
846 // FIXME: This alignment is incorrect but this path is disabled
847 // for now (will return false). We need to determine the right alignment
848 // based on the normal alignment for the underlying machine type.
850 unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
852 unsigned BEAlign = 0;
853 if (ArgSize < 8 && !Subtarget->isLittle())
854 BEAlign = 8 - ArgSize;
857 Addr.setKind(Address::RegBase);
858 Addr.setReg(Mips::SP);
859 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
861 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
862 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
863 MachinePointerInfo::getStack(Addr.getOffset()),
864 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
866 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
867 return false; // can't store on the stack yet.
874 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
876 CallingConv::ID CC = CLI.CallConv;
877 emitInst(Mips::ADJCALLSTACKUP).addImm(16);
878 if (RetVT != MVT::isVoid) {
879 SmallVector<CCValAssign, 16> RVLocs;
880 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
881 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
883 // Only handle a single return value.
884 if (RVLocs.size() != 1)
886 // Copy all of the result registers out of their specified physreg.
887 MVT CopyVT = RVLocs[0].getValVT();
888 // Special handling for extended integers.
889 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
892 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
893 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
894 TII.get(TargetOpcode::COPY),
895 ResultReg).addReg(RVLocs[0].getLocReg());
896 CLI.InRegs.push_back(RVLocs[0].getLocReg());
898 CLI.ResultReg = ResultReg;
899 CLI.NumResultRegs = 1;
904 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
905 CallingConv::ID CC = CLI.CallConv;
906 bool IsTailCall = CLI.IsTailCall;
907 bool IsVarArg = CLI.IsVarArg;
908 const Value *Callee = CLI.Callee;
909 // const char *SymName = CLI.SymName;
911 // Allow SelectionDAG isel to handle tail calls.
915 // Let SDISel handle vararg functions.
919 // FIXME: Only handle *simple* calls for now.
921 if (CLI.RetTy->isVoidTy())
923 else if (!isTypeLegal(CLI.RetTy, RetVT))
926 for (auto Flag : CLI.OutFlags)
927 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
930 // Set up the argument vectors.
931 SmallVector<MVT, 16> OutVTs;
932 OutVTs.reserve(CLI.OutVals.size());
934 for (auto *Val : CLI.OutVals) {
936 if (!isTypeLegal(Val->getType(), VT) &&
937 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
940 // We don't handle vector parameters yet.
941 if (VT.isVector() || VT.getSizeInBits() > 64)
944 OutVTs.push_back(VT);
948 if (!computeCallAddress(Callee, Addr))
951 // Handle the arguments now that we've gotten them.
953 if (!processCallArgs(CLI, OutVTs, NumBytes))
957 unsigned DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
958 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
959 MachineInstrBuilder MIB =
960 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
961 Mips::RA).addReg(Mips::T9);
963 // Add implicit physical register uses to the call.
964 for (auto Reg : CLI.OutRegs)
965 MIB.addReg(Reg, RegState::Implicit);
967 // Add a register mask with the call-preserved registers.
968 // Proper defs for return values will be added by setPhysRegsDeadExcept().
969 MIB.addRegMask(TRI.getCallPreservedMask(CC));
973 // Add implicit physical register uses to the call.
974 for (auto Reg : CLI.OutRegs)
975 MIB.addReg(Reg, RegState::Implicit);
977 // Add a register mask with the call-preserved registers. Proper
978 // defs for return values will be added by setPhysRegsDeadExcept().
979 MIB.addRegMask(TRI.getCallPreservedMask(CC));
982 // Finish off the call including any return values.
983 return finishCall(CLI, RetVT, NumBytes);
986 bool MipsFastISel::selectRet(const Instruction *I) {
987 const ReturnInst *Ret = cast<ReturnInst>(I);
989 if (!FuncInfo.CanLowerReturn)
991 if (Ret->getNumOperands() > 0) {
994 emitInst(Mips::RetRA);
998 bool MipsFastISel::selectTrunc(const Instruction *I) {
999 // The high bits for a type smaller than the register size are assumed to be
1001 Value *Op = I->getOperand(0);
1004 SrcVT = TLI.getValueType(Op->getType(), true);
1005 DestVT = TLI.getValueType(I->getType(), true);
1007 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1009 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1012 unsigned SrcReg = getRegForValue(Op);
1016 // Because the high bits are undefined, a truncate doesn't generate
1018 updateValueMap(I, SrcReg);
1021 bool MipsFastISel::selectIntExt(const Instruction *I) {
1022 Type *DestTy = I->getType();
1023 Value *Src = I->getOperand(0);
1024 Type *SrcTy = Src->getType();
1026 bool isZExt = isa<ZExtInst>(I);
1027 unsigned SrcReg = getRegForValue(Src);
1031 EVT SrcEVT, DestEVT;
1032 SrcEVT = TLI.getValueType(SrcTy, true);
1033 DestEVT = TLI.getValueType(DestTy, true);
1034 if (!SrcEVT.isSimple())
1036 if (!DestEVT.isSimple())
1039 MVT SrcVT = SrcEVT.getSimpleVT();
1040 MVT DestVT = DestEVT.getSimpleVT();
1041 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1043 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1045 updateValueMap(I, ResultReg);
1048 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1051 switch (SrcVT.SimpleTy) {
1061 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1062 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1063 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1067 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1069 switch (SrcVT.SimpleTy) {
1073 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1076 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1082 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1084 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1086 if (Subtarget->hasMips32r2())
1087 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1088 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1091 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1093 switch (SrcVT.SimpleTy) {
1097 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1100 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1103 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1109 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1110 unsigned DestReg, bool IsZExt) {
1112 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1113 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1116 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1118 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1119 return emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1122 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1123 if (!TargetSupported)
1125 switch (I->getOpcode()) {
1128 case Instruction::Load:
1129 return selectLoad(I);
1130 case Instruction::Store:
1131 return selectStore(I);
1132 case Instruction::Br:
1133 return selectBranch(I);
1134 case Instruction::Ret:
1135 return selectRet(I);
1136 case Instruction::Trunc:
1137 return selectTrunc(I);
1138 case Instruction::ZExt:
1139 case Instruction::SExt:
1140 return selectIntExt(I);
1141 case Instruction::FPTrunc:
1142 return selectFPTrunc(I);
1143 case Instruction::FPExt:
1144 return selectFPExt(I);
1145 case Instruction::FPToSI:
1146 return selectFPToInt(I, /*isSigned*/ true);
1147 case Instruction::FPToUI:
1148 return selectFPToInt(I, /*isSigned*/ false);
1149 case Instruction::ICmp:
1150 case Instruction::FCmp:
1151 return selectCmp(I);
1156 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1158 unsigned VReg = getRegForValue(V);
1161 MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
1162 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1163 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1164 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1172 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1173 const TargetLibraryInfo *libInfo) {
1174 return new MipsFastISel(funcInfo, libInfo);