1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "MipsCCState.h"
5 #include "MipsInstrInfo.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/FunctionLoweringInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/IR/GetElementPtrTypeIterator.h"
17 #include "llvm/IR/GlobalAlias.h"
18 #include "llvm/IR/GlobalVariable.h"
19 #include "llvm/Target/TargetInstrInfo.h"
25 class MipsFastISel final : public FastISel {
27 // All possible address modes.
30 typedef enum { RegBase, FrameIndexBase } BaseKind;
41 const GlobalValue *GV;
44 // Innocuous defaults for our address.
45 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
46 void setKind(BaseKind K) { Kind = K; }
47 BaseKind getKind() const { return Kind; }
48 bool isRegBase() const { return Kind == RegBase; }
49 bool isFIBase() const { return Kind == FrameIndexBase; }
50 void setReg(unsigned Reg) {
51 assert(isRegBase() && "Invalid base register access!");
54 unsigned getReg() const {
55 assert(isRegBase() && "Invalid base register access!");
58 void setFI(unsigned FI) {
59 assert(isFIBase() && "Invalid base frame index access!");
62 unsigned getFI() const {
63 assert(isFIBase() && "Invalid base frame index access!");
67 void setOffset(int64_t Offset_) { Offset = Offset_; }
68 int64_t getOffset() const { return Offset; }
69 void setGlobalValue(const GlobalValue *G) { GV = G; }
70 const GlobalValue *getGlobalValue() { return GV; }
73 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
74 /// make the right decision when generating code for different targets.
75 const TargetMachine &TM;
76 const MipsSubtarget *Subtarget;
77 const TargetInstrInfo &TII;
78 const TargetLowering &TLI;
79 MipsFunctionInfo *MFI;
81 // Convenience variables to avoid some queries.
84 bool fastLowerCall(CallLoweringInfo &CLI) override;
87 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
88 // floating point but not reject doing fast-isel in other
92 // Selection routines.
93 bool selectLogicalOp(const Instruction *I);
94 bool selectLoad(const Instruction *I);
95 bool selectStore(const Instruction *I);
96 bool selectBranch(const Instruction *I);
97 bool selectCmp(const Instruction *I);
98 bool selectFPExt(const Instruction *I);
99 bool selectFPTrunc(const Instruction *I);
100 bool selectFPToInt(const Instruction *I, bool IsSigned);
101 bool selectRet(const Instruction *I);
102 bool selectTrunc(const Instruction *I);
103 bool selectIntExt(const Instruction *I);
104 bool selectShift(const Instruction *I);
106 // Utility helper routines.
107 bool isTypeLegal(Type *Ty, MVT &VT);
108 bool isTypeSupported(Type *Ty, MVT &VT);
109 bool isLoadTypeLegal(Type *Ty, MVT &VT);
110 bool computeAddress(const Value *Obj, Address &Addr);
111 bool computeCallAddress(const Value *V, Address &Addr);
112 void simplifyAddress(Address &Addr);
114 // Emit helper routines.
115 bool emitCmp(unsigned DestReg, const CmpInst *CI);
116 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
117 unsigned Alignment = 0);
118 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
119 MachineMemOperand *MMO = nullptr);
120 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
121 unsigned Alignment = 0);
122 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
123 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
126 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
128 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
129 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
131 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
134 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
136 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
139 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
140 unsigned materializeGV(const GlobalValue *GV, MVT VT);
141 unsigned materializeInt(const Constant *C, MVT VT);
142 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
144 MachineInstrBuilder emitInst(unsigned Opc) {
145 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
147 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
148 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
151 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
152 unsigned MemReg, int64_t MemOffset) {
153 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
155 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
156 unsigned MemReg, int64_t MemOffset) {
157 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
160 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
161 const TargetRegisterClass *RC,
162 unsigned Op0, bool Op0IsKill,
163 unsigned Op1, bool Op1IsKill);
165 // for some reason, this default is not generated by tablegen
166 // so we explicitly generate it here.
168 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
169 unsigned Op0, bool Op0IsKill, uint64_t imm1,
170 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
174 // Call handling routines.
176 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
177 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
179 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
182 // Backend specific FastISel code.
183 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
184 const TargetLibraryInfo *libInfo)
185 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
186 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
187 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
188 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
189 Context = &funcInfo.Fn->getContext();
191 ((TM.getRelocationModel() == Reloc::PIC_) &&
192 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
193 (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
194 UnsupportedFPMode = Subtarget->isFP64bit();
197 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
198 unsigned fastMaterializeConstant(const Constant *C) override;
199 bool fastSelectInstruction(const Instruction *I) override;
201 #include "MipsGenFastISel.inc"
203 } // end anonymous namespace.
205 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
206 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
207 CCState &State) LLVM_ATTRIBUTE_UNUSED;
209 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
210 CCValAssign::LocInfo LocInfo,
211 ISD::ArgFlagsTy ArgFlags, CCState &State) {
212 llvm_unreachable("should not be called");
215 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
216 CCValAssign::LocInfo LocInfo,
217 ISD::ArgFlagsTy ArgFlags, CCState &State) {
218 llvm_unreachable("should not be called");
221 #include "MipsGenCallingConv.inc"
223 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
227 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
228 const Value *LHS, const Value *RHS) {
229 // Canonicalize immediates to the RHS first.
230 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
234 if (ISDOpc == ISD::AND) {
236 } else if (ISDOpc == ISD::OR) {
238 } else if (ISDOpc == ISD::XOR) {
241 llvm_unreachable("unexpected opcode");
243 unsigned LHSReg = getRegForValue(LHS);
244 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
252 if (const auto *C = dyn_cast<ConstantInt>(RHS))
253 RHSReg = materializeInt(C, MVT::i32);
255 RHSReg = getRegForValue(RHS);
260 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
264 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
265 assert(TLI.getValueType(AI->getType(), true) == MVT::i32 &&
266 "Alloca should always return a pointer.");
268 DenseMap<const AllocaInst *, int>::iterator SI =
269 FuncInfo.StaticAllocaMap.find(AI);
271 if (SI != FuncInfo.StaticAllocaMap.end()) {
272 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
273 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
275 .addFrameIndex(SI->second)
283 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
284 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
286 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
287 const ConstantInt *CI = cast<ConstantInt>(C);
289 if ((VT != MVT::i1) && CI->isNegative())
290 Imm = CI->getSExtValue();
292 Imm = CI->getZExtValue();
293 return materialize32BitInt(Imm, RC);
296 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
297 const TargetRegisterClass *RC) {
298 unsigned ResultReg = createResultReg(RC);
300 if (isInt<16>(Imm)) {
301 unsigned Opc = Mips::ADDiu;
302 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
304 } else if (isUInt<16>(Imm)) {
305 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
308 unsigned Lo = Imm & 0xFFFF;
309 unsigned Hi = (Imm >> 16) & 0xFFFF;
311 // Both Lo and Hi have nonzero bits.
312 unsigned TmpReg = createResultReg(RC);
313 emitInst(Mips::LUi, TmpReg).addImm(Hi);
314 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
316 emitInst(Mips::LUi, ResultReg).addImm(Hi);
321 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
322 if (UnsupportedFPMode)
324 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
325 if (VT == MVT::f32) {
326 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
327 unsigned DestReg = createResultReg(RC);
328 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
329 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
331 } else if (VT == MVT::f64) {
332 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
333 unsigned DestReg = createResultReg(RC);
334 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
336 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
337 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
343 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
344 // For now 32-bit only.
347 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
348 unsigned DestReg = createResultReg(RC);
349 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
350 bool IsThreadLocal = GVar && GVar->isThreadLocal();
351 // TLS not supported at this time.
354 emitInst(Mips::LW, DestReg)
355 .addReg(MFI->getGlobalBaseReg())
356 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
357 if ((GV->hasInternalLinkage() ||
358 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
359 unsigned TempReg = createResultReg(RC);
360 emitInst(Mips::ADDiu, TempReg)
362 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
368 // Materialize a constant into a register, and return the register
369 // number (or zero if we failed to handle it).
370 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
371 EVT CEVT = TLI.getValueType(C->getType(), true);
373 // Only handle simple types.
374 if (!CEVT.isSimple())
376 MVT VT = CEVT.getSimpleVT();
378 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
379 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
380 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
381 return materializeGV(GV, VT);
382 else if (isa<ConstantInt>(C))
383 return materializeInt(C, VT);
388 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
390 const User *U = nullptr;
391 unsigned Opcode = Instruction::UserOp1;
392 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
393 // Don't walk into other basic blocks unless the object is an alloca from
394 // another block, otherwise it may not have a virtual register assigned.
395 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
396 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
397 Opcode = I->getOpcode();
400 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
401 Opcode = C->getOpcode();
407 case Instruction::BitCast: {
408 // Look through bitcasts.
409 return computeAddress(U->getOperand(0), Addr);
411 case Instruction::GetElementPtr: {
412 Address SavedAddr = Addr;
413 uint64_t TmpOffset = Addr.getOffset();
414 // Iterate through the GEP folding the constants into offsets where
416 gep_type_iterator GTI = gep_type_begin(U);
417 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
419 const Value *Op = *i;
420 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
421 const StructLayout *SL = DL.getStructLayout(STy);
422 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
423 TmpOffset += SL->getElementOffset(Idx);
425 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
427 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
428 // Constant-offset addressing.
429 TmpOffset += CI->getSExtValue() * S;
432 if (canFoldAddIntoGEP(U, Op)) {
433 // A compatible add with a constant operand. Fold the constant.
435 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
436 TmpOffset += CI->getSExtValue() * S;
437 // Iterate on the other operand.
438 Op = cast<AddOperator>(Op)->getOperand(0);
442 goto unsupported_gep;
446 // Try to grab the base operand now.
447 Addr.setOffset(TmpOffset);
448 if (computeAddress(U->getOperand(0), Addr))
450 // We failed, restore everything and try the other options.
455 case Instruction::Alloca: {
456 const AllocaInst *AI = cast<AllocaInst>(Obj);
457 DenseMap<const AllocaInst *, int>::iterator SI =
458 FuncInfo.StaticAllocaMap.find(AI);
459 if (SI != FuncInfo.StaticAllocaMap.end()) {
460 Addr.setKind(Address::FrameIndexBase);
461 Addr.setFI(SI->second);
467 Addr.setReg(getRegForValue(Obj));
468 return Addr.getReg() != 0;
471 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
472 const GlobalValue *GV = dyn_cast<GlobalValue>(V);
473 if (GV && isa<Function>(GV) && cast<Function>(GV)->isIntrinsic())
477 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
478 Addr.setGlobalValue(GV);
484 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
485 EVT evt = TLI.getValueType(Ty, true);
486 // Only handle simple types.
487 if (evt == MVT::Other || !evt.isSimple())
489 VT = evt.getSimpleVT();
491 // Handle all legal types, i.e. a register that will directly hold this
493 return TLI.isTypeLegal(VT);
496 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
497 if (Ty->isVectorTy())
500 if (isTypeLegal(Ty, VT))
503 // If this is a type than can be sign or zero-extended to a basic operation
504 // go ahead and accept it now.
505 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
511 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
512 if (isTypeLegal(Ty, VT))
514 // We will extend this in a later patch:
515 // If this is a type than can be sign or zero-extended to a basic operation
516 // go ahead and accept it now.
517 if (VT == MVT::i8 || VT == MVT::i16)
521 // Because of how EmitCmp is called with fast-isel, you can
522 // end up with redundant "andi" instructions after the sequences emitted below.
523 // We should try and solve this issue in the future.
525 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
526 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
527 bool IsUnsigned = CI->isUnsigned();
528 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
531 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
534 CmpInst::Predicate P = CI->getPredicate();
539 case CmpInst::ICMP_EQ: {
540 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
541 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
542 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
545 case CmpInst::ICMP_NE: {
546 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
547 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
548 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
551 case CmpInst::ICMP_UGT: {
552 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
555 case CmpInst::ICMP_ULT: {
556 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
559 case CmpInst::ICMP_UGE: {
560 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
561 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
562 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
565 case CmpInst::ICMP_ULE: {
566 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
567 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
568 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
571 case CmpInst::ICMP_SGT: {
572 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
575 case CmpInst::ICMP_SLT: {
576 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
579 case CmpInst::ICMP_SGE: {
580 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
581 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
582 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
585 case CmpInst::ICMP_SLE: {
586 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
587 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
588 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
591 case CmpInst::FCMP_OEQ:
592 case CmpInst::FCMP_UNE:
593 case CmpInst::FCMP_OLT:
594 case CmpInst::FCMP_OLE:
595 case CmpInst::FCMP_OGT:
596 case CmpInst::FCMP_OGE: {
597 if (UnsupportedFPMode)
599 bool IsFloat = Left->getType()->isFloatTy();
600 bool IsDouble = Left->getType()->isDoubleTy();
601 if (!IsFloat && !IsDouble)
603 unsigned Opc, CondMovOpc;
605 case CmpInst::FCMP_OEQ:
606 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
607 CondMovOpc = Mips::MOVT_I;
609 case CmpInst::FCMP_UNE:
610 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
611 CondMovOpc = Mips::MOVF_I;
613 case CmpInst::FCMP_OLT:
614 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
615 CondMovOpc = Mips::MOVT_I;
617 case CmpInst::FCMP_OLE:
618 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
619 CondMovOpc = Mips::MOVT_I;
621 case CmpInst::FCMP_OGT:
622 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
623 CondMovOpc = Mips::MOVF_I;
625 case CmpInst::FCMP_OGE:
626 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
627 CondMovOpc = Mips::MOVF_I;
630 llvm_unreachable("Only switching of a subset of CCs.");
632 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
633 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
634 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
635 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
636 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
637 Mips::FCC0, RegState::ImplicitDefine);
638 MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
641 .addReg(RegWithZero, RegState::Implicit);
642 MI->tieOperands(0, 3);
648 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
649 unsigned Alignment) {
651 // more cases will be handled here in following patches.
654 switch (VT.SimpleTy) {
656 ResultReg = createResultReg(&Mips::GPR32RegClass);
661 ResultReg = createResultReg(&Mips::GPR32RegClass);
666 ResultReg = createResultReg(&Mips::GPR32RegClass);
671 if (UnsupportedFPMode)
673 ResultReg = createResultReg(&Mips::FGR32RegClass);
678 if (UnsupportedFPMode)
680 ResultReg = createResultReg(&Mips::AFGR64RegClass);
687 if (Addr.isRegBase()) {
688 simplifyAddress(Addr);
689 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
692 if (Addr.isFIBase()) {
693 unsigned FI = Addr.getFI();
695 unsigned Offset = Addr.getOffset();
696 MachineFrameInfo &MFI = *MF->getFrameInfo();
697 MachineMemOperand *MMO = MF->getMachineMemOperand(
698 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
699 MFI.getObjectSize(FI), Align);
700 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
709 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
710 unsigned Alignment) {
712 // more cases will be handled here in following patches.
715 switch (VT.SimpleTy) {
726 if (UnsupportedFPMode)
731 if (UnsupportedFPMode)
738 if (Addr.isRegBase()) {
739 simplifyAddress(Addr);
740 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
743 if (Addr.isFIBase()) {
744 unsigned FI = Addr.getFI();
746 unsigned Offset = Addr.getOffset();
747 MachineFrameInfo &MFI = *MF->getFrameInfo();
748 MachineMemOperand *MMO = MF->getMachineMemOperand(
749 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
750 MFI.getObjectSize(FI), Align);
751 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
761 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
763 if (!isTypeSupported(I->getType(), VT))
767 switch (I->getOpcode()) {
769 llvm_unreachable("Unexpected instruction.");
770 case Instruction::And:
771 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
773 case Instruction::Or:
774 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
776 case Instruction::Xor:
777 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
784 updateValueMap(I, ResultReg);
788 bool MipsFastISel::selectLoad(const Instruction *I) {
789 // Atomic loads need special handling.
790 if (cast<LoadInst>(I)->isAtomic())
793 // Verify we have a legal type before going any further.
795 if (!isLoadTypeLegal(I->getType(), VT))
798 // See if we can handle this address.
800 if (!computeAddress(I->getOperand(0), Addr))
804 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
806 updateValueMap(I, ResultReg);
810 bool MipsFastISel::selectStore(const Instruction *I) {
811 Value *Op0 = I->getOperand(0);
814 // Atomic stores need special handling.
815 if (cast<StoreInst>(I)->isAtomic())
818 // Verify we have a legal type before going any further.
820 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
823 // Get the value to be stored into a register.
824 SrcReg = getRegForValue(Op0);
828 // See if we can handle this address.
830 if (!computeAddress(I->getOperand(1), Addr))
833 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
839 // This can cause a redundant sltiu to be generated.
840 // FIXME: try and eliminate this in a future patch.
842 bool MipsFastISel::selectBranch(const Instruction *I) {
843 const BranchInst *BI = cast<BranchInst>(I);
844 MachineBasicBlock *BrBB = FuncInfo.MBB;
846 // TBB is the basic block for the case where the comparison is true.
847 // FBB is the basic block for the case where the comparison is false.
848 // if (cond) goto TBB
852 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
853 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
855 // For now, just try the simplest case where it's fed by a compare.
856 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
857 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
858 if (!emitCmp(CondReg, CI))
860 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
863 fastEmitBranch(FBB, DbgLoc);
864 FuncInfo.MBB->addSuccessor(TBB);
870 bool MipsFastISel::selectCmp(const Instruction *I) {
871 const CmpInst *CI = cast<CmpInst>(I);
872 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
873 if (!emitCmp(ResultReg, CI))
875 updateValueMap(I, ResultReg);
879 // Attempt to fast-select a floating-point extend instruction.
880 bool MipsFastISel::selectFPExt(const Instruction *I) {
881 if (UnsupportedFPMode)
883 Value *Src = I->getOperand(0);
884 EVT SrcVT = TLI.getValueType(Src->getType(), true);
885 EVT DestVT = TLI.getValueType(I->getType(), true);
887 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
891 getRegForValue(Src); // his must be a 32 bit floating point register class
892 // maybe we should handle this differently
896 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
897 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
898 updateValueMap(I, DestReg);
902 // Attempt to fast-select a floating-point truncate instruction.
903 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
904 if (UnsupportedFPMode)
906 Value *Src = I->getOperand(0);
907 EVT SrcVT = TLI.getValueType(Src->getType(), true);
908 EVT DestVT = TLI.getValueType(I->getType(), true);
910 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
913 unsigned SrcReg = getRegForValue(Src);
917 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
921 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
922 updateValueMap(I, DestReg);
926 // Attempt to fast-select a floating-point-to-integer conversion.
927 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
928 if (UnsupportedFPMode)
932 return false; // We don't handle this case yet. There is no native
933 // instruction for this but it can be synthesized.
934 Type *DstTy = I->getType();
935 if (!isTypeLegal(DstTy, DstVT))
938 if (DstVT != MVT::i32)
941 Value *Src = I->getOperand(0);
942 Type *SrcTy = Src->getType();
943 if (!isTypeLegal(SrcTy, SrcVT))
946 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
949 unsigned SrcReg = getRegForValue(Src);
953 // Determine the opcode for the conversion, which takes place
954 // entirely within FPRs.
955 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
956 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
959 if (SrcVT == MVT::f32)
960 Opc = Mips::TRUNC_W_S;
962 Opc = Mips::TRUNC_W_D32;
964 // Generate the convert.
965 emitInst(Opc, TempReg).addReg(SrcReg);
967 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
969 updateValueMap(I, DestReg);
973 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
974 SmallVectorImpl<MVT> &OutVTs,
975 unsigned &NumBytes) {
976 CallingConv::ID CC = CLI.CallConv;
977 SmallVector<CCValAssign, 16> ArgLocs;
978 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
979 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
980 // Get a count of how many bytes are to be pushed on the stack.
981 NumBytes = CCInfo.getNextStackOffset();
982 // This is the minimum argument area used for A0-A3.
986 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
989 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
990 CCValAssign &VA = ArgLocs[i];
991 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
992 MVT ArgVT = OutVTs[VA.getValNo()];
996 if (ArgVT == MVT::f32) {
997 VA.convertToReg(Mips::F12);
998 } else if (ArgVT == MVT::f64) {
999 VA.convertToReg(Mips::D6);
1001 } else if (i == 1) {
1002 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1003 if (ArgVT == MVT::f32) {
1004 VA.convertToReg(Mips::F14);
1005 } else if (ArgVT == MVT::f64) {
1006 VA.convertToReg(Mips::D7);
1010 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1011 (ArgVT == MVT::i8)) &&
1013 switch (VA.getLocMemOffset()) {
1015 VA.convertToReg(Mips::A0);
1018 VA.convertToReg(Mips::A1);
1021 VA.convertToReg(Mips::A2);
1024 VA.convertToReg(Mips::A3);
1030 unsigned ArgReg = getRegForValue(ArgVal);
1034 // Handle arg promotion: SExt, ZExt, AExt.
1035 switch (VA.getLocInfo()) {
1036 case CCValAssign::Full:
1038 case CCValAssign::AExt:
1039 case CCValAssign::SExt: {
1040 MVT DestVT = VA.getLocVT();
1042 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1047 case CCValAssign::ZExt: {
1048 MVT DestVT = VA.getLocVT();
1050 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1056 llvm_unreachable("Unknown arg promotion!");
1059 // Now copy/store arg to correct locations.
1060 if (VA.isRegLoc() && !VA.needsCustom()) {
1061 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1062 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1063 CLI.OutRegs.push_back(VA.getLocReg());
1064 } else if (VA.needsCustom()) {
1065 llvm_unreachable("Mips does not use custom args.");
1069 // FIXME: This path will currently return false. It was copied
1070 // from the AArch64 port and should be essentially fine for Mips too.
1071 // The work to finish up this path will be done in a follow-on patch.
1073 assert(VA.isMemLoc() && "Assuming store on stack.");
1074 // Don't emit stores for undef values.
1075 if (isa<UndefValue>(ArgVal))
1078 // Need to store on the stack.
1079 // FIXME: This alignment is incorrect but this path is disabled
1080 // for now (will return false). We need to determine the right alignment
1081 // based on the normal alignment for the underlying machine type.
1083 unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
1085 unsigned BEAlign = 0;
1086 if (ArgSize < 8 && !Subtarget->isLittle())
1087 BEAlign = 8 - ArgSize;
1090 Addr.setKind(Address::RegBase);
1091 Addr.setReg(Mips::SP);
1092 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1094 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1095 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1096 MachinePointerInfo::getStack(Addr.getOffset()),
1097 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1099 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1100 return false; // can't store on the stack yet.
1107 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1108 unsigned NumBytes) {
1109 CallingConv::ID CC = CLI.CallConv;
1110 emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1111 if (RetVT != MVT::isVoid) {
1112 SmallVector<CCValAssign, 16> RVLocs;
1113 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1114 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1116 // Only handle a single return value.
1117 if (RVLocs.size() != 1)
1119 // Copy all of the result registers out of their specified physreg.
1120 MVT CopyVT = RVLocs[0].getValVT();
1121 // Special handling for extended integers.
1122 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1125 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1128 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1129 TII.get(TargetOpcode::COPY),
1130 ResultReg).addReg(RVLocs[0].getLocReg());
1131 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1133 CLI.ResultReg = ResultReg;
1134 CLI.NumResultRegs = 1;
1139 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1140 CallingConv::ID CC = CLI.CallConv;
1141 bool IsTailCall = CLI.IsTailCall;
1142 bool IsVarArg = CLI.IsVarArg;
1143 const Value *Callee = CLI.Callee;
1144 // const char *SymName = CLI.SymName;
1146 // Allow SelectionDAG isel to handle tail calls.
1150 // Let SDISel handle vararg functions.
1154 // FIXME: Only handle *simple* calls for now.
1156 if (CLI.RetTy->isVoidTy())
1157 RetVT = MVT::isVoid;
1158 else if (!isTypeSupported(CLI.RetTy, RetVT))
1161 for (auto Flag : CLI.OutFlags)
1162 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1165 // Set up the argument vectors.
1166 SmallVector<MVT, 16> OutVTs;
1167 OutVTs.reserve(CLI.OutVals.size());
1169 for (auto *Val : CLI.OutVals) {
1171 if (!isTypeLegal(Val->getType(), VT) &&
1172 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1175 // We don't handle vector parameters yet.
1176 if (VT.isVector() || VT.getSizeInBits() > 64)
1179 OutVTs.push_back(VT);
1183 if (!computeCallAddress(Callee, Addr))
1186 // Handle the arguments now that we've gotten them.
1188 if (!processCallArgs(CLI, OutVTs, NumBytes))
1192 unsigned DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1193 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1194 MachineInstrBuilder MIB =
1195 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1196 Mips::RA).addReg(Mips::T9);
1198 // Add implicit physical register uses to the call.
1199 for (auto Reg : CLI.OutRegs)
1200 MIB.addReg(Reg, RegState::Implicit);
1202 // Add a register mask with the call-preserved registers.
1203 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1204 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1208 // Finish off the call including any return values.
1209 return finishCall(CLI, RetVT, NumBytes);
1212 bool MipsFastISel::selectRet(const Instruction *I) {
1213 const Function &F = *I->getParent()->getParent();
1214 const ReturnInst *Ret = cast<ReturnInst>(I);
1216 if (!FuncInfo.CanLowerReturn)
1219 // Build a list of return value registers.
1220 SmallVector<unsigned, 4> RetRegs;
1222 if (Ret->getNumOperands() > 0) {
1223 CallingConv::ID CC = F.getCallingConv();
1224 SmallVector<ISD::OutputArg, 4> Outs;
1225 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1226 // Analyze operands of the call, assigning locations to each operand.
1227 SmallVector<CCValAssign, 16> ValLocs;
1228 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1230 CCAssignFn *RetCC = RetCC_Mips;
1231 CCInfo.AnalyzeReturn(Outs, RetCC);
1233 // Only handle a single return value for now.
1234 if (ValLocs.size() != 1)
1237 CCValAssign &VA = ValLocs[0];
1238 const Value *RV = Ret->getOperand(0);
1240 // Don't bother handling odd stuff for now.
1241 if ((VA.getLocInfo() != CCValAssign::Full) &&
1242 (VA.getLocInfo() != CCValAssign::BCvt))
1245 // Only handle register returns for now.
1249 unsigned Reg = getRegForValue(RV);
1253 unsigned SrcReg = Reg + VA.getValNo();
1254 unsigned DestReg = VA.getLocReg();
1255 // Avoid a cross-class copy. This is very unlikely.
1256 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1259 EVT RVEVT = TLI.getValueType(RV->getType());
1260 if (!RVEVT.isSimple())
1263 if (RVEVT.isVector())
1266 MVT RVVT = RVEVT.getSimpleVT();
1267 if (RVVT == MVT::f128)
1270 MVT DestVT = VA.getValVT();
1271 // Special handling for extended integers.
1272 if (RVVT != DestVT) {
1273 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1276 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1277 bool IsZExt = Outs[0].Flags.isZExt();
1278 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1285 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1286 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1288 // Add register to return instruction.
1289 RetRegs.push_back(VA.getLocReg());
1291 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1292 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1293 MIB.addReg(RetRegs[i], RegState::Implicit);
1297 bool MipsFastISel::selectTrunc(const Instruction *I) {
1298 // The high bits for a type smaller than the register size are assumed to be
1300 Value *Op = I->getOperand(0);
1303 SrcVT = TLI.getValueType(Op->getType(), true);
1304 DestVT = TLI.getValueType(I->getType(), true);
1306 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1308 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1311 unsigned SrcReg = getRegForValue(Op);
1315 // Because the high bits are undefined, a truncate doesn't generate
1317 updateValueMap(I, SrcReg);
1320 bool MipsFastISel::selectIntExt(const Instruction *I) {
1321 Type *DestTy = I->getType();
1322 Value *Src = I->getOperand(0);
1323 Type *SrcTy = Src->getType();
1325 bool isZExt = isa<ZExtInst>(I);
1326 unsigned SrcReg = getRegForValue(Src);
1330 EVT SrcEVT, DestEVT;
1331 SrcEVT = TLI.getValueType(SrcTy, true);
1332 DestEVT = TLI.getValueType(DestTy, true);
1333 if (!SrcEVT.isSimple())
1335 if (!DestEVT.isSimple())
1338 MVT SrcVT = SrcEVT.getSimpleVT();
1339 MVT DestVT = DestEVT.getSimpleVT();
1340 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1342 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1344 updateValueMap(I, ResultReg);
1347 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1350 switch (SrcVT.SimpleTy) {
1360 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1361 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1362 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1366 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1368 switch (SrcVT.SimpleTy) {
1372 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1375 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1381 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1383 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1385 if (Subtarget->hasMips32r2())
1386 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1387 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1390 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1392 switch (SrcVT.SimpleTy) {
1396 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1399 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1402 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1408 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1409 unsigned DestReg, bool IsZExt) {
1410 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1411 // DestVT are odd things, so test to make sure that they are both types we can
1412 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1413 // bail out to SelectionDAG.
1414 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1415 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1418 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1419 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1422 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1424 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1425 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1426 return Success ? DestReg : 0;
1429 bool MipsFastISel::selectShift(const Instruction *I) {
1432 if (!isTypeSupported(I->getType(), RetVT))
1435 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1439 unsigned Opcode = I->getOpcode();
1440 const Value *Op0 = I->getOperand(0);
1441 unsigned Op0Reg = getRegForValue(Op0);
1445 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1446 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1447 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1451 MVT Op0MVT = TLI.getValueType(Op0->getType(), true).getSimpleVT();
1452 bool IsZExt = Opcode == Instruction::LShr;
1453 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1459 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1460 uint64_t ShiftVal = C->getZExtValue();
1464 llvm_unreachable("Unexpected instruction.");
1465 case Instruction::Shl:
1468 case Instruction::AShr:
1471 case Instruction::LShr:
1476 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1477 updateValueMap(I, ResultReg);
1481 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1487 llvm_unreachable("Unexpected instruction.");
1488 case Instruction::Shl:
1489 Opcode = Mips::SLLV;
1491 case Instruction::AShr:
1492 Opcode = Mips::SRAV;
1494 case Instruction::LShr:
1495 Opcode = Mips::SRLV;
1499 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1500 updateValueMap(I, ResultReg);
1504 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1505 if (!TargetSupported)
1507 switch (I->getOpcode()) {
1510 case Instruction::Load:
1511 return selectLoad(I);
1512 case Instruction::Store:
1513 return selectStore(I);
1514 case Instruction::Shl:
1515 case Instruction::LShr:
1516 case Instruction::AShr:
1517 return selectShift(I);
1518 case Instruction::And:
1519 case Instruction::Or:
1520 case Instruction::Xor:
1521 return selectLogicalOp(I);
1522 case Instruction::Br:
1523 return selectBranch(I);
1524 case Instruction::Ret:
1525 return selectRet(I);
1526 case Instruction::Trunc:
1527 return selectTrunc(I);
1528 case Instruction::ZExt:
1529 case Instruction::SExt:
1530 return selectIntExt(I);
1531 case Instruction::FPTrunc:
1532 return selectFPTrunc(I);
1533 case Instruction::FPExt:
1534 return selectFPExt(I);
1535 case Instruction::FPToSI:
1536 return selectFPToInt(I, /*isSigned*/ true);
1537 case Instruction::FPToUI:
1538 return selectFPToInt(I, /*isSigned*/ false);
1539 case Instruction::ICmp:
1540 case Instruction::FCmp:
1541 return selectCmp(I);
1546 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1548 unsigned VReg = getRegForValue(V);
1551 MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
1552 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1553 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1554 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1561 void MipsFastISel::simplifyAddress(Address &Addr) {
1562 if (!isInt<16>(Addr.getOffset())) {
1564 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1565 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1566 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1567 Addr.setReg(DestReg);
1572 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1573 const TargetRegisterClass *RC,
1574 unsigned Op0, bool Op0IsKill,
1575 unsigned Op1, bool Op1IsKill) {
1576 // We treat the MUL instruction in a special way because it clobbers
1577 // the HI0 & LO0 registers. The TableGen definition of this instruction can
1578 // mark these registers only as implicitly defined. As a result, the
1579 // register allocator runs out of registers when this instruction is
1580 // followed by another instruction that defines the same registers too.
1581 // We can fix this by explicitly marking those registers as dead.
1582 if (MachineInstOpcode == Mips::MUL) {
1583 unsigned ResultReg = createResultReg(RC);
1584 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1585 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1586 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1587 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1588 .addReg(Op0, getKillRegState(Op0IsKill))
1589 .addReg(Op1, getKillRegState(Op1IsKill))
1590 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
1591 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
1595 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
1600 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1601 const TargetLibraryInfo *libInfo) {
1602 return new MipsFastISel(funcInfo, libInfo);