1 //===-- DelaySlotFiller.cpp - Mips Delay Slot Filler ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Simple pass to fills delay slots with useful instructions.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "delay-slot-filler"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
29 STATISTIC(FilledSlots, "Number of delay slots filled");
30 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
33 static cl::opt<bool> DisableDelaySlotFiller(
34 "disable-mips-delay-filler",
36 cl::desc("Disable the delay slot filler, which attempts to fill the Mips"
37 "delay slots with useful instructions."),
40 // This option can be used to silence complaints by machine verifier passes.
41 static cl::opt<bool> SkipDelaySlotFiller(
42 "skip-mips-delay-filler",
44 cl::desc("Skip MIPS' delay slot filling pass."),
48 class Filler : public MachineFunctionPass {
50 Filler(TargetMachine &tm)
51 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
53 virtual const char *getPassName() const {
54 return "Mips Delay Slot Filler";
57 bool runOnMachineFunction(MachineFunction &F) {
58 if (SkipDelaySlotFiller)
62 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
64 Changed |= runOnMachineBasicBlock(*FI);
69 typedef MachineBasicBlock::iterator Iter;
70 typedef MachineBasicBlock::reverse_iterator ReverseIter;
72 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
74 bool isDelayFiller(MachineBasicBlock &MBB,
77 void insertCallUses(Iter MI,
78 SmallSet<unsigned, 32> &RegDefs,
79 SmallSet<unsigned, 32> &RegUses);
81 void insertDefsUses(Iter MI,
82 SmallSet<unsigned, 32> &RegDefs,
83 SmallSet<unsigned, 32> &RegUses);
85 bool IsRegInSet(SmallSet<unsigned, 32> &RegSet,
88 bool delayHasHazard(Iter candidate,
89 bool &sawLoad, bool &sawStore,
90 SmallSet<unsigned, 32> &RegDefs,
91 SmallSet<unsigned, 32> &RegUses);
94 findDelayInstr(MachineBasicBlock &MBB, Iter slot,
97 bool terminateSearch(const MachineInstr &Candidate) const;
100 const TargetInstrInfo *TII;
105 } // end of anonymous namespace
107 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
108 /// We assume there is only one delay slot per delayed instruction.
110 runOnMachineBasicBlock(MachineBasicBlock &MBB) {
111 bool Changed = false;
113 for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
114 if (!I->hasDelaySlot())
121 // Delay slot filling is disabled at -O0.
122 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) &&
123 findDelayInstr(MBB, I, D)) {
124 MBB.splice(llvm::next(I), &MBB, D);
127 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
129 // Bundle the delay slot filler to the instruction with the delay slot.
130 MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
136 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
137 /// slots in Mips MachineFunctions
138 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
139 return new Filler(tm);
142 bool Filler::findDelayInstr(MachineBasicBlock &MBB,
145 SmallSet<unsigned, 32> RegDefs;
146 SmallSet<unsigned, 32> RegUses;
148 insertDefsUses(slot, RegDefs, RegUses);
150 bool sawLoad = false;
151 bool sawStore = false;
153 for (ReverseIter I(slot); I != MBB.rend(); ++I) {
155 if (I->isDebugValue())
158 if (terminateSearch(*I))
161 // Convert to forward iterator.
162 Iter FI(llvm::next(I).base());
164 if (delayHasHazard(FI, sawLoad, sawStore, RegDefs, RegUses)) {
165 insertDefsUses(FI, RegDefs, RegUses);
176 bool Filler::delayHasHazard(Iter candidate,
177 bool &sawLoad, bool &sawStore,
178 SmallSet<unsigned, 32> &RegDefs,
179 SmallSet<unsigned, 32> &RegUses) {
180 if (candidate->isImplicitDef() || candidate->isKill())
183 // Loads or stores cannot be moved past a store to the delay slot
184 // and stores cannot be moved past a load.
185 if (candidate->mayLoad()) {
191 if (candidate->mayStore()) {
199 assert((!candidate->isCall() && !candidate->isReturn()) &&
200 "Cannot put calls or returns in delay slot.");
202 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
203 const MachineOperand &MO = candidate->getOperand(i);
206 if (!MO.isReg() || !(Reg = MO.getReg()))
210 // check whether Reg is defined or used before delay slot.
211 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
215 // check whether Reg is defined before delay slot.
216 if (IsRegInSet(RegDefs, Reg))
223 // Helper function for getting a MachineOperand's register number and adding it
224 // to RegDefs or RegUses.
225 static void insertDefUse(const MachineOperand &MO,
226 SmallSet<unsigned, 32> &RegDefs,
227 SmallSet<unsigned, 32> &RegUses,
228 unsigned ExcludedReg = 0) {
231 if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
240 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
241 void Filler::insertDefsUses(Iter MI,
242 SmallSet<unsigned, 32> &RegDefs,
243 SmallSet<unsigned, 32> &RegUses) {
244 unsigned I, E = MI->getDesc().getNumOperands();
246 for (I = 0; I != E; ++I)
247 insertDefUse(MI->getOperand(I), RegDefs, RegUses);
249 // If MI is a call, add RA to RegDefs to prevent users of RA from going into
252 RegDefs.insert(Mips::RA);
256 // Return if MI is a return.
260 // Examine the implicit operands. Exclude register AT which is in the list of
261 // clobbered registers of branch instructions.
262 E = MI->getNumOperands();
264 insertDefUse(MI->getOperand(I), RegDefs, RegUses, Mips::AT);
267 //returns true if the Reg or its alias is in the RegSet.
268 bool Filler::IsRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) {
269 // Check Reg and all aliased Registers.
270 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
272 if (RegSet.count(*AI))
277 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
278 return (Candidate.isTerminator() || Candidate.isCall() ||
279 Candidate.isLabel() || Candidate.isInlineAsm() ||
280 Candidate.hasUnmodeledSideEffects());