lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  24                                         SDTCisVT<2, untyped>]>;
  25 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  26                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  27 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  28                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  29 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  30                                              SDTCisVT<2, i32>]>;
  31
  32 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  33   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  34
  35 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  36   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  37
  38 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  39 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  40 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  41 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  42 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  43 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  44
  45 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  46 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  47
  48 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  49 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  51 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  53
  54 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  55 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  56 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  58 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  59 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  61 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  62
  63 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  64 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  65 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  67 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  68 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  71 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  72
  73 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  74 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  75 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  76 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  77 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  78 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  79 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  80 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  82
  83 // Flags.
  84 class UseAC {
  85   list<Register> Uses = [AC0];
  86 }
  87
  88 class UseDSPCtrl {
  89   list<Register> Uses = [DSPCtrl];
  90 }
  91
  92 class ClearDefs {
  93   list<Register> Defs = [];
  94 }
  95
  96 // Instruction encoding.
  97 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  98 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  99 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
 100 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 101 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 102 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 103 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 104 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 105 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 106 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 107 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 108 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 109 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 110 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 111 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 112 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 113 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 114 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 115 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 116 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 117 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 118 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 119 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 120 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 121 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 122 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 123 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 124 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 125 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 126 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 127 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 128 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 129 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 130 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 131 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 132 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 133 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 134 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 135 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 136 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 137 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 138 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 139 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 140 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 141 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 142 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 143 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 144 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 145 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 146 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 147 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 148 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 149 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 150 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 151 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 152 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 153 class MFHI_ENC : MFHI_FMT<0b010000>;
 154 class MFLO_ENC : MFHI_FMT<0b010010>;
 155 class MTHI_ENC : MTHI_FMT<0b010001>;
 156 class MTLO_ENC : MTHI_FMT<0b010011>;
 157 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 158 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 159 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 160 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 161 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 162 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 163 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 164 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 165 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 166 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 167 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 168 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 169 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 170 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 171 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 172 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 173 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 174 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 175 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 176 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 177 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 178 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 179 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 180 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 181 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 182 class REPL_QB_ENC : REPL_FMT<0b00010>;
 183 class REPL_PH_ENC : REPL_FMT<0b01010>;
 184 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 185 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 186 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 187 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 188 class LWX_ENC : LX_FMT<0b00000>;
 189 class LHX_ENC : LX_FMT<0b00100>;
 190 class LBUX_ENC : LX_FMT<0b00110>;
 191 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 192 class INSV_ENC : INSV_FMT<0b001100>;
 193
 194 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 195 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 196 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 197 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 198 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 199 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 200 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 201 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 202 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 203 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 204 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 205 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 206 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 207 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 208 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 209
 210 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 211 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 212 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 213 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 214 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 215 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 216 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 217 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 218 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 219 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 220 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 221 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 222 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 223 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 224 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 225 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 226 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 227 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 228 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 229 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 230 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 231 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 232 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 233 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 234 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 235 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 236 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 237 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 238 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 239 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 240 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 241 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 242 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 243 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 244 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 245 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 246 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 247 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 248 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 249 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 250 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 251 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 252 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 253 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 254 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 255 class APPEND_ENC : APPEND_FMT<0b00000>;
 256 class BALIGN_ENC : APPEND_FMT<0b10000>;
 257 class PREPEND_ENC : APPEND_FMT<0b00001>;
 258
 259 // Instruction desc.
 260 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 261                         InstrItinClass itin, RegisterClass RCD,
 262                         RegisterClass RCS,  RegisterClass RCT = RCS> {
 263   dag OutOperandList = (outs RCD:$rd);
 264   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 265   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 266   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 267   InstrItinClass Itinerary = itin;
 268   list<Register> Defs = [DSPCtrl];
 269 }
 270
 271 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 272                            InstrItinClass itin, RegisterClass RCD,
 273                            RegisterClass RCS = RCD> {
 274   dag OutOperandList = (outs RCD:$rd);
 275   dag InOperandList = (ins RCS:$rs);
 276   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 277   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
 278   InstrItinClass Itinerary = itin;
 279   list<Register> Defs = [DSPCtrl];
 280 }
 281
 282 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 283                              InstrItinClass itin, RegisterClass RCS,
 284                              RegisterClass RCT = RCS> {
 285   dag OutOperandList = (outs);
 286   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 287   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 288   list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
 289   InstrItinClass Itinerary = itin;
 290   list<Register> Defs = [DSPCtrl];
 291 }
 292
 293 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 294                              InstrItinClass itin, RegisterClass RCD,
 295                              RegisterClass RCS,  RegisterClass RCT = RCS> {
 296   dag OutOperandList = (outs RCD:$rd);
 297   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 298   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 299   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 300   InstrItinClass Itinerary = itin;
 301   list<Register> Defs = [DSPCtrl];
 302 }
 303
 304 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 305                                InstrItinClass itin, RegisterClass RCT,
 306                                RegisterClass RCS = RCT> {
 307   dag OutOperandList = (outs RCT:$rt);
 308   dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src);
 309   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 310   list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
 311   InstrItinClass Itinerary = itin;
 312   list<Register> Defs = [DSPCtrl];
 313   string Constraints = "$src = $rt";
 314 }
 315
 316 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 317                              InstrItinClass itin, RegisterClass RCD,
 318                              RegisterClass RCT = RCD> {
 319   dag OutOperandList = (outs RCD:$rd);
 320   dag InOperandList = (ins RCT:$rt);
 321   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 322   list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))];
 323   InstrItinClass Itinerary = itin;
 324   list<Register> Defs = [DSPCtrl];
 325 }
 326
 327 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 328                      ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> {
 329   dag OutOperandList = (outs RC:$rd);
 330   dag InOperandList = (ins uimm16:$imm);
 331   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 332   list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))];
 333   InstrItinClass Itinerary = itin;
 334   list<Register> Defs = [DSPCtrl];
 335 }
 336
 337 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 338                            InstrItinClass itin, RegisterClass RC> {
 339   dag OutOperandList = (outs RC:$rd);
 340   dag InOperandList =  (ins RC:$rt, CPURegs:$rs_sa);
 341   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 342   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))];
 343   InstrItinClass Itinerary = itin;
 344   list<Register> Defs = [DSPCtrl];
 345 }
 346
 347 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 348                            SDPatternOperator ImmPat, InstrItinClass itin,
 349                            RegisterClass RC> {
 350   dag OutOperandList = (outs RC:$rd);
 351   dag InOperandList = (ins RC:$rt, uimm16:$rs_sa);
 352   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 353   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))];
 354   InstrItinClass Itinerary = itin;
 355   list<Register> Defs = [DSPCtrl];
 356   bit hasSideEffects = 1;
 357 }
 358
 359 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 360                    InstrItinClass itin> {
 361   dag OutOperandList = (outs CPURegs:$rd);
 362   dag InOperandList = (ins CPURegs:$base, CPURegs:$index);
 363   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 364   list<dag> Pattern = [(set CPURegs:$rd,
 365                        (OpNode CPURegs:$base, CPURegs:$index))];
 366   InstrItinClass Itinerary = itin;
 367   list<Register> Defs = [DSPCtrl];
 368   bit mayLoad = 1;
 369 }
 370
 371 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 372                          InstrItinClass itin, RegisterClass RCD,
 373                          RegisterClass RCS = RCD,  RegisterClass RCT = RCD> {
 374   dag OutOperandList = (outs RCD:$rd);
 375   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 376   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 377   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 378   InstrItinClass Itinerary = itin;
 379   list<Register> Defs = [DSPCtrl];
 380 }
 381
 382 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 383                        SDPatternOperator ImmOp, InstrItinClass itin> {
 384   dag OutOperandList = (outs CPURegs:$rt);
 385   dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src);
 386   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 387   list<dag> Pattern =  [(set CPURegs:$rt,
 388                         (OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))];
 389   InstrItinClass Itinerary = itin;
 390   list<Register> Defs = [DSPCtrl];
 391   string Constraints = "$src = $rt";
 392 }
 393
 394 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 395                               InstrItinClass itin> {
 396   dag OutOperandList = (outs CPURegs:$rt);
 397   dag InOperandList = (ins ACRegsDSP:$ac, CPURegs:$shift_rs);
 398   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 399   InstrItinClass Itinerary = itin;
 400   list<Register> Defs = [DSPCtrl];
 401 }
 402
 403 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 404                               InstrItinClass itin> {
 405   dag OutOperandList = (outs CPURegs:$rt);
 406   dag InOperandList = (ins ACRegsDSP:$ac, uimm16:$shift_rs);
 407   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 408   InstrItinClass Itinerary = itin;
 409   list<Register> Defs = [DSPCtrl];
 410 }
 411
 412 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 413   dag OutOperandList = (outs ACRegsDSP:$ac);
 414   dag InOperandList = (ins simm16:$shift, ACRegsDSP:$acin);
 415   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 416   list<dag> Pattern = [(set ACRegsDSP:$ac,
 417                         (OpNode immSExt6:$shift, ACRegsDSP:$acin))];
 418   list<Register> Defs = [DSPCtrl];
 419   string Constraints = "$acin = $ac";
 420 }
 421
 422 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 423   dag OutOperandList = (outs ACRegsDSP:$ac);
 424   dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin);
 425   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 426   list<dag> Pattern = [(set ACRegsDSP:$ac,
 427                         (OpNode CPURegs:$rs, ACRegsDSP:$acin))];
 428   list<Register> Defs = [DSPCtrl];
 429   string Constraints = "$acin = $ac";
 430 }
 431
 432 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 433   dag OutOperandList = (outs ACRegsDSP:$ac);
 434   dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin);
 435   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 436   list<dag> Pattern = [(set ACRegsDSP:$ac,
 437                         (OpNode CPURegs:$rs, ACRegsDSP:$acin))];
 438   list<Register> Uses = [DSPCtrl];
 439   string Constraints = "$acin = $ac";
 440 }
 441
 442 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 443                       InstrItinClass itin> {
 444   dag OutOperandList = (outs CPURegs:$rd);
 445   dag InOperandList = (ins uimm16:$mask);
 446   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 447   list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))];
 448   InstrItinClass Itinerary = itin;
 449   list<Register> Uses = [DSPCtrl];
 450 }
 451
 452 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 453                       InstrItinClass itin> {
 454   dag OutOperandList = (outs);
 455   dag InOperandList = (ins CPURegs:$rs, uimm16:$mask);
 456   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 457   list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)];
 458   InstrItinClass Itinerary = itin;
 459   list<Register> Defs = [DSPCtrl];
 460 }
 461
 462 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 463   dag OutOperandList = (outs ACRegsDSP:$ac);
 464   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin);
 465   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 466   list<dag> Pattern = [(set ACRegsDSP:$ac,
 467                         (OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))];
 468   list<Register> Defs = [DSPCtrl];
 469   string Constraints = "$acin = $ac";
 470 }
 471
 472 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 473                      InstrItinClass itin> {
 474   dag OutOperandList = (outs ACRegsDSP:$ac);
 475   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 476   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 477   list<dag> Pattern = [(set ACRegsDSP:$ac, (OpNode CPURegs:$rs, CPURegs:$rt))];
 478   InstrItinClass Itinerary = itin;
 479   int AddedComplexity = 20;
 480   bit isCommutable = 1;
 481 }
 482
 483 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 484                      InstrItinClass itin> {
 485   dag OutOperandList = (outs ACRegsDSP:$ac);
 486   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin);
 487   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 488   list<dag> Pattern = [(set ACRegsDSP:$ac,
 489                         (OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))];
 490   InstrItinClass Itinerary = itin;
 491   int AddedComplexity = 20;
 492   string Constraints = "$acin = $ac";
 493 }
 494
 495 class MFHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> {
 496   dag OutOperandList = (outs CPURegs:$rd);
 497   dag InOperandList = (ins RC:$ac);
 498   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 499   InstrItinClass Itinerary = itin;
 500 }
 501
 502 class MTHI_DESC_BASE<string instr_asm, RegisterClass RC, InstrItinClass itin> {
 503   dag OutOperandList = (outs RC:$ac);
 504   dag InOperandList = (ins CPURegs:$rs);
 505   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 506   InstrItinClass Itinerary = itin;
 507 }
 508
 509 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 510   MipsPseudo<(outs CPURegs:$dst), (ins), [(set CPURegs:$dst, (OpNode))]> {
 511   list<Register> Uses = [DSPCtrl];
 512   bit usesCustomInserter = 1;
 513 }
 514
 515 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 516   dag OutOperandList = (outs);
 517   dag InOperandList = (ins brtarget:$offset);
 518   string AsmString = !strconcat(instr_asm, "\t$offset");
 519   InstrItinClass Itinerary = itin;
 520   list<Register> Uses = [DSPCtrl];
 521   bit isBranch = 1;
 522   bit isTerminator = 1;
 523   bit hasDelaySlot = 1;
 524 }
 525
 526 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 527                      InstrItinClass itin> {
 528   dag OutOperandList = (outs CPURegs:$rt);
 529   dag InOperandList = (ins CPURegs:$src, CPURegs:$rs);
 530   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 531   list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))];
 532   InstrItinClass Itinerary = itin;
 533   list<Register> Uses = [DSPCtrl];
 534   string Constraints = "$src = $rt";
 535 }
 536
 537 //===----------------------------------------------------------------------===//
 538 // MIPS DSP Rev 1
 539 //===----------------------------------------------------------------------===//
 540
 541 // Addition/subtraction
 542 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 543                                        DSPRegs, DSPRegs>, IsCommutable;
 544
 545 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 546                                          NoItinerary, DSPRegs, DSPRegs>,
 547                        IsCommutable;
 548
 549 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 550                                        DSPRegs, DSPRegs>;
 551
 552 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 553                                          NoItinerary, DSPRegs, DSPRegs>;
 554
 555 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 556                                        DSPRegs, DSPRegs>, IsCommutable;
 557
 558 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 559                                          NoItinerary, DSPRegs, DSPRegs>,
 560                        IsCommutable;
 561
 562 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 563                                        DSPRegs, DSPRegs>;
 564
 565 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 566                                          NoItinerary, DSPRegs, DSPRegs>;
 567
 568 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 569                                         NoItinerary, CPURegs, CPURegs>,
 570                       IsCommutable;
 571
 572 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 573                                         NoItinerary, CPURegs, CPURegs>;
 574
 575 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 576                                      CPURegs, CPURegs>, IsCommutable;
 577
 578 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 579                                      CPURegs, CPURegs>,
 580                    IsCommutable, UseDSPCtrl;
 581
 582 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 583                                       CPURegs, CPURegs>, ClearDefs;
 584
 585 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 586                                              NoItinerary, CPURegs, DSPRegs>,
 587                         ClearDefs;
 588
 589 // Absolute value
 590 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 591                                               NoItinerary, DSPRegs>;
 592
 593 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 594                                              NoItinerary, CPURegs>;
 595
 596 // Precision reduce/expand
 597 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 598                                                  int_mips_precrq_qb_ph,
 599                                                  NoItinerary, DSPRegs, DSPRegs>,
 600                           ClearDefs;
 601
 602 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 603                                                 int_mips_precrq_ph_w,
 604                                                 NoItinerary, DSPRegs, CPURegs>,
 605                          ClearDefs;
 606
 607 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 608                                                    int_mips_precrq_rs_ph_w,
 609                                                    NoItinerary, DSPRegs,
 610                                                    CPURegs>;
 611
 612 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 613                                                     int_mips_precrqu_s_qb_ph,
 614                                                     NoItinerary, DSPRegs,
 615                                                     DSPRegs>;
 616
 617 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 618                                                  int_mips_preceq_w_phl,
 619                                                  NoItinerary, CPURegs, DSPRegs>,
 620                           ClearDefs;
 621
 622 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 623                                                  int_mips_preceq_w_phr,
 624                                                  NoItinerary, CPURegs, DSPRegs>,
 625                           ClearDefs;
 626
 627 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 628                                                    int_mips_precequ_ph_qbl,
 629                                                    NoItinerary, DSPRegs>,
 630                             ClearDefs;
 631
 632 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 633                                                    int_mips_precequ_ph_qbr,
 634                                                    NoItinerary, DSPRegs>,
 635                             ClearDefs;
 636
 637 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 638                                                     int_mips_precequ_ph_qbla,
 639                                                     NoItinerary, DSPRegs>,
 640                              ClearDefs;
 641
 642 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 643                                                     int_mips_precequ_ph_qbra,
 644                                                     NoItinerary, DSPRegs>,
 645                              ClearDefs;
 646
 647 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 648                                                   int_mips_preceu_ph_qbl,
 649                                                   NoItinerary, DSPRegs>,
 650                            ClearDefs;
 651
 652 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 653                                                   int_mips_preceu_ph_qbr,
 654                                                   NoItinerary, DSPRegs>,
 655                            ClearDefs;
 656
 657 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 658                                                    int_mips_preceu_ph_qbla,
 659                                                    NoItinerary, DSPRegs>,
 660                             ClearDefs;
 661
 662 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 663                                                    int_mips_preceu_ph_qbra,
 664                                                    NoItinerary, DSPRegs>,
 665                             ClearDefs;
 666
 667 // Shift
 668 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 669                                           NoItinerary, DSPRegs>;
 670
 671 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 672                                            NoItinerary, DSPRegs>;
 673
 674 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 675                                           NoItinerary, DSPRegs>, ClearDefs;
 676
 677 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 678                                            NoItinerary, DSPRegs>, ClearDefs;
 679
 680 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 681                                           NoItinerary, DSPRegs>;
 682
 683 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 684                                            NoItinerary, DSPRegs>;
 685
 686 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 687                                             immZExt4, NoItinerary, DSPRegs>;
 688
 689 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 690                                              NoItinerary, DSPRegs>;
 691
 692 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 693                                           NoItinerary, DSPRegs>, ClearDefs;
 694
 695 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 696                                            NoItinerary, DSPRegs>, ClearDefs;
 697
 698 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 699                                             immZExt4, NoItinerary, DSPRegs>,
 700                        ClearDefs;
 701
 702 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 703                                              NoItinerary, DSPRegs>, ClearDefs;
 704
 705 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 706                                            immZExt5, NoItinerary, CPURegs>;
 707
 708 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 709                                             NoItinerary, CPURegs>;
 710
 711 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 712                                            immZExt5, NoItinerary, CPURegs>,
 713                       ClearDefs;
 714
 715 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 716                                             NoItinerary, CPURegs>;
 717
 718 // Multiplication
 719 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 720                                               int_mips_muleu_s_ph_qbl,
 721                                               NoItinerary, DSPRegs, DSPRegs>;
 722
 723 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 724                                               int_mips_muleu_s_ph_qbr,
 725                                               NoItinerary, DSPRegs, DSPRegs>;
 726
 727 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 728                                              int_mips_muleq_s_w_phl,
 729                                              NoItinerary, CPURegs, DSPRegs>,
 730                            IsCommutable;
 731
 732 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 733                                              int_mips_muleq_s_w_phr,
 734                                              NoItinerary, CPURegs, DSPRegs>,
 735                            IsCommutable;
 736
 737 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 738                                           NoItinerary, DSPRegs, DSPRegs>,
 739                         IsCommutable;
 740
 741 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 742                                               MipsMULSAQ_S_W_PH>;
 743
 744 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>;
 745
 746 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>;
 747
 748 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>;
 749
 750 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>;
 751
 752 // Move from/to hi/lo.
 753 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", HIRegsDSP, NoItinerary>;
 754 class MFLO_DESC : MFHI_DESC_BASE<"mflo", LORegsDSP, NoItinerary>;
 755 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HIRegsDSP, NoItinerary>;
 756 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LORegsDSP, NoItinerary>;
 757
 758 // Dot product with accumulate/subtract
 759 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 760
 761 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 762
 763 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 764
 765 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 766
 767 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>;
 768
 769 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>;
 770
 771 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>;
 772
 773 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>;
 774
 775 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 776 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 777 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 778 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 779 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 780 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 781
 782 // Comparison
 783 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 784                                                int_mips_cmpu_eq_qb, NoItinerary,
 785                                                DSPRegs>, IsCommutable;
 786
 787 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 788                                                int_mips_cmpu_lt_qb, NoItinerary,
 789                                                DSPRegs>, IsCommutable;
 790
 791 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 792                                                int_mips_cmpu_le_qb, NoItinerary,
 793                                                DSPRegs>, IsCommutable;
 794
 795 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 796                                                 int_mips_cmpgu_eq_qb,
 797                                                 NoItinerary, CPURegs, DSPRegs>,
 798                          IsCommutable;
 799
 800 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 801                                                 int_mips_cmpgu_lt_qb,
 802                                                 NoItinerary, CPURegs, DSPRegs>,
 803                          IsCommutable;
 804
 805 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 806                                                 int_mips_cmpgu_le_qb,
 807                                                 NoItinerary, CPURegs, DSPRegs>,
 808                          IsCommutable;
 809
 810 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 811                                               NoItinerary, DSPRegs>,
 812                        IsCommutable;
 813
 814 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 815                                               NoItinerary, DSPRegs>,
 816                        IsCommutable;
 817
 818 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 819                                               NoItinerary, DSPRegs>,
 820                        IsCommutable;
 821
 822 // Misc
 823 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 824                                            NoItinerary, CPURegs>, ClearDefs;
 825
 826 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 827                                               NoItinerary, DSPRegs, DSPRegs>,
 828                        ClearDefs;
 829
 830 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 831                                     NoItinerary, DSPRegs>, ClearDefs;
 832
 833 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 834                                     NoItinerary, DSPRegs>, ClearDefs;
 835
 836 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 837                                              NoItinerary, DSPRegs, CPURegs>,
 838                       ClearDefs;
 839
 840 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 841                                              NoItinerary, DSPRegs, CPURegs>,
 842                       ClearDefs;
 843
 844 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 845                                             NoItinerary, DSPRegs, DSPRegs>,
 846                      ClearDefs, UseDSPCtrl;
 847
 848 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 849                                             NoItinerary, DSPRegs, DSPRegs>,
 850                      ClearDefs, UseDSPCtrl;
 851
 852 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs;
 853
 854 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs;
 855
 856 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs;
 857
 858 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 859
 860 // Extr
 861 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
 862
 863 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
 864
 865 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
 866
 867 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 868                                              NoItinerary>;
 869
 870 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
 871
 872 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 873                                              NoItinerary>;
 874
 875 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 876                                               NoItinerary>;
 877
 878 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 879                                                NoItinerary>;
 880
 881 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 882                                                NoItinerary>;
 883
 884 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 885                                                 NoItinerary>;
 886
 887 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 888                                               NoItinerary>;
 889
 890 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 891                                                NoItinerary>;
 892
 893 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 894
 895 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 896
 897 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>;
 898
 899 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 900
 901 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 902
 903 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>;
 904
 905 //===----------------------------------------------------------------------===//
 906 // MIPS DSP Rev 2
 907 // Addition/subtraction
 908 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 909                                        DSPRegs, DSPRegs>, IsCommutable;
 910
 911 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 912                                          NoItinerary, DSPRegs, DSPRegs>,
 913                        IsCommutable;
 914
 915 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 916                                        DSPRegs, DSPRegs>;
 917
 918 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 919                                          NoItinerary, DSPRegs, DSPRegs>;
 920
 921 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 922                                          NoItinerary, DSPRegs>,
 923                       ClearDefs, IsCommutable;
 924
 925 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 926                                            NoItinerary, DSPRegs>,
 927                         ClearDefs, IsCommutable;
 928
 929 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 930                                          NoItinerary, DSPRegs>, ClearDefs;
 931
 932 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 933                                            NoItinerary, DSPRegs>, ClearDefs;
 934
 935 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 936                                          NoItinerary, DSPRegs>,
 937                       ClearDefs, IsCommutable;
 938
 939 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 940                                            NoItinerary, DSPRegs>,
 941                         ClearDefs, IsCommutable;
 942
 943 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 944                                          NoItinerary, DSPRegs>, ClearDefs;
 945
 946 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 947                                            NoItinerary, DSPRegs>, ClearDefs;
 948
 949 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 950                                         NoItinerary, CPURegs>,
 951                      ClearDefs, IsCommutable;
 952
 953 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 954                                           NoItinerary, CPURegs>,
 955                        ClearDefs, IsCommutable;
 956
 957 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 958                                         NoItinerary, CPURegs>, ClearDefs;
 959
 960 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 961                                           NoItinerary, CPURegs>, ClearDefs;
 962
 963 // Comparison
 964 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 965                                                  int_mips_cmpgdu_eq_qb,
 966                                                  NoItinerary, CPURegs, DSPRegs>,
 967                           IsCommutable;
 968
 969 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 970                                                  int_mips_cmpgdu_lt_qb,
 971                                                  NoItinerary, CPURegs, DSPRegs>,
 972                           IsCommutable;
 973
 974 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 975                                                  int_mips_cmpgdu_le_qb,
 976                                                  NoItinerary, CPURegs, DSPRegs>,
 977                           IsCommutable;
 978
 979 // Absolute
 980 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 981                                               NoItinerary, DSPRegs>;
 982
 983 // Multiplication
 984 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 985                                        DSPRegs>, IsCommutable;
 986
 987 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 988                                          NoItinerary, DSPRegs>, IsCommutable;
 989
 990 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 991                                          NoItinerary, CPURegs>, IsCommutable;
 992
 993 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
 994                                           NoItinerary, CPURegs>, IsCommutable;
 995
 996 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
 997                                          NoItinerary, DSPRegs, DSPRegs>,
 998                        IsCommutable;
 999
1000 // Dot product with accumulate/subtract
1001 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1002
1003 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1004
1005 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>;
1006
1007 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1008                                               MipsDPAQX_SA_W_PH>;
1009
1010 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1011
1012 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1013
1014 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>;
1015
1016 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1017                                               MipsDPSQX_SA_W_PH>;
1018
1019 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1020
1021 // Precision reduce/expand
1022 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1023                                                 int_mips_precr_qb_ph,
1024                                                 NoItinerary, DSPRegs, DSPRegs>;
1025
1026 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1027                                                      int_mips_precr_sra_ph_w,
1028                                                      NoItinerary, DSPRegs,
1029                                                      CPURegs>, ClearDefs;
1030
1031 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1032                                                       int_mips_precr_sra_r_ph_w,
1033                                                        NoItinerary, DSPRegs,
1034                                                        CPURegs>, ClearDefs;
1035
1036 // Shift
1037 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1038                                           NoItinerary, DSPRegs>, ClearDefs;
1039
1040 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1041                                            NoItinerary, DSPRegs>, ClearDefs;
1042
1043 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1044                                             immZExt3, NoItinerary, DSPRegs>,
1045                        ClearDefs;
1046
1047 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1048                                              NoItinerary, DSPRegs>, ClearDefs;
1049
1050 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1051                                           NoItinerary, DSPRegs>, ClearDefs;
1052
1053 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1054                                            NoItinerary, DSPRegs>, ClearDefs;
1055
1056 // Misc
1057 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1058                                      NoItinerary>, ClearDefs;
1059
1060 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1061                                      NoItinerary>, ClearDefs;
1062
1063 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1064                                       NoItinerary>, ClearDefs;
1065
1066 // Pseudos.
1067 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
1068
1069 // Instruction defs.
1070 // MIPS DSP Rev 1
1071 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
1072 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1073 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1074 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1075 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
1076 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1077 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1078 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1079 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1080 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1081 def ADDSC : ADDSC_ENC, ADDSC_DESC;
1082 def ADDWC : ADDWC_ENC, ADDWC_DESC;
1083 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1084 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1085 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1086 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1087 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1088 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1089 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1090 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1091 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1092 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1093 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1094 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1095 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1096 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1097 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1098 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1099 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1100 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1101 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1102 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1103 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1104 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1105 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1106 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1107 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1108 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1109 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1110 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1111 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1112 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1113 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1114 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1115 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1116 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1117 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1118 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1119 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1120 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1121 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1122 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1123 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1124 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1125 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1126 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1127 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1128 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1129 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1130 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1131 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1132 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1133 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1134 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1135 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1136 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1137 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1138 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1139 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
1140 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
1141 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
1142 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
1143 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
1144 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1145 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1146 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1147 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1148 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1149 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1150 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1151 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1152 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1153 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1154 def BITREV : BITREV_ENC, BITREV_DESC;
1155 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1156 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1157 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1158 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1159 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1160 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1161 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1162 def LWX : LWX_ENC, LWX_DESC;
1163 def LHX : LHX_ENC, LHX_DESC;
1164 def LBUX : LBUX_ENC, LBUX_DESC;
1165 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1166 def INSV : INSV_ENC, INSV_DESC;
1167 def EXTP : EXTP_ENC, EXTP_DESC;
1168 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1169 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1170 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1171 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1172 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1173 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1174 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1175 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1176 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1177 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1178 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1179 def SHILO : SHILO_ENC, SHILO_DESC;
1180 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1181 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1182 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1183 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1184
1185 // MIPS DSP Rev 2
1186 let Predicates = [HasDSPR2] in {
1187
1188 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1189 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1190 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1191 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1192 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1193 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1194 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1195 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1196 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1197 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1198 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1199 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1200 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1201 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1202 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1203 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1204 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1205 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1206 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1207 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1208 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1209 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1210 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1211 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1212 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1213 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
1214 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1215 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1216 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1217 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1218 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1219 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1220 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1221 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1222 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1223 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1224 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1225 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1226 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1227 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1228 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1229 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1230 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1231 def APPEND : APPEND_ENC, APPEND_DESC;
1232 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1233 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1234
1235 }
1236
1237 // Pseudos.
1238 /// Pseudo instructions for loading, storing and copying accumulator registers.
1239 let isPseudo = 1 in {
1240   defm LOAD_AC_DSP  : LoadM<"load_ac_dsp", ACRegsDSP>;
1241   defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSP>;
1242 }
1243
1244 def COPY_AC_DSP : PseudoSE<(outs ACRegsDSP:$dst), (ins ACRegsDSP:$src), []>;
1245
1246 // Patterns.
1247 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1248   Pat<pattern, result>, Requires<[pred]>;
1249
1250 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1251                     RegisterClass SrcRC> :
1252    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1253           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1254
1255 def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
1256 def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
1257 def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
1258 def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
1259
1260 def : DSPPat<(v2i16 (load addr:$a)),
1261              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1262 def : DSPPat<(v4i8 (load addr:$a)),
1263              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1264 def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
1265              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1266 def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
1267              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1268
1269 // Binary operations.
1270 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1271                 Predicate Pred = HasDSP> :
1272   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1273
1274 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1275 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1276 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1277 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1278 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1279 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1280 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1281 def : DSPBinPat<ADDU_QB, v4i8, add>;
1282 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1283 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1284 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1285 def : DSPBinPat<ADDSC, i32, addc>;
1286 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1287 def : DSPBinPat<ADDWC, i32, adde>;
1288
1289 // Shift immediate patterns.
1290 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1291                   ImmLeaf Imm, Predicate Pred = HasDSP> :
1292   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1293
1294 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, immZExt4>;
1295 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, immZExt4>;
1296 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, immZExt4, HasDSPR2>;
1297 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1298 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1299 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1300 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, immZExt3>;
1301 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, immZExt3, HasDSPR2>;
1302 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, immZExt3>;
1303 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1304 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1305 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1306
1307 // Extr patterns.
1308 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1309   DSPPat<(i32 (OpNode CPURegs:$rs, ACRegsDSP:$ac)),
1310          (Instr ACRegsDSP:$ac, CPURegs:$rs)>;
1311
1312 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1313   DSPPat<(i32 (OpNode immZExt5:$shift, ACRegsDSP:$ac)),
1314          (Instr ACRegsDSP:$ac, immZExt5:$shift)>;
1315
1316 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1317 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1318 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1319 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1320 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1321 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1322 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1323 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1324 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1325 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1326 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1327 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1328
1329 // mflo/hi patterns.
1330 let AddedComplexity = 20 in
1331 def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)),
1332              (EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>;
1333
1334 // Indexed load patterns.
1335 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1336   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1337          (Instr i32:$base, i32:$index)>;
1338
1339 let AddedComplexity = 20 in {
1340   def : IndexedLoadPat<zextloadi8, LBUX>;
1341   def : IndexedLoadPat<sextloadi16, LHX>;
1342   def : IndexedLoadPat<load, LWX>;
1343 }