lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  24                                         SDTCisVT<2, untyped>]>;
  25 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  26                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  27 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  28                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  29
  30 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  31   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  32
  33 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  35
  36 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  37 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  38 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  39 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  40 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  41 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  42
  43 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  44 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  45
  46 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  47 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  48 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  49 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  50 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  51
  52 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  53 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  54 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  55 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  56 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  57 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  58 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  59 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  60
  61 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  62 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  63 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  64 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  65 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  66 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  67 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  68 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  69 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  70
  71 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  72 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  73 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  74 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  75 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  76 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  77
  78 // Flags.
  79 class UseAC {
  80   list<Register> Uses = [AC0];
  81 }
  82
  83 class UseDSPCtrl {
  84   list<Register> Uses = [DSPCtrl];
  85 }
  86
  87 class ClearDefs {
  88   list<Register> Defs = [];
  89 }
  90
  91 // Instruction encoding.
  92 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  93 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  94 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  95 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
  96 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
  97 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
  98 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
  99 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 100 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 101 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 102 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 103 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 104 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 105 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 106 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 107 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 108 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 109 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 110 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 111 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 112 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 113 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 114 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 115 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 116 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 117 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 118 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 119 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 120 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 121 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 122 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 123 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 124 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 125 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 126 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 127 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 128 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 129 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 130 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 131 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 132 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 133 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 134 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 135 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 136 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 137 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 138 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 139 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 140 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 141 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 142 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 143 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 144 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 145 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 146 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 147 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 148 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 149 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 150 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 151 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 152 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 153 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 154 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 155 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 156 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 157 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 158 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 159 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 160 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 161 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 162 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 163 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 164 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 165 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 166 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 167 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 168 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 169 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 170 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 171 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 172 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 173 class REPL_QB_ENC : REPL_FMT<0b00010>;
 174 class REPL_PH_ENC : REPL_FMT<0b01010>;
 175 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 176 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 177 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 178 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 179 class LWX_ENC : LX_FMT<0b00000>;
 180 class LHX_ENC : LX_FMT<0b00100>;
 181 class LBUX_ENC : LX_FMT<0b00110>;
 182 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 183 class INSV_ENC : INSV_FMT<0b001100>;
 184
 185 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 186 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 187 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 188 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 189 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 190 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 191 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 192 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 193 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 194 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 195 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 196 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 197 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 198 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 199 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 200
 201 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 202 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 203 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 204 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 205 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 206 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 207 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 208 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 209 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 210 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 211 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 212 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 213 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 214 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 215 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 216 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 217 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 218 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 219 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 220 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 221 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 222 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 223 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 224 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 225 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 226 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 227 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 228 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 229 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 230 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 231 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 232 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 233 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 234 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 235 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 236 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 237 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 238 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 239 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 240 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 241 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 242 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 243 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 244 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 245 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 246 class APPEND_ENC : APPEND_FMT<0b00000>;
 247 class BALIGN_ENC : APPEND_FMT<0b10000>;
 248 class PREPEND_ENC : APPEND_FMT<0b00001>;
 249
 250 // Instruction desc.
 251 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 252                         InstrItinClass itin, RegisterClass RCD,
 253                         RegisterClass RCS,  RegisterClass RCT = RCS> {
 254   dag OutOperandList = (outs RCD:$rd);
 255   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 256   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 257   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 258   InstrItinClass Itinerary = itin;
 259   list<Register> Defs = [DSPCtrl];
 260 }
 261
 262 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 263                            InstrItinClass itin, RegisterClass RCD,
 264                            RegisterClass RCS = RCD> {
 265   dag OutOperandList = (outs RCD:$rd);
 266   dag InOperandList = (ins RCS:$rs);
 267   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 268   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs))];
 269   InstrItinClass Itinerary = itin;
 270   list<Register> Defs = [DSPCtrl];
 271 }
 272
 273 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 274                              InstrItinClass itin, RegisterClass RCS,
 275                              RegisterClass RCT = RCS> {
 276   dag OutOperandList = (outs);
 277   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 278   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 279   list<dag> Pattern = [(OpNode RCS:$rs, RCT:$rt)];
 280   InstrItinClass Itinerary = itin;
 281   list<Register> Defs = [DSPCtrl];
 282 }
 283
 284 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 285                              InstrItinClass itin, RegisterClass RCD,
 286                              RegisterClass RCS,  RegisterClass RCT = RCS> {
 287   dag OutOperandList = (outs RCD:$rd);
 288   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 289   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 290   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 291   InstrItinClass Itinerary = itin;
 292   list<Register> Defs = [DSPCtrl];
 293 }
 294
 295 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 296                                InstrItinClass itin, RegisterClass RCT,
 297                                RegisterClass RCS = RCT> {
 298   dag OutOperandList = (outs RCT:$rt);
 299   dag InOperandList = (ins RCS:$rs, shamt:$sa, RCS:$src);
 300   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 301   list<dag> Pattern = [(set RCT:$rt, (OpNode RCS:$src, RCS:$rs, immZExt5:$sa))];
 302   InstrItinClass Itinerary = itin;
 303   list<Register> Defs = [DSPCtrl];
 304   string Constraints = "$src = $rt";
 305 }
 306
 307 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 308                              InstrItinClass itin, RegisterClass RCD,
 309                              RegisterClass RCT = RCD> {
 310   dag OutOperandList = (outs RCD:$rd);
 311   dag InOperandList = (ins RCT:$rt);
 312   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 313   list<dag> Pattern = [(set RCD:$rd, (OpNode RCT:$rt))];
 314   InstrItinClass Itinerary = itin;
 315   list<Register> Defs = [DSPCtrl];
 316 }
 317
 318 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 319                      ImmLeaf immPat, InstrItinClass itin, RegisterClass RC> {
 320   dag OutOperandList = (outs RC:$rd);
 321   dag InOperandList = (ins uimm16:$imm);
 322   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 323   list<dag> Pattern = [(set RC:$rd, (OpNode immPat:$imm))];
 324   InstrItinClass Itinerary = itin;
 325   list<Register> Defs = [DSPCtrl];
 326 }
 327
 328 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 329                            InstrItinClass itin, RegisterClass RC> {
 330   dag OutOperandList = (outs RC:$rd);
 331   dag InOperandList =  (ins RC:$rt, CPURegs:$rs_sa);
 332   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 333   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs_sa))];
 334   InstrItinClass Itinerary = itin;
 335   list<Register> Defs = [DSPCtrl];
 336 }
 337
 338 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 339                            SDPatternOperator ImmPat, InstrItinClass itin,
 340                            RegisterClass RC> {
 341   dag OutOperandList = (outs RC:$rd);
 342   dag InOperandList = (ins RC:$rt, uimm16:$rs_sa);
 343   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 344   list<dag> Pattern = [(set RC:$rd, (OpNode RC:$rt, ImmPat:$rs_sa))];
 345   InstrItinClass Itinerary = itin;
 346   list<Register> Defs = [DSPCtrl];
 347 }
 348
 349 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 350                    InstrItinClass itin> {
 351   dag OutOperandList = (outs CPURegs:$rd);
 352   dag InOperandList = (ins CPURegs:$base, CPURegs:$index);
 353   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 354   list<dag> Pattern = [(set CPURegs:$rd,
 355                        (OpNode CPURegs:$base, CPURegs:$index))];
 356   InstrItinClass Itinerary = itin;
 357   list<Register> Defs = [DSPCtrl];
 358   bit mayLoad = 1;
 359 }
 360
 361 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 362                          InstrItinClass itin, RegisterClass RCD,
 363                          RegisterClass RCS = RCD,  RegisterClass RCT = RCD> {
 364   dag OutOperandList = (outs RCD:$rd);
 365   dag InOperandList = (ins RCS:$rs, RCT:$rt);
 366   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 367   list<dag> Pattern = [(set RCD:$rd, (OpNode RCS:$rs, RCT:$rt))];
 368   InstrItinClass Itinerary = itin;
 369   list<Register> Defs = [DSPCtrl];
 370 }
 371
 372 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 373                        SDPatternOperator ImmOp, InstrItinClass itin> {
 374   dag OutOperandList = (outs CPURegs:$rt);
 375   dag InOperandList = (ins CPURegs:$rs, shamt:$sa, CPURegs:$src);
 376   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 377   list<dag> Pattern =  [(set CPURegs:$rt,
 378                         (OpNode CPURegs:$src, CPURegs:$rs, ImmOp:$sa))];
 379   InstrItinClass Itinerary = itin;
 380   list<Register> Defs = [DSPCtrl];
 381   string Constraints = "$src = $rt";
 382 }
 383
 384 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 385                               InstrItinClass itin> {
 386   dag OutOperandList = (outs CPURegs:$rt);
 387   dag InOperandList = (ins ACRegsDSP:$ac, CPURegs:$shift_rs);
 388   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 389   InstrItinClass Itinerary = itin;
 390   list<Register> Defs = [DSPCtrl];
 391 }
 392
 393 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 394                               InstrItinClass itin> {
 395   dag OutOperandList = (outs CPURegs:$rt);
 396   dag InOperandList = (ins ACRegsDSP:$ac, uimm16:$shift_rs);
 397   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 398   InstrItinClass Itinerary = itin;
 399   list<Register> Defs = [DSPCtrl];
 400 }
 401
 402 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 403   dag OutOperandList = (outs ACRegsDSP:$ac);
 404   dag InOperandList = (ins simm16:$shift, ACRegsDSP:$acin);
 405   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 406   list<dag> Pattern = [(set ACRegsDSP:$ac,
 407                         (OpNode immSExt6:$shift, ACRegsDSP:$acin))];
 408   list<Register> Defs = [DSPCtrl];
 409   string Constraints = "$acin = $ac";
 410 }
 411
 412 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 413   dag OutOperandList = (outs ACRegsDSP:$ac);
 414   dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin);
 415   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 416   list<dag> Pattern = [(set ACRegsDSP:$ac,
 417                         (OpNode CPURegs:$rs, ACRegsDSP:$acin))];
 418   list<Register> Defs = [DSPCtrl];
 419   string Constraints = "$acin = $ac";
 420 }
 421
 422 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 423   dag OutOperandList = (outs ACRegsDSP:$ac);
 424   dag InOperandList = (ins CPURegs:$rs, ACRegsDSP:$acin);
 425   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 426   list<dag> Pattern = [(set ACRegsDSP:$ac,
 427                         (OpNode CPURegs:$rs, ACRegsDSP:$acin))];
 428   list<Register> Uses = [DSPCtrl];
 429   string Constraints = "$acin = $ac";
 430 }
 431
 432 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 433                       InstrItinClass itin> {
 434   dag OutOperandList = (outs CPURegs:$rd);
 435   dag InOperandList = (ins uimm16:$mask);
 436   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 437   list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))];
 438   InstrItinClass Itinerary = itin;
 439   list<Register> Uses = [DSPCtrl];
 440 }
 441
 442 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 443                       InstrItinClass itin> {
 444   dag OutOperandList = (outs);
 445   dag InOperandList = (ins CPURegs:$rs, uimm16:$mask);
 446   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 447   list<dag> Pattern = [(OpNode CPURegs:$rs, immZExt10:$mask)];
 448   InstrItinClass Itinerary = itin;
 449   list<Register> Defs = [DSPCtrl];
 450 }
 451
 452 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 453   dag OutOperandList = (outs ACRegsDSP:$ac);
 454   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin);
 455   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 456   list<dag> Pattern = [(set ACRegsDSP:$ac,
 457                         (OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))];
 458   list<Register> Defs = [DSPCtrl];
 459   string Constraints = "$acin = $ac";
 460 }
 461
 462 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 463                      InstrItinClass itin> {
 464   dag OutOperandList = (outs ACRegsDSP:$ac);
 465   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt);
 466   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 467   list<dag> Pattern = [(set ACRegsDSP:$ac, (OpNode CPURegs:$rs, CPURegs:$rt))];
 468   InstrItinClass Itinerary = itin;
 469   int AddedComplexity = 20;
 470   bit isCommutable = 1;
 471 }
 472
 473 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 474                      InstrItinClass itin> {
 475   dag OutOperandList = (outs ACRegsDSP:$ac);
 476   dag InOperandList = (ins CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin);
 477   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 478   list<dag> Pattern = [(set ACRegsDSP:$ac,
 479                         (OpNode CPURegs:$rs, CPURegs:$rt, ACRegsDSP:$acin))];
 480   InstrItinClass Itinerary = itin;
 481   int AddedComplexity = 20;
 482   string Constraints = "$acin = $ac";
 483 }
 484
 485 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 486   MipsPseudo<(outs CPURegs:$dst), (ins), [(set CPURegs:$dst, (OpNode))]> {
 487   list<Register> Uses = [DSPCtrl];
 488   bit usesCustomInserter = 1;
 489 }
 490
 491 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 492   dag OutOperandList = (outs);
 493   dag InOperandList = (ins brtarget:$offset);
 494   string AsmString = !strconcat(instr_asm, "\t$offset");
 495   InstrItinClass Itinerary = itin;
 496   list<Register> Uses = [DSPCtrl];
 497   bit isBranch = 1;
 498   bit isTerminator = 1;
 499   bit hasDelaySlot = 1;
 500 }
 501
 502 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 503                      InstrItinClass itin> {
 504   dag OutOperandList = (outs CPURegs:$rt);
 505   dag InOperandList = (ins CPURegs:$src, CPURegs:$rs);
 506   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 507   list<dag> Pattern = [(set CPURegs:$rt, (OpNode CPURegs:$src, CPURegs:$rs))];
 508   InstrItinClass Itinerary = itin;
 509   list<Register> Uses = [DSPCtrl];
 510   string Constraints = "$src = $rt";
 511 }
 512
 513 //===----------------------------------------------------------------------===//
 514 // MIPS DSP Rev 1
 515 //===----------------------------------------------------------------------===//
 516
 517 // Addition/subtraction
 518 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 519                                        DSPRegs, DSPRegs>, IsCommutable;
 520
 521 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 522                                          NoItinerary, DSPRegs, DSPRegs>,
 523                        IsCommutable;
 524
 525 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 526                                        DSPRegs, DSPRegs>;
 527
 528 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 529                                          NoItinerary, DSPRegs, DSPRegs>;
 530
 531 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 532                                        DSPRegs, DSPRegs>, IsCommutable;
 533
 534 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 535                                          NoItinerary, DSPRegs, DSPRegs>,
 536                        IsCommutable;
 537
 538 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 539                                        DSPRegs, DSPRegs>;
 540
 541 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 542                                          NoItinerary, DSPRegs, DSPRegs>;
 543
 544 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 545                                         NoItinerary, CPURegs, CPURegs>,
 546                       IsCommutable;
 547
 548 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 549                                         NoItinerary, CPURegs, CPURegs>;
 550
 551 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 552                                      CPURegs, CPURegs>, IsCommutable;
 553
 554 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 555                                      CPURegs, CPURegs>,
 556                    IsCommutable, UseDSPCtrl;
 557
 558 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 559                                       CPURegs, CPURegs>, ClearDefs;
 560
 561 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 562                                              NoItinerary, CPURegs, DSPRegs>,
 563                         ClearDefs;
 564
 565 // Absolute value
 566 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 567                                               NoItinerary, DSPRegs>;
 568
 569 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 570                                              NoItinerary, CPURegs>;
 571
 572 // Precision reduce/expand
 573 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 574                                                  int_mips_precrq_qb_ph,
 575                                                  NoItinerary, DSPRegs, DSPRegs>,
 576                           ClearDefs;
 577
 578 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 579                                                 int_mips_precrq_ph_w,
 580                                                 NoItinerary, DSPRegs, CPURegs>,
 581                          ClearDefs;
 582
 583 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 584                                                    int_mips_precrq_rs_ph_w,
 585                                                    NoItinerary, DSPRegs,
 586                                                    CPURegs>;
 587
 588 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 589                                                     int_mips_precrqu_s_qb_ph,
 590                                                     NoItinerary, DSPRegs,
 591                                                     DSPRegs>;
 592
 593 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 594                                                  int_mips_preceq_w_phl,
 595                                                  NoItinerary, CPURegs, DSPRegs>,
 596                           ClearDefs;
 597
 598 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 599                                                  int_mips_preceq_w_phr,
 600                                                  NoItinerary, CPURegs, DSPRegs>,
 601                           ClearDefs;
 602
 603 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 604                                                    int_mips_precequ_ph_qbl,
 605                                                    NoItinerary, DSPRegs>,
 606                             ClearDefs;
 607
 608 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 609                                                    int_mips_precequ_ph_qbr,
 610                                                    NoItinerary, DSPRegs>,
 611                             ClearDefs;
 612
 613 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 614                                                     int_mips_precequ_ph_qbla,
 615                                                     NoItinerary, DSPRegs>,
 616                              ClearDefs;
 617
 618 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 619                                                     int_mips_precequ_ph_qbra,
 620                                                     NoItinerary, DSPRegs>,
 621                              ClearDefs;
 622
 623 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 624                                                   int_mips_preceu_ph_qbl,
 625                                                   NoItinerary, DSPRegs>,
 626                            ClearDefs;
 627
 628 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 629                                                   int_mips_preceu_ph_qbr,
 630                                                   NoItinerary, DSPRegs>,
 631                            ClearDefs;
 632
 633 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 634                                                    int_mips_preceu_ph_qbla,
 635                                                    NoItinerary, DSPRegs>,
 636                             ClearDefs;
 637
 638 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 639                                                    int_mips_preceu_ph_qbra,
 640                                                    NoItinerary, DSPRegs>,
 641                             ClearDefs;
 642
 643 // Shift
 644 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", int_mips_shll_qb, immZExt3,
 645                                           NoItinerary, DSPRegs>;
 646
 647 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 648                                            NoItinerary, DSPRegs>;
 649
 650 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", int_mips_shrl_qb, immZExt3,
 651                                           NoItinerary, DSPRegs>, ClearDefs;
 652
 653 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 654                                            NoItinerary, DSPRegs>, ClearDefs;
 655
 656 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", int_mips_shll_ph, immZExt4,
 657                                           NoItinerary, DSPRegs>;
 658
 659 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 660                                            NoItinerary, DSPRegs>;
 661
 662 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 663                                             immZExt4, NoItinerary, DSPRegs>;
 664
 665 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 666                                              NoItinerary, DSPRegs>;
 667
 668 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", int_mips_shra_ph, immZExt4,
 669                                           NoItinerary, DSPRegs>, ClearDefs;
 670
 671 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 672                                            NoItinerary, DSPRegs>, ClearDefs;
 673
 674 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 675                                             immZExt4, NoItinerary, DSPRegs>,
 676                        ClearDefs;
 677
 678 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 679                                              NoItinerary, DSPRegs>, ClearDefs;
 680
 681 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 682                                            immZExt5, NoItinerary, CPURegs>;
 683
 684 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 685                                             NoItinerary, CPURegs>;
 686
 687 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 688                                            immZExt5, NoItinerary, CPURegs>,
 689                       ClearDefs;
 690
 691 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 692                                             NoItinerary, CPURegs>;
 693
 694 // Multiplication
 695 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 696                                               int_mips_muleu_s_ph_qbl,
 697                                               NoItinerary, DSPRegs, DSPRegs>;
 698
 699 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 700                                               int_mips_muleu_s_ph_qbr,
 701                                               NoItinerary, DSPRegs, DSPRegs>;
 702
 703 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 704                                              int_mips_muleq_s_w_phl,
 705                                              NoItinerary, CPURegs, DSPRegs>,
 706                            IsCommutable;
 707
 708 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 709                                              int_mips_muleq_s_w_phr,
 710                                              NoItinerary, CPURegs, DSPRegs>,
 711                            IsCommutable;
 712
 713 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 714                                           NoItinerary, DSPRegs, DSPRegs>,
 715                         IsCommutable;
 716
 717 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 718                                               MipsMULSAQ_S_W_PH>;
 719
 720 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>;
 721
 722 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>;
 723
 724 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>;
 725
 726 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>;
 727
 728 // Dot product with accumulate/subtract
 729 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 730
 731 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 732
 733 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 734
 735 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 736
 737 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>;
 738
 739 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>;
 740
 741 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>;
 742
 743 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>;
 744
 745 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 746 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 747 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 748 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 749 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 750 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 751
 752 // Comparison
 753 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 754                                                int_mips_cmpu_eq_qb, NoItinerary,
 755                                                DSPRegs>, IsCommutable;
 756
 757 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 758                                                int_mips_cmpu_lt_qb, NoItinerary,
 759                                                DSPRegs>, IsCommutable;
 760
 761 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 762                                                int_mips_cmpu_le_qb, NoItinerary,
 763                                                DSPRegs>, IsCommutable;
 764
 765 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 766                                                 int_mips_cmpgu_eq_qb,
 767                                                 NoItinerary, CPURegs, DSPRegs>,
 768                          IsCommutable;
 769
 770 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 771                                                 int_mips_cmpgu_lt_qb,
 772                                                 NoItinerary, CPURegs, DSPRegs>,
 773                          IsCommutable;
 774
 775 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 776                                                 int_mips_cmpgu_le_qb,
 777                                                 NoItinerary, CPURegs, DSPRegs>,
 778                          IsCommutable;
 779
 780 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 781                                               NoItinerary, DSPRegs>,
 782                        IsCommutable;
 783
 784 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 785                                               NoItinerary, DSPRegs>,
 786                        IsCommutable;
 787
 788 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 789                                               NoItinerary, DSPRegs>,
 790                        IsCommutable;
 791
 792 // Misc
 793 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 794                                            NoItinerary, CPURegs>, ClearDefs;
 795
 796 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 797                                               NoItinerary, DSPRegs, DSPRegs>,
 798                        ClearDefs;
 799
 800 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 801                                     NoItinerary, DSPRegs>, ClearDefs;
 802
 803 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 804                                     NoItinerary, DSPRegs>, ClearDefs;
 805
 806 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 807                                              NoItinerary, DSPRegs, CPURegs>,
 808                       ClearDefs;
 809
 810 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 811                                              NoItinerary, DSPRegs, CPURegs>,
 812                       ClearDefs;
 813
 814 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 815                                             NoItinerary, DSPRegs, DSPRegs>,
 816                      ClearDefs, UseDSPCtrl;
 817
 818 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 819                                             NoItinerary, DSPRegs, DSPRegs>,
 820                      ClearDefs, UseDSPCtrl;
 821
 822 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>, ClearDefs;
 823
 824 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>, ClearDefs;
 825
 826 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>, ClearDefs;
 827
 828 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 829
 830 // Extr
 831 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
 832
 833 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>;
 834
 835 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>;
 836
 837 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 838                                              NoItinerary>;
 839
 840 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>;
 841
 842 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 843                                              NoItinerary>;
 844
 845 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 846                                               NoItinerary>;
 847
 848 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 849                                                NoItinerary>;
 850
 851 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 852                                                NoItinerary>;
 853
 854 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 855                                                 NoItinerary>;
 856
 857 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 858                                               NoItinerary>;
 859
 860 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 861                                                NoItinerary>;
 862
 863 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 864
 865 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 866
 867 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>;
 868
 869 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 870
 871 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 872
 873 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>;
 874
 875 //===----------------------------------------------------------------------===//
 876 // MIPS DSP Rev 2
 877 // Addition/subtraction
 878 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 879                                        DSPRegs, DSPRegs>, IsCommutable;
 880
 881 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 882                                          NoItinerary, DSPRegs, DSPRegs>,
 883                        IsCommutable;
 884
 885 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 886                                        DSPRegs, DSPRegs>;
 887
 888 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 889                                          NoItinerary, DSPRegs, DSPRegs>;
 890
 891 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 892                                          NoItinerary, DSPRegs>,
 893                       ClearDefs, IsCommutable;
 894
 895 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 896                                            NoItinerary, DSPRegs>,
 897                         ClearDefs, IsCommutable;
 898
 899 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 900                                          NoItinerary, DSPRegs>, ClearDefs;
 901
 902 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 903                                            NoItinerary, DSPRegs>, ClearDefs;
 904
 905 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 906                                          NoItinerary, DSPRegs>,
 907                       ClearDefs, IsCommutable;
 908
 909 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 910                                            NoItinerary, DSPRegs>,
 911                         ClearDefs, IsCommutable;
 912
 913 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 914                                          NoItinerary, DSPRegs>, ClearDefs;
 915
 916 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 917                                            NoItinerary, DSPRegs>, ClearDefs;
 918
 919 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 920                                         NoItinerary, CPURegs>,
 921                      ClearDefs, IsCommutable;
 922
 923 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 924                                           NoItinerary, CPURegs>,
 925                        ClearDefs, IsCommutable;
 926
 927 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 928                                         NoItinerary, CPURegs>, ClearDefs;
 929
 930 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 931                                           NoItinerary, CPURegs>, ClearDefs;
 932
 933 // Comparison
 934 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 935                                                  int_mips_cmpgdu_eq_qb,
 936                                                  NoItinerary, CPURegs, DSPRegs>,
 937                           IsCommutable;
 938
 939 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 940                                                  int_mips_cmpgdu_lt_qb,
 941                                                  NoItinerary, CPURegs, DSPRegs>,
 942                           IsCommutable;
 943
 944 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 945                                                  int_mips_cmpgdu_le_qb,
 946                                                  NoItinerary, CPURegs, DSPRegs>,
 947                           IsCommutable;
 948
 949 // Absolute
 950 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 951                                               NoItinerary, DSPRegs>;
 952
 953 // Multiplication
 954 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 955                                        DSPRegs>, IsCommutable;
 956
 957 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 958                                          NoItinerary, DSPRegs>, IsCommutable;
 959
 960 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 961                                          NoItinerary, CPURegs>, IsCommutable;
 962
 963 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
 964                                           NoItinerary, CPURegs>, IsCommutable;
 965
 966 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
 967                                          NoItinerary, DSPRegs, DSPRegs>,
 968                        IsCommutable;
 969
 970 // Dot product with accumulate/subtract
 971 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
 972
 973 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
 974
 975 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>;
 976
 977 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
 978                                               MipsDPAQX_SA_W_PH>;
 979
 980 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
 981
 982 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
 983
 984 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>;
 985
 986 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
 987                                               MipsDPSQX_SA_W_PH>;
 988
 989 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
 990
 991 // Precision reduce/expand
 992 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
 993                                                 int_mips_precr_qb_ph,
 994                                                 NoItinerary, DSPRegs, DSPRegs>;
 995
 996 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
 997                                                      int_mips_precr_sra_ph_w,
 998                                                      NoItinerary, DSPRegs,
 999                                                      CPURegs>, ClearDefs;
1000
1001 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1002                                                       int_mips_precr_sra_r_ph_w,
1003                                                        NoItinerary, DSPRegs,
1004                                                        CPURegs>, ClearDefs;
1005
1006 // Shift
1007 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", int_mips_shra_qb, immZExt3,
1008                                           NoItinerary, DSPRegs>, ClearDefs;
1009
1010 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1011                                            NoItinerary, DSPRegs>, ClearDefs;
1012
1013 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1014                                             immZExt3, NoItinerary, DSPRegs>,
1015                        ClearDefs;
1016
1017 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1018                                              NoItinerary, DSPRegs>, ClearDefs;
1019
1020 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", int_mips_shrl_ph, immZExt4,
1021                                           NoItinerary, DSPRegs>, ClearDefs;
1022
1023 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1024                                            NoItinerary, DSPRegs>, ClearDefs;
1025
1026 // Misc
1027 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1028                                      NoItinerary>, ClearDefs;
1029
1030 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1031                                      NoItinerary>, ClearDefs;
1032
1033 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1034                                       NoItinerary>, ClearDefs;
1035
1036 // Pseudos.
1037 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
1038
1039 // Instruction defs.
1040 // MIPS DSP Rev 1
1041 def ADDU_QB : ADDU_QB_ENC, ADDU_QB_DESC;
1042 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1043 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1044 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1045 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
1046 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1047 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1048 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1049 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1050 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1051 def ADDSC : ADDSC_ENC, ADDSC_DESC;
1052 def ADDWC : ADDWC_ENC, ADDWC_DESC;
1053 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1054 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1055 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1056 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1057 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1058 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1059 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1060 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1061 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1062 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1063 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1064 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1065 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1066 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1067 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1068 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1069 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1070 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1071 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1072 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1073 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1074 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1075 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1076 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1077 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1078 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1079 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1080 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1081 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1082 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1083 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1084 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1085 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1086 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1087 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1088 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1089 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1090 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1091 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1092 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1093 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1094 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1095 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1096 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1097 def DPAU_H_QBL : DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1098 def DPAU_H_QBR : DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1099 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1100 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1101 def DPAQ_S_W_PH : DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1102 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1103 def DPAQ_SA_L_W : DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1104 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1105 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
1106 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
1107 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
1108 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
1109 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
1110 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1111 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1112 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1113 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1114 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1115 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1116 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1117 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1118 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1119 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1120 def BITREV : BITREV_ENC, BITREV_DESC;
1121 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1122 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1123 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1124 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1125 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1126 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1127 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1128 def LWX : LWX_ENC, LWX_DESC;
1129 def LHX : LHX_ENC, LHX_DESC;
1130 def LBUX : LBUX_ENC, LBUX_DESC;
1131 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1132 def INSV : INSV_ENC, INSV_DESC;
1133 def EXTP : EXTP_ENC, EXTP_DESC;
1134 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1135 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1136 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1137 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1138 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1139 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1140 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1141 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1142 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1143 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1144 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1145 def SHILO : SHILO_ENC, SHILO_DESC;
1146 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1147 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1148 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1149 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1150
1151 // MIPS DSP Rev 2
1152 let Predicates = [HasDSPR2] in {
1153
1154 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1155 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1156 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1157 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1158 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1159 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1160 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1161 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1162 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1163 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1164 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1165 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1166 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1167 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1168 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1169 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1170 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1171 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1172 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1173 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1174 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1175 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1176 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1177 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1178 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1179 def DPA_W_PH : DPA_W_PH_ENC, DPA_W_PH_DESC;
1180 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1181 def DPAQX_S_W_PH : DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1182 def DPAQX_SA_W_PH : DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1183 def DPAX_W_PH : DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1184 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1185 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1186 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1187 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1188 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1189 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1190 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1191 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1192 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1193 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1194 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1195 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1196 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1197 def APPEND : APPEND_ENC, APPEND_DESC;
1198 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1199 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1200
1201 }
1202
1203 // Pseudos.
1204 /// Pseudo instructions for loading, storing and copying accumulator registers.
1205 let isPseudo = 1 in {
1206   defm LOAD_AC_DSP  : LoadM<"load_ac_dsp", ACRegsDSP>;
1207   defm STORE_AC_DSP : StoreM<"store_ac_dsp", ACRegsDSP>;
1208 }
1209
1210 def COPY_AC_DSP : PseudoSE<(outs ACRegsDSP:$dst), (ins ACRegsDSP:$src), []>;
1211
1212 // Patterns.
1213 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1214   Pat<pattern, result>, Requires<[pred]>;
1215
1216 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1217                     RegisterClass SrcRC> :
1218    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1219           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1220
1221 def : BitconvertPat<i32, v2i16, CPURegs, DSPRegs>;
1222 def : BitconvertPat<i32, v4i8, CPURegs, DSPRegs>;
1223 def : BitconvertPat<v2i16, i32, DSPRegs, CPURegs>;
1224 def : BitconvertPat<v4i8, i32, DSPRegs, CPURegs>;
1225
1226 def : DSPPat<(v2i16 (load addr:$a)),
1227              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1228 def : DSPPat<(v4i8 (load addr:$a)),
1229              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPRegs))>;
1230 def : DSPPat<(store (v2i16 DSPRegs:$val), addr:$a),
1231              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1232 def : DSPPat<(store (v4i8 DSPRegs:$val), addr:$a),
1233              (SW (COPY_TO_REGCLASS DSPRegs:$val, CPURegs), addr:$a)>;
1234
1235 // Binary operations.
1236 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1237                 Predicate Pred = HasDSP> :
1238   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1239
1240 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1241 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1242 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1243 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1244 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1245 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1246 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1247 def : DSPBinPat<ADDU_QB, v4i8, add>;
1248 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1249 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1250 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1251 def : DSPBinPat<ADDSC, i32, addc>;
1252 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1253 def : DSPBinPat<ADDWC, i32, adde>;
1254
1255 // Extr patterns.
1256 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1257   DSPPat<(i32 (OpNode CPURegs:$rs, ACRegsDSP:$ac)),
1258          (Instr ACRegsDSP:$ac, CPURegs:$rs)>;
1259
1260 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1261   DSPPat<(i32 (OpNode immZExt5:$shift, ACRegsDSP:$ac)),
1262          (Instr ACRegsDSP:$ac, immZExt5:$shift)>;
1263
1264 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1265 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1266 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1267 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1268 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1269 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1270 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1271 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1272 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1273 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1274 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1275 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1276
1277 // mflo/hi patterns.
1278 let AddedComplexity = 20 in
1279 def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)),
1280              (EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>;
1281
1282 // Indexed load patterns.
1283 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1284   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1285          (Instr i32:$base, i32:$index)>;
1286
1287 let AddedComplexity = 20 in {
1288   def : IndexedLoadPat<zextloadi8, LBUX>;
1289   def : IndexedLoadPat<sextloadi16, LHX>;
1290   def : IndexedLoadPat<load, LWX>;
1291 }