lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  16 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  17 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  18 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  19 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  20 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  21
  22 // Mips-specific dsp nodes
  23 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  24                                         SDTCisVT<2, untyped>]>;
  25 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  26                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  27 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  28                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  29 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  30                                              SDTCisVT<2, i32>]>;
  31
  32 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  33   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  34
  35 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  36   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  37
  38 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  39 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  40 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  41 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  42 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  43 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  44
  45 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  46 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  47
  48 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  49 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  51 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  53
  54 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  55 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  56 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  58 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  59 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  61 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  62
  63 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  64 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  65 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  67 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  68 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  71 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  72
  73 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  74 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  75 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  76 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  77 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  78 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  79 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  80 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  83 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  84
  85 // Flags.
  86 class Uses<list<Register> Regs> {
  87   list<Register> Uses = Regs;
  88 }
  89
  90 class Defs<list<Register> Regs> {
  91   list<Register> Defs = Regs;
  92 }
  93
  94 // Instruction encoding.
  95 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  96 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  97 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  98 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
  99 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 100 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 101 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 102 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 103 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 104 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 105 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 106 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 107 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 108 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 109 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 110 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 111 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 112 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 113 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 114 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 115 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 116 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 117 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 118 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 119 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 120 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 121 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 122 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 123 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 124 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 125 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 126 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 127 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 128 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 129 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 130 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 131 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 132 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 133 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 134 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 135 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 136 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 137 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 138 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 139 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 140 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 141 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 142 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 143 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 144 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 145 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 146 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 147 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 148 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 149 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 150 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 151 class MFHI_ENC : MFHI_FMT<0b010000>;
 152 class MFLO_ENC : MFHI_FMT<0b010010>;
 153 class MTHI_ENC : MTHI_FMT<0b010001>;
 154 class MTLO_ENC : MTHI_FMT<0b010011>;
 155 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 156 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 157 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 158 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 159 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 160 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 161 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 162 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 163 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 164 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 165 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 166 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 167 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 168 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 169 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 170 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 171 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 172 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 173 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 174 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 175 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 176 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 177 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 178 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 179 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 180 class REPL_QB_ENC : REPL_FMT<0b00010>;
 181 class REPL_PH_ENC : REPL_FMT<0b01010>;
 182 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 183 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 184 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 185 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 186 class LWX_ENC : LX_FMT<0b00000>;
 187 class LHX_ENC : LX_FMT<0b00100>;
 188 class LBUX_ENC : LX_FMT<0b00110>;
 189 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 190 class INSV_ENC : INSV_FMT<0b001100>;
 191
 192 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 193 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 194 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 195 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 196 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 197 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 198 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 199 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 200 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 201 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 202 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 203 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 204 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 205 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 206 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 207
 208 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 209 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 210 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 211 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 212 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 213 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 214 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 215 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 216 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 217 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 218 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 219 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 220 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 221 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 222 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 223 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 224 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 225 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 226 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 227 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 228 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 229 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 230 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 231 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 232 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 233 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 234 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 235 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 236 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 237 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 238 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 239 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 240 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 241 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 242 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 243 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 244 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 245 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 246 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 247 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 248 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 249 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 250 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 251 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 252 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 253 class APPEND_ENC : APPEND_FMT<0b00000>;
 254 class BALIGN_ENC : APPEND_FMT<0b10000>;
 255 class PREPEND_ENC : APPEND_FMT<0b00001>;
 256
 257 // Instruction desc.
 258 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 259                         InstrItinClass itin, RegisterOperand ROD,
 260                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 261   dag OutOperandList = (outs ROD:$rd);
 262   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 263   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 264   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 265   InstrItinClass Itinerary = itin;
 266   string BaseOpcode = instr_asm;
 267 }
 268
 269 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 270                            InstrItinClass itin, RegisterOperand ROD,
 271                            RegisterOperand ROS = ROD> {
 272   dag OutOperandList = (outs ROD:$rd);
 273   dag InOperandList = (ins ROS:$rs);
 274   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 275   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 276   InstrItinClass Itinerary = itin;
 277 }
 278
 279 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 280                              InstrItinClass itin, RegisterOperand ROS,
 281                              RegisterOperand ROT = ROS> {
 282   dag OutOperandList = (outs);
 283   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 284   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 285   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 286   InstrItinClass Itinerary = itin;
 287 }
 288
 289 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 290                              InstrItinClass itin, RegisterOperand ROD,
 291                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 292   dag OutOperandList = (outs ROD:$rd);
 293   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 294   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 295   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 296   InstrItinClass Itinerary = itin;
 297 }
 298
 299 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 300                                InstrItinClass itin, RegisterOperand ROT,
 301                                RegisterOperand ROS = ROT> {
 302   dag OutOperandList = (outs ROT:$rt);
 303   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 304   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 305   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 306   InstrItinClass Itinerary = itin;
 307   string Constraints = "$src = $rt";
 308 }
 309
 310 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 311                              InstrItinClass itin, RegisterOperand ROD,
 312                              RegisterOperand ROT = ROD> {
 313   dag OutOperandList = (outs ROD:$rd);
 314   dag InOperandList = (ins ROT:$rt);
 315   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 316   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 317   InstrItinClass Itinerary = itin;
 318 }
 319
 320 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 321                      ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
 322   dag OutOperandList = (outs RO:$rd);
 323   dag InOperandList = (ins uimm16:$imm);
 324   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 325   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 326   InstrItinClass Itinerary = itin;
 327 }
 328
 329 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 330                            InstrItinClass itin, RegisterOperand RO> {
 331   dag OutOperandList = (outs RO:$rd);
 332   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 333   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 334   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 335   InstrItinClass Itinerary = itin;
 336 }
 337
 338 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 339                            SDPatternOperator ImmPat, InstrItinClass itin,
 340                            RegisterOperand RO> {
 341   dag OutOperandList = (outs RO:$rd);
 342   dag InOperandList = (ins RO:$rt, uimm16:$rs_sa);
 343   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 344   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 345   InstrItinClass Itinerary = itin;
 346   bit hasSideEffects = 1;
 347 }
 348
 349 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 350                    InstrItinClass itin> {
 351   dag OutOperandList = (outs GPR32Opnd:$rd);
 352   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 353   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 354   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 355   InstrItinClass Itinerary = itin;
 356   bit mayLoad = 1;
 357 }
 358
 359 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 360                          InstrItinClass itin, RegisterOperand ROD,
 361                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 362   dag OutOperandList = (outs ROD:$rd);
 363   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 364   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 365   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 366   InstrItinClass Itinerary = itin;
 367 }
 368
 369 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 370                        SDPatternOperator ImmOp, InstrItinClass itin> {
 371   dag OutOperandList = (outs GPR32Opnd:$rt);
 372   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src);
 373   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 374   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 375                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))];
 376   InstrItinClass Itinerary = itin;
 377   string Constraints = "$src = $rt";
 378 }
 379
 380 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 381                               InstrItinClass itin> {
 382   dag OutOperandList = (outs GPR32Opnd:$rt);
 383   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 384   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 385   InstrItinClass Itinerary = itin;
 386 }
 387
 388 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 389                               InstrItinClass itin> {
 390   dag OutOperandList = (outs GPR32Opnd:$rt);
 391   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
 392   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 393   InstrItinClass Itinerary = itin;
 394 }
 395
 396 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 397   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 398   dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
 399   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 400   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 401                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 402   string Constraints = "$acin = $ac";
 403 }
 404
 405 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 406   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 407   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 408   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 409   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 410                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 411   string Constraints = "$acin = $ac";
 412 }
 413
 414 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 415   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 416   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 417   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 418   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 419                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 420   string Constraints = "$acin = $ac";
 421 }
 422
 423 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 424                       InstrItinClass itin> {
 425   dag OutOperandList = (outs GPR32Opnd:$rd);
 426   dag InOperandList = (ins uimm16:$mask);
 427   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 428   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 429   InstrItinClass Itinerary = itin;
 430 }
 431
 432 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 433                       InstrItinClass itin> {
 434   dag OutOperandList = (outs);
 435   dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
 436   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 437   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 438   InstrItinClass Itinerary = itin;
 439 }
 440
 441 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 442   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 443   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 444   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 445   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 446                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 447   string Constraints = "$acin = $ac";
 448   string BaseOpcode = instr_asm;
 449 }
 450
 451 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 452                      InstrItinClass itin> {
 453   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 454   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 455   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 456   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 457   InstrItinClass Itinerary = itin;
 458   bit isCommutable = 1;
 459 }
 460
 461 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 462                      InstrItinClass itin> {
 463   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 464   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 465   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 466   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 467                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 468   InstrItinClass Itinerary = itin;
 469   string Constraints = "$acin = $ac";
 470 }
 471
 472 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 473                      InstrItinClass itin> {
 474   dag OutOperandList = (outs GPR32Opnd:$rd);
 475   dag InOperandList = (ins RO:$ac);
 476   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 477   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 478   InstrItinClass Itinerary = itin;
 479 }
 480
 481 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 482   dag OutOperandList = (outs RO:$ac);
 483   dag InOperandList = (ins GPR32Opnd:$rs);
 484   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 485   InstrItinClass Itinerary = itin;
 486 }
 487
 488 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 489   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 490   bit usesCustomInserter = 1;
 491 }
 492
 493 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 494   dag OutOperandList = (outs);
 495   dag InOperandList = (ins brtarget:$offset);
 496   string AsmString = !strconcat(instr_asm, "\t$offset");
 497   InstrItinClass Itinerary = itin;
 498   bit isBranch = 1;
 499   bit isTerminator = 1;
 500   bit hasDelaySlot = 1;
 501 }
 502
 503 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 504                      InstrItinClass itin> {
 505   dag OutOperandList = (outs GPR32Opnd:$rt);
 506   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 507   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 508   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 509   InstrItinClass Itinerary = itin;
 510   string Constraints = "$src = $rt";
 511 }
 512
 513 //===----------------------------------------------------------------------===//
 514 // MIPS DSP Rev 1
 515 //===----------------------------------------------------------------------===//
 516
 517 // Addition/subtraction
 518 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 519                                        DSPROpnd, DSPROpnd>, IsCommutable,
 520                      Defs<[DSPOutFlag20]>;
 521
 522 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 523                                          NoItinerary, DSPROpnd, DSPROpnd>,
 524                        IsCommutable, Defs<[DSPOutFlag20]>;
 525
 526 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 527                                        DSPROpnd, DSPROpnd>,
 528                      Defs<[DSPOutFlag20]>;
 529
 530 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 531                                          NoItinerary, DSPROpnd, DSPROpnd>,
 532                        Defs<[DSPOutFlag20]>;
 533
 534 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 535                                        DSPROpnd, DSPROpnd>, IsCommutable,
 536                      Defs<[DSPOutFlag20]>;
 537
 538 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 539                                          NoItinerary, DSPROpnd, DSPROpnd>,
 540                        IsCommutable, Defs<[DSPOutFlag20]>;
 541
 542 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 543                                        DSPROpnd, DSPROpnd>,
 544                      Defs<[DSPOutFlag20]>;
 545
 546 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 547                                          NoItinerary, DSPROpnd, DSPROpnd>,
 548                        Defs<[DSPOutFlag20]>;
 549
 550 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 551                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 552                       IsCommutable, Defs<[DSPOutFlag20]>;
 553
 554 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 555                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 556                       Defs<[DSPOutFlag20]>;
 557
 558 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 559                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 560                    Defs<[DSPCarry]>;
 561
 562 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 563                                      GPR32Opnd, GPR32Opnd>,
 564                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 565
 566 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 567                                       GPR32Opnd, GPR32Opnd>;
 568
 569 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 570                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 571
 572 // Absolute value
 573 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 574                                               NoItinerary, DSPROpnd>,
 575                        Defs<[DSPOutFlag20]>;
 576
 577 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 578                                              NoItinerary, GPR32Opnd>,
 579                       Defs<[DSPOutFlag20]>;
 580
 581 // Precision reduce/expand
 582 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 583                                                  int_mips_precrq_qb_ph,
 584                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 585
 586 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 587                                                 int_mips_precrq_ph_w,
 588                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 589
 590 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 591                                                    int_mips_precrq_rs_ph_w,
 592                                                    NoItinerary, DSPROpnd,
 593                                                    GPR32Opnd>,
 594                             Defs<[DSPOutFlag22]>;
 595
 596 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 597                                                     int_mips_precrqu_s_qb_ph,
 598                                                     NoItinerary, DSPROpnd,
 599                                                     DSPROpnd>,
 600                              Defs<[DSPOutFlag22]>;
 601
 602 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 603                                                  int_mips_preceq_w_phl,
 604                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 605
 606 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 607                                                  int_mips_preceq_w_phr,
 608                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 609
 610 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 611                                                    int_mips_precequ_ph_qbl,
 612                                                    NoItinerary, DSPROpnd>;
 613
 614 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 615                                                    int_mips_precequ_ph_qbr,
 616                                                    NoItinerary, DSPROpnd>;
 617
 618 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 619                                                     int_mips_precequ_ph_qbla,
 620                                                     NoItinerary, DSPROpnd>;
 621
 622 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 623                                                     int_mips_precequ_ph_qbra,
 624                                                     NoItinerary, DSPROpnd>;
 625
 626 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 627                                                   int_mips_preceu_ph_qbl,
 628                                                   NoItinerary, DSPROpnd>;
 629
 630 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 631                                                   int_mips_preceu_ph_qbr,
 632                                                   NoItinerary, DSPROpnd>;
 633
 634 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 635                                                    int_mips_preceu_ph_qbla,
 636                                                    NoItinerary, DSPROpnd>;
 637
 638 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 639                                                    int_mips_preceu_ph_qbra,
 640                                                    NoItinerary, DSPROpnd>;
 641
 642 // Shift
 643 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 644                                           NoItinerary, DSPROpnd>,
 645                      Defs<[DSPOutFlag22]>;
 646
 647 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 648                                            NoItinerary, DSPROpnd>,
 649                       Defs<[DSPOutFlag22]>;
 650
 651 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 652                                           NoItinerary, DSPROpnd>;
 653
 654 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 655                                            NoItinerary, DSPROpnd>;
 656
 657 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 658                                           NoItinerary, DSPROpnd>,
 659                      Defs<[DSPOutFlag22]>;
 660
 661 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 662                                            NoItinerary, DSPROpnd>,
 663                       Defs<[DSPOutFlag22]>;
 664
 665 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 666                                             immZExt4, NoItinerary, DSPROpnd>,
 667                        Defs<[DSPOutFlag22]>;
 668
 669 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 670                                              NoItinerary, DSPROpnd>,
 671                         Defs<[DSPOutFlag22]>;
 672
 673 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 674                                           NoItinerary, DSPROpnd>;
 675
 676 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 677                                            NoItinerary, DSPROpnd>;
 678
 679 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 680                                             immZExt4, NoItinerary, DSPROpnd>;
 681
 682 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 683                                              NoItinerary, DSPROpnd>;
 684
 685 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 686                                            immZExt5, NoItinerary, GPR32Opnd>,
 687                       Defs<[DSPOutFlag22]>;
 688
 689 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 690                                             NoItinerary, GPR32Opnd>,
 691                        Defs<[DSPOutFlag22]>;
 692
 693 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 694                                            immZExt5, NoItinerary, GPR32Opnd>;
 695
 696 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 697                                             NoItinerary, GPR32Opnd>;
 698
 699 // Multiplication
 700 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 701                                               int_mips_muleu_s_ph_qbl,
 702                                               NoItinerary, DSPROpnd, DSPROpnd>,
 703                             Defs<[DSPOutFlag21]>;
 704
 705 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 706                                               int_mips_muleu_s_ph_qbr,
 707                                               NoItinerary, DSPROpnd, DSPROpnd>,
 708                             Defs<[DSPOutFlag21]>;
 709
 710 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 711                                              int_mips_muleq_s_w_phl,
 712                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 713                            IsCommutable, Defs<[DSPOutFlag21]>;
 714
 715 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 716                                              int_mips_muleq_s_w_phr,
 717                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 718                            IsCommutable, Defs<[DSPOutFlag21]>;
 719
 720 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 721                                           NoItinerary, DSPROpnd, DSPROpnd>,
 722                         IsCommutable, Defs<[DSPOutFlag21]>;
 723
 724 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 725                                               MipsMULSAQ_S_W_PH>,
 726                            Defs<[DSPOutFlag16_19]>;
 727
 728 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 729                          Defs<[DSPOutFlag16_19]>;
 730
 731 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 732                          Defs<[DSPOutFlag16_19]>;
 733
 734 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 735                           Defs<[DSPOutFlag16_19]>;
 736
 737 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 738                           Defs<[DSPOutFlag16_19]>;
 739
 740 // Move from/to hi/lo.
 741 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 742 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 743 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 744 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 745
 746 // Dot product with accumulate/subtract
 747 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 748
 749 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 750
 751 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 752
 753 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 754
 755 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 756                          Defs<[DSPOutFlag16_19]>;
 757
 758 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 759                          Defs<[DSPOutFlag16_19]>;
 760
 761 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 762                          Defs<[DSPOutFlag16_19]>;
 763
 764 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 765                          Defs<[DSPOutFlag16_19]>;
 766
 767 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 768 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 769 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 770 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 771 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 772 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 773
 774 // Comparison
 775 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 776                                                int_mips_cmpu_eq_qb, NoItinerary,
 777                                                DSPROpnd>,
 778                         IsCommutable, Defs<[DSPCCond]>;
 779
 780 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 781                                                int_mips_cmpu_lt_qb, NoItinerary,
 782                                                DSPROpnd>, Defs<[DSPCCond]>;
 783
 784 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 785                                                int_mips_cmpu_le_qb, NoItinerary,
 786                                                DSPROpnd>, Defs<[DSPCCond]>;
 787
 788 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 789                                                 int_mips_cmpgu_eq_qb,
 790                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 791                          IsCommutable;
 792
 793 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 794                                                 int_mips_cmpgu_lt_qb,
 795                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 796
 797 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 798                                                 int_mips_cmpgu_le_qb,
 799                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 800
 801 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 802                                               NoItinerary, DSPROpnd>,
 803                        IsCommutable, Defs<[DSPCCond]>;
 804
 805 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 806                                               NoItinerary, DSPROpnd>,
 807                        Defs<[DSPCCond]>;
 808
 809 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 810                                               NoItinerary, DSPROpnd>,
 811                        Defs<[DSPCCond]>;
 812
 813 // Misc
 814 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 815                                            NoItinerary, GPR32Opnd>;
 816
 817 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 818                                               NoItinerary, DSPROpnd, DSPROpnd>;
 819
 820 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 821                                     NoItinerary, DSPROpnd>;
 822
 823 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 824                                     NoItinerary, DSPROpnd>;
 825
 826 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 827                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 828
 829 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 830                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 831
 832 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 833                                             NoItinerary, DSPROpnd, DSPROpnd>,
 834                      Uses<[DSPCCond]>;
 835
 836 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 837                                             NoItinerary, DSPROpnd, DSPROpnd>,
 838                      Uses<[DSPCCond]>;
 839
 840 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 841
 842 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 843
 844 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 845
 846 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 847
 848 // Extr
 849 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 850                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 851
 852 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 853                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 854
 855 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 856                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 857
 858 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 859                                              NoItinerary>,
 860                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 861
 862 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 863                     Defs<[DSPOutFlag23]>;
 864
 865 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 866                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 867
 868 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 869                                               NoItinerary>,
 870                       Defs<[DSPOutFlag23]>;
 871
 872 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 873                                                NoItinerary>,
 874                        Defs<[DSPOutFlag23]>;
 875
 876 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 877                                                NoItinerary>,
 878                        Defs<[DSPOutFlag23]>;
 879
 880 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 881                                                 NoItinerary>,
 882                         Defs<[DSPOutFlag23]>;
 883
 884 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 885                                               NoItinerary>,
 886                       Defs<[DSPOutFlag23]>;
 887
 888 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 889                                                NoItinerary>,
 890                        Defs<[DSPOutFlag23]>;
 891
 892 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 893
 894 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 895
 896 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 897
 898 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 899
 900 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 901
 902 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 903                   Uses<[DSPPos, DSPSCount]>;
 904
 905 //===----------------------------------------------------------------------===//
 906 // MIPS DSP Rev 2
 907 // Addition/subtraction
 908 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 909                                        DSPROpnd, DSPROpnd>, IsCommutable,
 910                      Defs<[DSPOutFlag20]>;
 911
 912 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 913                                          NoItinerary, DSPROpnd, DSPROpnd>,
 914                        IsCommutable, Defs<[DSPOutFlag20]>;
 915
 916 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 917                                        DSPROpnd, DSPROpnd>,
 918                      Defs<[DSPOutFlag20]>;
 919
 920 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 921                                          NoItinerary, DSPROpnd, DSPROpnd>,
 922                        Defs<[DSPOutFlag20]>;
 923
 924 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 925                                          NoItinerary, DSPROpnd>, IsCommutable;
 926
 927 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 928                                            NoItinerary, DSPROpnd>, IsCommutable;
 929
 930 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 931                                          NoItinerary, DSPROpnd>;
 932
 933 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 934                                            NoItinerary, DSPROpnd>;
 935
 936 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 937                                          NoItinerary, DSPROpnd>, IsCommutable;
 938
 939 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 940                                            NoItinerary, DSPROpnd>, IsCommutable;
 941
 942 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 943                                          NoItinerary, DSPROpnd>;
 944
 945 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 946                                            NoItinerary, DSPROpnd>;
 947
 948 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 949                                         NoItinerary, GPR32Opnd>, IsCommutable;
 950
 951 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 952                                           NoItinerary, GPR32Opnd>, IsCommutable;
 953
 954 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 955                                         NoItinerary, GPR32Opnd>;
 956
 957 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 958                                           NoItinerary, GPR32Opnd>;
 959
 960 // Comparison
 961 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 962                                                  int_mips_cmpgdu_eq_qb,
 963                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 964                           IsCommutable, Defs<[DSPCCond]>;
 965
 966 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 967                                                  int_mips_cmpgdu_lt_qb,
 968                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 969                           Defs<[DSPCCond]>;
 970
 971 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 972                                                  int_mips_cmpgdu_le_qb,
 973                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 974                           Defs<[DSPCCond]>;
 975
 976 // Absolute
 977 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 978                                               NoItinerary, DSPROpnd>,
 979                        Defs<[DSPOutFlag20]>;
 980
 981 // Multiplication
 982 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 983                                        DSPROpnd>, IsCommutable,
 984                     Defs<[DSPOutFlag21]>;
 985
 986 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 987                                          NoItinerary, DSPROpnd>, IsCommutable,
 988                       Defs<[DSPOutFlag21]>;
 989
 990 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 991                                          NoItinerary, GPR32Opnd>, IsCommutable,
 992                       Defs<[DSPOutFlag21]>;
 993
 994 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
 995                                           NoItinerary, GPR32Opnd>, IsCommutable,
 996                        Defs<[DSPOutFlag21]>;
 997
 998 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
 999                                          NoItinerary, DSPROpnd, DSPROpnd>,
1000                        IsCommutable, Defs<[DSPOutFlag21]>;
1001
1002 // Dot product with accumulate/subtract
1003 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1004
1005 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1006
1007 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1008                           Defs<[DSPOutFlag16_19]>;
1009
1010 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1011                                               MipsDPAQX_SA_W_PH>,
1012                            Defs<[DSPOutFlag16_19]>;
1013
1014 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1015
1016 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1017
1018 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1019                           Defs<[DSPOutFlag16_19]>;
1020
1021 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1022                                               MipsDPSQX_SA_W_PH>,
1023                            Defs<[DSPOutFlag16_19]>;
1024
1025 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1026
1027 // Precision reduce/expand
1028 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1029                                                 int_mips_precr_qb_ph,
1030                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1031
1032 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1033                                                      int_mips_precr_sra_ph_w,
1034                                                      NoItinerary, DSPROpnd,
1035                                                      GPR32Opnd>;
1036
1037 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1038                                                       int_mips_precr_sra_r_ph_w,
1039                                                        NoItinerary, DSPROpnd,
1040                                                        GPR32Opnd>;
1041
1042 // Shift
1043 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1044                                           NoItinerary, DSPROpnd>;
1045
1046 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1047                                            NoItinerary, DSPROpnd>;
1048
1049 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1050                                             immZExt3, NoItinerary, DSPROpnd>;
1051
1052 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1053                                              NoItinerary, DSPROpnd>;
1054
1055 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1056                                           NoItinerary, DSPROpnd>;
1057
1058 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1059                                            NoItinerary, DSPROpnd>;
1060
1061 // Misc
1062 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1063                                      NoItinerary>;
1064
1065 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1066                                      NoItinerary>;
1067
1068 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1069                                       NoItinerary>;
1070
1071 // Pseudos.
1072 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1073                                                 NoItinerary>, Uses<[DSPPos]>;
1074
1075 // Instruction defs.
1076 // MIPS DSP Rev 1
1077 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1078 def ADDU_S_QB : ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1079 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1080 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1081 def ADDQ_PH : ADDQ_PH_ENC, ADDQ_PH_DESC;
1082 def ADDQ_S_PH : ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1083 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1084 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1085 def ADDQ_S_W : ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1086 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1087 def ADDSC : ADDSC_ENC, ADDSC_DESC;
1088 def ADDWC : ADDWC_ENC, ADDWC_DESC;
1089 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1090 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1091 def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1092 def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1093 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1094 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1095 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1096 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1097 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1098 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1099 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1100 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1101 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1102 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1103 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1104 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1105 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1106 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1107 def SHLL_QB : SHLL_QB_ENC, SHLL_QB_DESC;
1108 def SHLLV_QB : SHLLV_QB_ENC, SHLLV_QB_DESC;
1109 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1110 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1111 def SHLL_PH : SHLL_PH_ENC, SHLL_PH_DESC;
1112 def SHLLV_PH : SHLLV_PH_ENC, SHLLV_PH_DESC;
1113 def SHLL_S_PH : SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1114 def SHLLV_S_PH : SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1115 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1116 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1117 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1118 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1119 def SHLL_S_W : SHLL_S_W_ENC, SHLL_S_W_DESC;
1120 def SHLLV_S_W : SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1121 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1122 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1123 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1124 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1125 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1126 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1127 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1128 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1129 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1130 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1131 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1132 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1133 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1134 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1135 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1136 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1137 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1138 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1139 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1140 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1141 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1142 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1143 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1144 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1145 def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
1146 def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
1147 def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
1148 def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
1149 def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
1150 def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1151 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1152 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1153 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1154 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1155 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1156 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1157 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1158 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1159 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1160 def BITREV : BITREV_ENC, BITREV_DESC;
1161 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1162 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1163 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1164 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1165 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1166 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1167 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1168 def LWX : LWX_ENC, LWX_DESC;
1169 def LHX : LHX_ENC, LHX_DESC;
1170 def LBUX : LBUX_ENC, LBUX_DESC;
1171 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1172 def INSV : INSV_ENC, INSV_DESC;
1173 def EXTP : EXTP_ENC, EXTP_DESC;
1174 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1175 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1176 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1177 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1178 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1179 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1180 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1181 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1182 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1183 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1184 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1185 def SHILO : SHILO_ENC, SHILO_DESC;
1186 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1187 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1188 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1189 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1190
1191 // MIPS DSP Rev 2
1192 let Predicates = [HasDSPR2] in {
1193
1194 def ADDU_PH : ADDU_PH_ENC, ADDU_PH_DESC;
1195 def ADDU_S_PH : ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1196 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1197 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1198 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1199 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1200 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1201 def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1202 def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
1203 def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1204 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1205 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1206 def ADDQH_PH : ADDQH_PH_ENC, ADDQH_PH_DESC;
1207 def ADDQH_R_PH : ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1208 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1209 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1210 def ADDQH_W : ADDQH_W_ENC, ADDQH_W_DESC;
1211 def ADDQH_R_W : ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1212 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1213 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1214 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1215 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1216 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1217 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1218 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1219 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
1220 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1221 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1222 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1223 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1224 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1225 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1226 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1227 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1228 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1229 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1230 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1231 def SHRA_QB : SHRA_QB_ENC, SHRA_QB_DESC;
1232 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1233 def SHRA_R_QB : SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1234 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1235 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1236 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1237 def APPEND : APPEND_ENC, APPEND_DESC;
1238 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1239 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1240
1241 }
1242
1243 // Pseudos.
1244 let isPseudo = 1, isCodeGenOnly = 1 in {
1245   // Pseudo instructions for loading and storing accumulator registers.
1246   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1247   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1248
1249   // Pseudos for loading and storing ccond field of DSP control register.
1250   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1251   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1252 }
1253
1254 // Pseudo CMP and PICK instructions.
1255 class PseudoCMP<Instruction RealInst> :
1256   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1257   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1258
1259 class PseudoPICK<Instruction RealInst> :
1260   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1261   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1262   NeverHasSideEffects;
1263
1264 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1265 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1266 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1267 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1268 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1269 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1270
1271 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1272 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1273
1274 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1275
1276 // Patterns.
1277 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1278   Pat<pattern, result>, Requires<[pred]>;
1279
1280 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1281                     RegisterClass SrcRC> :
1282    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1283           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1284
1285 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1286 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1287 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1288 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1289
1290 def : DSPPat<(v2i16 (load addr:$a)),
1291              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1292 def : DSPPat<(v4i8 (load addr:$a)),
1293              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1294 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1295              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1296 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1297              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1298
1299 // Binary operations.
1300 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1301                 Predicate Pred = HasDSP> :
1302   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1303
1304 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1305 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1306 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1307 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1308 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1309 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1310 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1311 def : DSPBinPat<ADDU_QB, v4i8, add>;
1312 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1313 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1314 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1315 def : DSPBinPat<ADDSC, i32, addc>;
1316 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1317 def : DSPBinPat<ADDWC, i32, adde>;
1318
1319 // Shift immediate patterns.
1320 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1321                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1322   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1323
1324 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1325 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1326 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1327 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1328 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1329 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1330 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1331 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1332 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1333 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1334 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1335 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1336
1337 // SETCC/SELECT_CC patterns.
1338 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1339                   CondCode CC> :
1340   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1341          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1342                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1343                       (ValTy ZERO)))>;
1344
1345 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1346                      CondCode CC> :
1347   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1348          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1349                       (ValTy ZERO),
1350                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1351
1352 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1353                      CondCode CC> :
1354   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1355          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1356
1357 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1358                         CondCode CC> :
1359   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1360          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1361
1362 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1363 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1364 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1365 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1366 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1367 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1368 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1369 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1370 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1371 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1372 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1373 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1374
1375 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1376 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1377 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1378 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1379 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1380 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1381 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1382 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1383 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1384 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1385 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1386 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1387
1388 // Extr patterns.
1389 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1390   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1391          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1392
1393 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1394   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1395          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1396
1397 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1398 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1399 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1400 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1401 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1402 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1403 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1404 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1405 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1406 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1407 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1408 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1409
1410 // Indexed load patterns.
1411 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1412   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1413          (Instr i32:$base, i32:$index)>;
1414
1415 let AddedComplexity = 20 in {
1416   def : IndexedLoadPat<zextloadi8, LBUX>;
1417   def : IndexedLoadPat<sextloadi16, LHX>;
1418   def : IndexedLoadPat<load, LWX>;
1419 }