lib/Target/Mips/MipsDSPInstrInfo.td

   1 //===- MipsDSPInstrInfo.td - DSP ASE instructions -*- tablegen ------------*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes Mips DSP ASE instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // ImmLeaf
  15 def immZExt1 : ImmLeaf<i32, [{return isUInt<1>(Imm);}]>;
  16 def immZExt2 : ImmLeaf<i32, [{return isUInt<2>(Imm);}]>;
  17 def immZExt3 : ImmLeaf<i32, [{return isUInt<3>(Imm);}]>;
  18 def immZExt4 : ImmLeaf<i32, [{return isUInt<4>(Imm);}]>;
  19 def immZExt8 : ImmLeaf<i32, [{return isUInt<8>(Imm);}]>;
  20 def immZExt10 : ImmLeaf<i32, [{return isUInt<10>(Imm);}]>;
  21 def immSExt6 : ImmLeaf<i32, [{return isInt<6>(Imm);}]>;
  22
  23 // Mips-specific dsp nodes
  24 def SDT_MipsExtr : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
  25                                         SDTCisVT<2, untyped>]>;
  26 def SDT_MipsShilo : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  27                                          SDTCisSameAs<0, 2>, SDTCisVT<1, i32>]>;
  28 def SDT_MipsDPA : SDTypeProfile<1, 3, [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  29                                        SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  30 def SDT_MipsSHIFT_DSP : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  31                                              SDTCisVT<2, i32>]>;
  32
  33 class MipsDSPBase<string Opc, SDTypeProfile Prof> :
  34   SDNode<!strconcat("MipsISD::", Opc), Prof>;
  35
  36 class MipsDSPSideEffectBase<string Opc, SDTypeProfile Prof> :
  37   SDNode<!strconcat("MipsISD::", Opc), Prof, [SDNPHasChain, SDNPSideEffect]>;
  38
  39 def MipsEXTP : MipsDSPSideEffectBase<"EXTP", SDT_MipsExtr>;
  40 def MipsEXTPDP : MipsDSPSideEffectBase<"EXTPDP", SDT_MipsExtr>;
  41 def MipsEXTR_S_H : MipsDSPSideEffectBase<"EXTR_S_H", SDT_MipsExtr>;
  42 def MipsEXTR_W : MipsDSPSideEffectBase<"EXTR_W", SDT_MipsExtr>;
  43 def MipsEXTR_R_W : MipsDSPSideEffectBase<"EXTR_R_W", SDT_MipsExtr>;
  44 def MipsEXTR_RS_W : MipsDSPSideEffectBase<"EXTR_RS_W", SDT_MipsExtr>;
  45
  46 def MipsSHILO : MipsDSPBase<"SHILO", SDT_MipsShilo>;
  47 def MipsMTHLIP : MipsDSPSideEffectBase<"MTHLIP", SDT_MipsShilo>;
  48
  49 def MipsMULSAQ_S_W_PH : MipsDSPSideEffectBase<"MULSAQ_S_W_PH", SDT_MipsDPA>;
  50 def MipsMAQ_S_W_PHL : MipsDSPSideEffectBase<"MAQ_S_W_PHL", SDT_MipsDPA>;
  51 def MipsMAQ_S_W_PHR : MipsDSPSideEffectBase<"MAQ_S_W_PHR", SDT_MipsDPA>;
  52 def MipsMAQ_SA_W_PHL : MipsDSPSideEffectBase<"MAQ_SA_W_PHL", SDT_MipsDPA>;
  53 def MipsMAQ_SA_W_PHR : MipsDSPSideEffectBase<"MAQ_SA_W_PHR", SDT_MipsDPA>;
  54
  55 def MipsDPAU_H_QBL : MipsDSPBase<"DPAU_H_QBL", SDT_MipsDPA>;
  56 def MipsDPAU_H_QBR : MipsDSPBase<"DPAU_H_QBR", SDT_MipsDPA>;
  57 def MipsDPSU_H_QBL : MipsDSPBase<"DPSU_H_QBL", SDT_MipsDPA>;
  58 def MipsDPSU_H_QBR : MipsDSPBase<"DPSU_H_QBR", SDT_MipsDPA>;
  59 def MipsDPAQ_S_W_PH : MipsDSPSideEffectBase<"DPAQ_S_W_PH", SDT_MipsDPA>;
  60 def MipsDPSQ_S_W_PH : MipsDSPSideEffectBase<"DPSQ_S_W_PH", SDT_MipsDPA>;
  61 def MipsDPAQ_SA_L_W : MipsDSPSideEffectBase<"DPAQ_SA_L_W", SDT_MipsDPA>;
  62 def MipsDPSQ_SA_L_W : MipsDSPSideEffectBase<"DPSQ_SA_L_W", SDT_MipsDPA>;
  63
  64 def MipsDPA_W_PH : MipsDSPBase<"DPA_W_PH", SDT_MipsDPA>;
  65 def MipsDPS_W_PH : MipsDSPBase<"DPS_W_PH", SDT_MipsDPA>;
  66 def MipsDPAQX_S_W_PH : MipsDSPSideEffectBase<"DPAQX_S_W_PH", SDT_MipsDPA>;
  67 def MipsDPAQX_SA_W_PH : MipsDSPSideEffectBase<"DPAQX_SA_W_PH", SDT_MipsDPA>;
  68 def MipsDPAX_W_PH : MipsDSPBase<"DPAX_W_PH", SDT_MipsDPA>;
  69 def MipsDPSX_W_PH : MipsDSPBase<"DPSX_W_PH", SDT_MipsDPA>;
  70 def MipsDPSQX_S_W_PH : MipsDSPSideEffectBase<"DPSQX_S_W_PH", SDT_MipsDPA>;
  71 def MipsDPSQX_SA_W_PH : MipsDSPSideEffectBase<"DPSQX_SA_W_PH", SDT_MipsDPA>;
  72 def MipsMULSA_W_PH : MipsDSPBase<"MULSA_W_PH", SDT_MipsDPA>;
  73
  74 def MipsMULT : MipsDSPBase<"MULT", SDT_MipsDPA>;
  75 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>;
  76 def MipsMADD_DSP : MipsDSPBase<"MADD_DSP", SDT_MipsDPA>;
  77 def MipsMADDU_DSP : MipsDSPBase<"MADDU_DSP", SDT_MipsDPA>;
  78 def MipsMSUB_DSP : MipsDSPBase<"MSUB_DSP", SDT_MipsDPA>;
  79 def MipsMSUBU_DSP : MipsDSPBase<"MSUBU_DSP", SDT_MipsDPA>;
  80 def MipsSHLL_DSP : MipsDSPBase<"SHLL_DSP", SDT_MipsSHIFT_DSP>;
  81 def MipsSHRA_DSP : MipsDSPBase<"SHRA_DSP", SDT_MipsSHIFT_DSP>;
  82 def MipsSHRL_DSP : MipsDSPBase<"SHRL_DSP", SDT_MipsSHIFT_DSP>;
  83 def MipsSETCC_DSP : MipsDSPBase<"SETCC_DSP", SDTSetCC>;
  84 def MipsSELECT_CC_DSP : MipsDSPBase<"SELECT_CC_DSP", SDTSelectCC>;
  85
  86 // Flags.
  87 class Uses<list<Register> Regs> {
  88   list<Register> Uses = Regs;
  89 }
  90
  91 class Defs<list<Register> Regs> {
  92   list<Register> Defs = Regs;
  93 }
  94
  95 // Instruction encoding.
  96 class ADDU_QB_ENC : ADDU_QB_FMT<0b00000>;
  97 class ADDU_S_QB_ENC : ADDU_QB_FMT<0b00100>;
  98 class SUBU_QB_ENC : ADDU_QB_FMT<0b00001>;
  99 class SUBU_S_QB_ENC : ADDU_QB_FMT<0b00101>;
 100 class ADDQ_PH_ENC : ADDU_QB_FMT<0b01010>;
 101 class ADDQ_S_PH_ENC : ADDU_QB_FMT<0b01110>;
 102 class SUBQ_PH_ENC : ADDU_QB_FMT<0b01011>;
 103 class SUBQ_S_PH_ENC : ADDU_QB_FMT<0b01111>;
 104 class ADDQ_S_W_ENC : ADDU_QB_FMT<0b10110>;
 105 class SUBQ_S_W_ENC : ADDU_QB_FMT<0b10111>;
 106 class ADDSC_ENC : ADDU_QB_FMT<0b10000>;
 107 class ADDWC_ENC : ADDU_QB_FMT<0b10001>;
 108 class MODSUB_ENC : ADDU_QB_FMT<0b10010>;
 109 class RADDU_W_QB_ENC : RADDU_W_QB_FMT<0b10100>;
 110 class ABSQ_S_PH_ENC : ABSQ_S_PH_R2_FMT<0b01001>;
 111 class ABSQ_S_W_ENC : ABSQ_S_PH_R2_FMT<0b10001>;
 112 class PRECRQ_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01100>;
 113 class PRECRQ_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10100>;
 114 class PRECRQ_RS_PH_W_ENC : CMP_EQ_QB_R3_FMT<0b10101>;
 115 class PRECRQU_S_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01111>;
 116 class PRECEQ_W_PHL_ENC : ABSQ_S_PH_R2_FMT<0b01100>;
 117 class PRECEQ_W_PHR_ENC : ABSQ_S_PH_R2_FMT<0b01101>;
 118 class PRECEQU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b00100>;
 119 class PRECEQU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b00101>;
 120 class PRECEQU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b00110>;
 121 class PRECEQU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b00111>;
 122 class PRECEU_PH_QBL_ENC : ABSQ_S_PH_R2_FMT<0b11100>;
 123 class PRECEU_PH_QBR_ENC : ABSQ_S_PH_R2_FMT<0b11101>;
 124 class PRECEU_PH_QBLA_ENC : ABSQ_S_PH_R2_FMT<0b11110>;
 125 class PRECEU_PH_QBRA_ENC : ABSQ_S_PH_R2_FMT<0b11111>;
 126 class SHLL_QB_ENC : SHLL_QB_FMT<0b00000>;
 127 class SHLLV_QB_ENC : SHLL_QB_FMT<0b00010>;
 128 class SHRL_QB_ENC : SHLL_QB_FMT<0b00001>;
 129 class SHRLV_QB_ENC : SHLL_QB_FMT<0b00011>;
 130 class SHLL_PH_ENC : SHLL_QB_FMT<0b01000>;
 131 class SHLLV_PH_ENC : SHLL_QB_FMT<0b01010>;
 132 class SHLL_S_PH_ENC : SHLL_QB_FMT<0b01100>;
 133 class SHLLV_S_PH_ENC : SHLL_QB_FMT<0b01110>;
 134 class SHRA_PH_ENC : SHLL_QB_FMT<0b01001>;
 135 class SHRAV_PH_ENC : SHLL_QB_FMT<0b01011>;
 136 class SHRA_R_PH_ENC : SHLL_QB_FMT<0b01101>;
 137 class SHRAV_R_PH_ENC : SHLL_QB_FMT<0b01111>;
 138 class SHLL_S_W_ENC : SHLL_QB_FMT<0b10100>;
 139 class SHLLV_S_W_ENC : SHLL_QB_FMT<0b10110>;
 140 class SHRA_R_W_ENC : SHLL_QB_FMT<0b10101>;
 141 class SHRAV_R_W_ENC : SHLL_QB_FMT<0b10111>;
 142 class MULEU_S_PH_QBL_ENC : ADDU_QB_FMT<0b00110>;
 143 class MULEU_S_PH_QBR_ENC : ADDU_QB_FMT<0b00111>;
 144 class MULEQ_S_W_PHL_ENC : ADDU_QB_FMT<0b11100>;
 145 class MULEQ_S_W_PHR_ENC : ADDU_QB_FMT<0b11101>;
 146 class MULQ_RS_PH_ENC : ADDU_QB_FMT<0b11111>;
 147 class MULSAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00110>;
 148 class MAQ_S_W_PHL_ENC : DPA_W_PH_FMT<0b10100>;
 149 class MAQ_S_W_PHR_ENC : DPA_W_PH_FMT<0b10110>;
 150 class MAQ_SA_W_PHL_ENC : DPA_W_PH_FMT<0b10000>;
 151 class MAQ_SA_W_PHR_ENC : DPA_W_PH_FMT<0b10010>;
 152 class MFHI_ENC : MFHI_FMT<0b010000>;
 153 class MFLO_ENC : MFHI_FMT<0b010010>;
 154 class MTHI_ENC : MTHI_FMT<0b010001>;
 155 class MTLO_ENC : MTHI_FMT<0b010011>;
 156 class DPAU_H_QBL_ENC : DPA_W_PH_FMT<0b00011>;
 157 class DPAU_H_QBR_ENC : DPA_W_PH_FMT<0b00111>;
 158 class DPSU_H_QBL_ENC : DPA_W_PH_FMT<0b01011>;
 159 class DPSU_H_QBR_ENC : DPA_W_PH_FMT<0b01111>;
 160 class DPAQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00100>;
 161 class DPSQ_S_W_PH_ENC : DPA_W_PH_FMT<0b00101>;
 162 class DPAQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01100>;
 163 class DPSQ_SA_L_W_ENC : DPA_W_PH_FMT<0b01101>;
 164 class MULT_DSP_ENC : MULT_FMT<0b000000, 0b011000>;
 165 class MULTU_DSP_ENC : MULT_FMT<0b000000, 0b011001>;
 166 class MADD_DSP_ENC : MULT_FMT<0b011100, 0b000000>;
 167 class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
 168 class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
 169 class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
 170 class CMPU_EQ_QB_ENC : CMP_EQ_QB_R2_FMT<0b00000>;
 171 class CMPU_LT_QB_ENC : CMP_EQ_QB_R2_FMT<0b00001>;
 172 class CMPU_LE_QB_ENC : CMP_EQ_QB_R2_FMT<0b00010>;
 173 class CMPGU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b00100>;
 174 class CMPGU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b00101>;
 175 class CMPGU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b00110>;
 176 class CMP_EQ_PH_ENC : CMP_EQ_QB_R2_FMT<0b01000>;
 177 class CMP_LT_PH_ENC : CMP_EQ_QB_R2_FMT<0b01001>;
 178 class CMP_LE_PH_ENC : CMP_EQ_QB_R2_FMT<0b01010>;
 179 class BITREV_ENC : ABSQ_S_PH_R2_FMT<0b11011>;
 180 class PACKRL_PH_ENC : CMP_EQ_QB_R3_FMT<0b01110>;
 181 class REPL_QB_ENC : REPL_FMT<0b00010>;
 182 class REPL_PH_ENC : REPL_FMT<0b01010>;
 183 class REPLV_QB_ENC : ABSQ_S_PH_R2_FMT<0b00011>;
 184 class REPLV_PH_ENC : ABSQ_S_PH_R2_FMT<0b01011>;
 185 class PICK_QB_ENC : CMP_EQ_QB_R3_FMT<0b00011>;
 186 class PICK_PH_ENC : CMP_EQ_QB_R3_FMT<0b01011>;
 187 class LWX_ENC : LX_FMT<0b00000>;
 188 class LHX_ENC : LX_FMT<0b00100>;
 189 class LBUX_ENC : LX_FMT<0b00110>;
 190 class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
 191 class INSV_ENC : INSV_FMT<0b001100>;
 192
 193 class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
 194 class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
 195 class EXTPDP_ENC : EXTR_W_TY1_FMT<0b01010>;
 196 class EXTPDPV_ENC : EXTR_W_TY1_FMT<0b01011>;
 197 class EXTR_W_ENC : EXTR_W_TY1_FMT<0b00000>;
 198 class EXTRV_W_ENC : EXTR_W_TY1_FMT<0b00001>;
 199 class EXTR_R_W_ENC : EXTR_W_TY1_FMT<0b00100>;
 200 class EXTRV_R_W_ENC : EXTR_W_TY1_FMT<0b00101>;
 201 class EXTR_RS_W_ENC : EXTR_W_TY1_FMT<0b00110>;
 202 class EXTRV_RS_W_ENC : EXTR_W_TY1_FMT<0b00111>;
 203 class EXTR_S_H_ENC : EXTR_W_TY1_FMT<0b01110>;
 204 class EXTRV_S_H_ENC : EXTR_W_TY1_FMT<0b01111>;
 205 class SHILO_ENC : SHILO_R1_FMT<0b11010>;
 206 class SHILOV_ENC : SHILO_R2_FMT<0b11011>;
 207 class MTHLIP_ENC : SHILO_R2_FMT<0b11111>;
 208
 209 class RDDSP_ENC : RDDSP_FMT<0b10010>;
 210 class WRDSP_ENC : WRDSP_FMT<0b10011>;
 211 class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>;
 212 class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>;
 213 class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>;
 214 class SUBU_S_PH_ENC : ADDU_QB_FMT<0b01101>;
 215 class CMPGDU_EQ_QB_ENC : CMP_EQ_QB_R3_FMT<0b11000>;
 216 class CMPGDU_LT_QB_ENC : CMP_EQ_QB_R3_FMT<0b11001>;
 217 class CMPGDU_LE_QB_ENC : CMP_EQ_QB_R3_FMT<0b11010>;
 218 class ABSQ_S_QB_ENC : ABSQ_S_PH_R2_FMT<0b00001>;
 219 class ADDUH_QB_ENC : ADDUH_QB_FMT<0b00000>;
 220 class ADDUH_R_QB_ENC : ADDUH_QB_FMT<0b00010>;
 221 class SUBUH_QB_ENC : ADDUH_QB_FMT<0b00001>;
 222 class SUBUH_R_QB_ENC : ADDUH_QB_FMT<0b00011>;
 223 class ADDQH_PH_ENC : ADDUH_QB_FMT<0b01000>;
 224 class ADDQH_R_PH_ENC : ADDUH_QB_FMT<0b01010>;
 225 class SUBQH_PH_ENC : ADDUH_QB_FMT<0b01001>;
 226 class SUBQH_R_PH_ENC : ADDUH_QB_FMT<0b01011>;
 227 class ADDQH_W_ENC : ADDUH_QB_FMT<0b10000>;
 228 class ADDQH_R_W_ENC : ADDUH_QB_FMT<0b10010>;
 229 class SUBQH_W_ENC : ADDUH_QB_FMT<0b10001>;
 230 class SUBQH_R_W_ENC : ADDUH_QB_FMT<0b10011>;
 231 class MUL_PH_ENC : ADDUH_QB_FMT<0b01100>;
 232 class MUL_S_PH_ENC : ADDUH_QB_FMT<0b01110>;
 233 class MULQ_S_W_ENC : ADDUH_QB_FMT<0b10110>;
 234 class MULQ_RS_W_ENC : ADDUH_QB_FMT<0b10111>;
 235 class MULQ_S_PH_ENC : ADDU_QB_FMT<0b11110>;
 236 class DPA_W_PH_ENC : DPA_W_PH_FMT<0b00000>;
 237 class DPS_W_PH_ENC : DPA_W_PH_FMT<0b00001>;
 238 class DPAQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11000>;
 239 class DPAQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11010>;
 240 class DPAX_W_PH_ENC : DPA_W_PH_FMT<0b01000>;
 241 class DPSX_W_PH_ENC : DPA_W_PH_FMT<0b01001>;
 242 class DPSQX_S_W_PH_ENC : DPA_W_PH_FMT<0b11001>;
 243 class DPSQX_SA_W_PH_ENC : DPA_W_PH_FMT<0b11011>;
 244 class MULSA_W_PH_ENC : DPA_W_PH_FMT<0b00010>;
 245 class PRECR_QB_PH_ENC : CMP_EQ_QB_R3_FMT<0b01101>;
 246 class PRECR_SRA_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11110>;
 247 class PRECR_SRA_R_PH_W_ENC : PRECR_SRA_PH_W_FMT<0b11111>;
 248 class SHRA_QB_ENC : SHLL_QB_FMT<0b00100>;
 249 class SHRAV_QB_ENC : SHLL_QB_FMT<0b00110>;
 250 class SHRA_R_QB_ENC : SHLL_QB_FMT<0b00101>;
 251 class SHRAV_R_QB_ENC : SHLL_QB_FMT<0b00111>;
 252 class SHRL_PH_ENC : SHLL_QB_FMT<0b11001>;
 253 class SHRLV_PH_ENC : SHLL_QB_FMT<0b11011>;
 254 class APPEND_ENC : APPEND_FMT<0b00000>;
 255 class BALIGN_ENC : APPEND_FMT<0b10000>;
 256 class PREPEND_ENC : APPEND_FMT<0b00001>;
 257
 258 // Instruction desc.
 259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 260                         InstrItinClass itin, RegisterOperand ROD,
 261                         RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 262   dag OutOperandList = (outs ROD:$rd);
 263   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 264   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 265   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 266   InstrItinClass Itinerary = itin;
 267   string BaseOpcode = instr_asm;
 268 }
 269
 270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 271                            InstrItinClass itin, RegisterOperand ROD,
 272                            RegisterOperand ROS = ROD> {
 273   dag OutOperandList = (outs ROD:$rd);
 274   dag InOperandList = (ins ROS:$rs);
 275   string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
 276   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
 277   InstrItinClass Itinerary = itin;
 278 }
 279
 280 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 281                              InstrItinClass itin, RegisterOperand ROS,
 282                              RegisterOperand ROT = ROS> {
 283   dag OutOperandList = (outs);
 284   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 285   string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
 286   list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
 287   InstrItinClass Itinerary = itin;
 288 }
 289
 290 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 291                              InstrItinClass itin, RegisterOperand ROD,
 292                              RegisterOperand ROS,  RegisterOperand ROT = ROS> {
 293   dag OutOperandList = (outs ROD:$rd);
 294   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 295   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 296   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 297   InstrItinClass Itinerary = itin;
 298 }
 299
 300 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 301                                InstrItinClass itin, RegisterOperand ROT,
 302                                RegisterOperand ROS = ROT> {
 303   dag OutOperandList = (outs ROT:$rt);
 304   dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
 305   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 306   list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
 307   InstrItinClass Itinerary = itin;
 308   string Constraints = "$src = $rt";
 309 }
 310
 311 class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 312                              InstrItinClass itin, RegisterOperand ROD,
 313                              RegisterOperand ROT = ROD> {
 314   dag OutOperandList = (outs ROD:$rd);
 315   dag InOperandList = (ins ROT:$rt);
 316   string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
 317   list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
 318   InstrItinClass Itinerary = itin;
 319   string BaseOpcode = instr_asm;
 320 }
 321
 322 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 323                      ImmLeaf immPat, InstrItinClass itin, RegisterOperand RO> {
 324   dag OutOperandList = (outs RO:$rd);
 325   dag InOperandList = (ins uimm16:$imm);
 326   string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
 327   list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
 328   InstrItinClass Itinerary = itin;
 329 }
 330
 331 class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 332                            InstrItinClass itin, RegisterOperand RO> {
 333   dag OutOperandList = (outs RO:$rd);
 334   dag InOperandList =  (ins RO:$rt, GPR32Opnd:$rs_sa);
 335   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 336   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
 337   InstrItinClass Itinerary = itin;
 338   string BaseOpcode = instr_asm;
 339 }
 340
 341 class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 342                            SDPatternOperator ImmPat, InstrItinClass itin,
 343                            RegisterOperand RO> {
 344   dag OutOperandList = (outs RO:$rd);
 345   dag InOperandList = (ins RO:$rt, uimm16:$rs_sa);
 346   string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
 347   list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
 348   InstrItinClass Itinerary = itin;
 349   bit hasSideEffects = 1;
 350   string BaseOpcode = instr_asm;
 351 }
 352
 353 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 354                    InstrItinClass itin> {
 355   dag OutOperandList = (outs GPR32Opnd:$rd);
 356   dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
 357   string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
 358   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
 359   InstrItinClass Itinerary = itin;
 360   bit mayLoad = 1;
 361 }
 362
 363 class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 364                          InstrItinClass itin, RegisterOperand ROD,
 365                          RegisterOperand ROS = ROD,  RegisterOperand ROT = ROD> {
 366   dag OutOperandList = (outs ROD:$rd);
 367   dag InOperandList = (ins ROS:$rs, ROT:$rt);
 368   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
 369   list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
 370   InstrItinClass Itinerary = itin;
 371   string BaseOpcode = instr_asm;
 372 }
 373
 374 class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 375                        SDPatternOperator ImmOp, InstrItinClass itin> {
 376   dag OutOperandList = (outs GPR32Opnd:$rt);
 377   dag InOperandList = (ins GPR32Opnd:$rs, uimm5:$sa, GPR32Opnd:$src);
 378   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
 379   list<dag> Pattern =  [(set GPR32Opnd:$rt,
 380                         (OpNode GPR32Opnd:$src, GPR32Opnd:$rs, ImmOp:$sa))];
 381   InstrItinClass Itinerary = itin;
 382   string Constraints = "$src = $rt";
 383 }
 384
 385 class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 386                               InstrItinClass itin> {
 387   dag OutOperandList = (outs GPR32Opnd:$rt);
 388   dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
 389   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 390   InstrItinClass Itinerary = itin;
 391 }
 392
 393 class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 394                               InstrItinClass itin> {
 395   dag OutOperandList = (outs GPR32Opnd:$rt);
 396   dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm16:$shift_rs);
 397   string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
 398   InstrItinClass Itinerary = itin;
 399 }
 400
 401 class SHILO_R1_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 402   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 403   dag InOperandList = (ins simm16:$shift, ACC64DSPOpnd:$acin);
 404   string AsmString = !strconcat(instr_asm, "\t$ac, $shift");
 405   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 406                         (OpNode immSExt6:$shift, ACC64DSPOpnd:$acin))];
 407   string Constraints = "$acin = $ac";
 408 }
 409
 410 class SHILO_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 411   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 412   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 413   string AsmString = !strconcat(instr_asm, "\t$ac, $rs");
 414   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 415                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 416   string Constraints = "$acin = $ac";
 417 }
 418
 419 class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 420   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 421   dag InOperandList = (ins GPR32Opnd:$rs, ACC64DSPOpnd:$acin);
 422   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 423   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 424                         (OpNode GPR32Opnd:$rs, ACC64DSPOpnd:$acin))];
 425   string Constraints = "$acin = $ac";
 426 }
 427
 428 class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 429                       InstrItinClass itin> {
 430   dag OutOperandList = (outs GPR32Opnd:$rd);
 431   dag InOperandList = (ins uimm16:$mask);
 432   string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
 433   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode immZExt10:$mask))];
 434   InstrItinClass Itinerary = itin;
 435 }
 436
 437 class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 438                       InstrItinClass itin> {
 439   dag OutOperandList = (outs);
 440   dag InOperandList = (ins GPR32Opnd:$rs, uimm16:$mask);
 441   string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
 442   list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
 443   InstrItinClass Itinerary = itin;
 444 }
 445
 446 class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
 447   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 448   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 449   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 450   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 451                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 452   string Constraints = "$acin = $ac";
 453   string BaseOpcode = instr_asm;
 454 }
 455
 456 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 457                      InstrItinClass itin> {
 458   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 459   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
 460   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 461   list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
 462   InstrItinClass Itinerary = itin;
 463   bit isCommutable = 1;
 464   string BaseOpcode = instr_asm;
 465 }
 466
 467 class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 468                      InstrItinClass itin> {
 469   dag OutOperandList = (outs ACC64DSPOpnd:$ac);
 470   dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
 471   string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
 472   list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
 473                         (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
 474   InstrItinClass Itinerary = itin;
 475   string Constraints = "$acin = $ac";
 476   string BaseOpcode = instr_asm;
 477 }
 478
 479 class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
 480                      InstrItinClass itin> {
 481   dag OutOperandList = (outs GPR32Opnd:$rd);
 482   dag InOperandList = (ins RO:$ac);
 483   string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
 484   list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
 485   InstrItinClass Itinerary = itin;
 486 }
 487
 488 class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> {
 489   dag OutOperandList = (outs RO:$ac);
 490   dag InOperandList = (ins GPR32Opnd:$rs);
 491   string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
 492   InstrItinClass Itinerary = itin;
 493 }
 494
 495 class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
 496   MipsPseudo<(outs GPR32Opnd:$dst), (ins), [(set GPR32Opnd:$dst, (OpNode))]> {
 497   bit usesCustomInserter = 1;
 498 }
 499
 500 class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
 501   dag OutOperandList = (outs);
 502   dag InOperandList = (ins brtarget:$offset);
 503   string AsmString = !strconcat(instr_asm, "\t$offset");
 504   InstrItinClass Itinerary = itin;
 505   bit isBranch = 1;
 506   bit isTerminator = 1;
 507   bit hasDelaySlot = 1;
 508 }
 509
 510 class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
 511                      InstrItinClass itin> {
 512   dag OutOperandList = (outs GPR32Opnd:$rt);
 513   dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
 514   string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
 515   list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
 516   InstrItinClass Itinerary = itin;
 517   string Constraints = "$src = $rt";
 518   string BaseOpcode = instr_asm;
 519 }
 520
 521 //===----------------------------------------------------------------------===//
 522 // MIPS DSP Rev 1
 523 //===----------------------------------------------------------------------===//
 524
 525 // Addition/subtraction
 526 class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
 527                                        DSPROpnd, DSPROpnd>, IsCommutable,
 528                      Defs<[DSPOutFlag20]>;
 529
 530 class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
 531                                          NoItinerary, DSPROpnd, DSPROpnd>,
 532                        IsCommutable, Defs<[DSPOutFlag20]>;
 533
 534 class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
 535                                        DSPROpnd, DSPROpnd>,
 536                      Defs<[DSPOutFlag20]>;
 537
 538 class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
 539                                          NoItinerary, DSPROpnd, DSPROpnd>,
 540                        Defs<[DSPOutFlag20]>;
 541
 542 class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
 543                                        DSPROpnd, DSPROpnd>, IsCommutable,
 544                      Defs<[DSPOutFlag20]>;
 545
 546 class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
 547                                          NoItinerary, DSPROpnd, DSPROpnd>,
 548                        IsCommutable, Defs<[DSPOutFlag20]>;
 549
 550 class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
 551                                        DSPROpnd, DSPROpnd>,
 552                      Defs<[DSPOutFlag20]>;
 553
 554 class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
 555                                          NoItinerary, DSPROpnd, DSPROpnd>,
 556                        Defs<[DSPOutFlag20]>;
 557
 558 class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
 559                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 560                       IsCommutable, Defs<[DSPOutFlag20]>;
 561
 562 class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
 563                                         NoItinerary, GPR32Opnd, GPR32Opnd>,
 564                       Defs<[DSPOutFlag20]>;
 565
 566 class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
 567                                      GPR32Opnd, GPR32Opnd>, IsCommutable,
 568                    Defs<[DSPCarry]>;
 569
 570 class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
 571                                      GPR32Opnd, GPR32Opnd>,
 572                    IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
 573
 574 class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
 575                                       GPR32Opnd, GPR32Opnd>;
 576
 577 class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
 578                                              NoItinerary, GPR32Opnd, DSPROpnd>;
 579
 580 // Absolute value
 581 class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
 582                                               NoItinerary, DSPROpnd>,
 583                        Defs<[DSPOutFlag20]>;
 584
 585 class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
 586                                              NoItinerary, GPR32Opnd>,
 587                       Defs<[DSPOutFlag20]>;
 588
 589 // Precision reduce/expand
 590 class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
 591                                                  int_mips_precrq_qb_ph,
 592                                                  NoItinerary, DSPROpnd, DSPROpnd>;
 593
 594 class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
 595                                                 int_mips_precrq_ph_w,
 596                                                 NoItinerary, DSPROpnd, GPR32Opnd>;
 597
 598 class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
 599                                                    int_mips_precrq_rs_ph_w,
 600                                                    NoItinerary, DSPROpnd,
 601                                                    GPR32Opnd>,
 602                             Defs<[DSPOutFlag22]>;
 603
 604 class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
 605                                                     int_mips_precrqu_s_qb_ph,
 606                                                     NoItinerary, DSPROpnd,
 607                                                     DSPROpnd>,
 608                              Defs<[DSPOutFlag22]>;
 609
 610 class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
 611                                                  int_mips_preceq_w_phl,
 612                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 613
 614 class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
 615                                                  int_mips_preceq_w_phr,
 616                                                  NoItinerary, GPR32Opnd, DSPROpnd>;
 617
 618 class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
 619                                                    int_mips_precequ_ph_qbl,
 620                                                    NoItinerary, DSPROpnd>;
 621
 622 class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
 623                                                    int_mips_precequ_ph_qbr,
 624                                                    NoItinerary, DSPROpnd>;
 625
 626 class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
 627                                                     int_mips_precequ_ph_qbla,
 628                                                     NoItinerary, DSPROpnd>;
 629
 630 class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
 631                                                     int_mips_precequ_ph_qbra,
 632                                                     NoItinerary, DSPROpnd>;
 633
 634 class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
 635                                                   int_mips_preceu_ph_qbl,
 636                                                   NoItinerary, DSPROpnd>;
 637
 638 class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
 639                                                   int_mips_preceu_ph_qbr,
 640                                                   NoItinerary, DSPROpnd>;
 641
 642 class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
 643                                                    int_mips_preceu_ph_qbla,
 644                                                    NoItinerary, DSPROpnd>;
 645
 646 class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
 647                                                    int_mips_preceu_ph_qbra,
 648                                                    NoItinerary, DSPROpnd>;
 649
 650 // Shift
 651 class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
 652                                           NoItinerary, DSPROpnd>,
 653                      Defs<[DSPOutFlag22]>;
 654
 655 class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
 656                                            NoItinerary, DSPROpnd>,
 657                       Defs<[DSPOutFlag22]>;
 658
 659 class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
 660                                           NoItinerary, DSPROpnd>;
 661
 662 class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
 663                                            NoItinerary, DSPROpnd>;
 664
 665 class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
 666                                           NoItinerary, DSPROpnd>,
 667                      Defs<[DSPOutFlag22]>;
 668
 669 class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
 670                                            NoItinerary, DSPROpnd>,
 671                       Defs<[DSPOutFlag22]>;
 672
 673 class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
 674                                             immZExt4, NoItinerary, DSPROpnd>,
 675                        Defs<[DSPOutFlag22]>;
 676
 677 class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
 678                                              NoItinerary, DSPROpnd>,
 679                         Defs<[DSPOutFlag22]>;
 680
 681 class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
 682                                           NoItinerary, DSPROpnd>;
 683
 684 class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
 685                                            NoItinerary, DSPROpnd>;
 686
 687 class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
 688                                             immZExt4, NoItinerary, DSPROpnd>;
 689
 690 class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
 691                                              NoItinerary, DSPROpnd>;
 692
 693 class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
 694                                            immZExt5, NoItinerary, GPR32Opnd>,
 695                       Defs<[DSPOutFlag22]>;
 696
 697 class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
 698                                             NoItinerary, GPR32Opnd>,
 699                        Defs<[DSPOutFlag22]>;
 700
 701 class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
 702                                            immZExt5, NoItinerary, GPR32Opnd>;
 703
 704 class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
 705                                             NoItinerary, GPR32Opnd>;
 706
 707 // Multiplication
 708 class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
 709                                               int_mips_muleu_s_ph_qbl,
 710                                               NoItinerary, DSPROpnd, DSPROpnd>,
 711                             Defs<[DSPOutFlag21]>;
 712
 713 class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
 714                                               int_mips_muleu_s_ph_qbr,
 715                                               NoItinerary, DSPROpnd, DSPROpnd>,
 716                             Defs<[DSPOutFlag21]>;
 717
 718 class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
 719                                              int_mips_muleq_s_w_phl,
 720                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 721                            IsCommutable, Defs<[DSPOutFlag21]>;
 722
 723 class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
 724                                              int_mips_muleq_s_w_phr,
 725                                              NoItinerary, GPR32Opnd, DSPROpnd>,
 726                            IsCommutable, Defs<[DSPOutFlag21]>;
 727
 728 class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
 729                                           NoItinerary, DSPROpnd, DSPROpnd>,
 730                         IsCommutable, Defs<[DSPOutFlag21]>;
 731
 732 class MULSAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsaq_s.w.ph",
 733                                               MipsMULSAQ_S_W_PH>,
 734                            Defs<[DSPOutFlag16_19]>;
 735
 736 class MAQ_S_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phl", MipsMAQ_S_W_PHL>,
 737                          Defs<[DSPOutFlag16_19]>;
 738
 739 class MAQ_S_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_s.w.phr", MipsMAQ_S_W_PHR>,
 740                          Defs<[DSPOutFlag16_19]>;
 741
 742 class MAQ_SA_W_PHL_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phl", MipsMAQ_SA_W_PHL>,
 743                           Defs<[DSPOutFlag16_19]>;
 744
 745 class MAQ_SA_W_PHR_DESC : DPA_W_PH_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR>,
 746                           Defs<[DSPOutFlag16_19]>;
 747
 748 // Move from/to hi/lo.
 749 class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
 750 class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
 751 class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
 752 class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
 753
 754 // Dot product with accumulate/subtract
 755 class DPAU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL>;
 756
 757 class DPAU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpau.h.qbr", MipsDPAU_H_QBR>;
 758
 759 class DPSU_H_QBL_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbl", MipsDPSU_H_QBL>;
 760
 761 class DPSU_H_QBR_DESC : DPA_W_PH_DESC_BASE<"dpsu.h.qbr", MipsDPSU_H_QBR>;
 762
 763 class DPAQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaq_s.w.ph", MipsDPAQ_S_W_PH>,
 764                          Defs<[DSPOutFlag16_19]>;
 765
 766 class DPSQ_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsq_s.w.ph", MipsDPSQ_S_W_PH>,
 767                          Defs<[DSPOutFlag16_19]>;
 768
 769 class DPAQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W>,
 770                          Defs<[DSPOutFlag16_19]>;
 771
 772 class DPSQ_SA_L_W_DESC : DPA_W_PH_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W>,
 773                          Defs<[DSPOutFlag16_19]>;
 774
 775 class MULT_DSP_DESC  : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
 776 class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
 777 class MADD_DSP_DESC  : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
 778 class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
 779 class MSUB_DSP_DESC  : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
 780 class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
 781
 782 // Comparison
 783 class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
 784                                                int_mips_cmpu_eq_qb, NoItinerary,
 785                                                DSPROpnd>,
 786                         IsCommutable, Defs<[DSPCCond]>;
 787
 788 class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
 789                                                int_mips_cmpu_lt_qb, NoItinerary,
 790                                                DSPROpnd>, Defs<[DSPCCond]>;
 791
 792 class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
 793                                                int_mips_cmpu_le_qb, NoItinerary,
 794                                                DSPROpnd>, Defs<[DSPCCond]>;
 795
 796 class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
 797                                                 int_mips_cmpgu_eq_qb,
 798                                                 NoItinerary, GPR32Opnd, DSPROpnd>,
 799                          IsCommutable;
 800
 801 class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
 802                                                 int_mips_cmpgu_lt_qb,
 803                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 804
 805 class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
 806                                                 int_mips_cmpgu_le_qb,
 807                                                 NoItinerary, GPR32Opnd, DSPROpnd>;
 808
 809 class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
 810                                               NoItinerary, DSPROpnd>,
 811                        IsCommutable, Defs<[DSPCCond]>;
 812
 813 class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
 814                                               NoItinerary, DSPROpnd>,
 815                        Defs<[DSPCCond]>;
 816
 817 class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
 818                                               NoItinerary, DSPROpnd>,
 819                        Defs<[DSPCCond]>;
 820
 821 // Misc
 822 class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 823                                            NoItinerary, GPR32Opnd>;
 824
 825 class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
 826                                               NoItinerary, DSPROpnd, DSPROpnd>;
 827
 828 class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, immZExt8,
 829                                     NoItinerary, DSPROpnd>;
 830
 831 class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, immZExt10,
 832                                     NoItinerary, DSPROpnd>;
 833
 834 class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
 835                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 836
 837 class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
 838                                              NoItinerary, DSPROpnd, GPR32Opnd>;
 839
 840 class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
 841                                             NoItinerary, DSPROpnd, DSPROpnd>,
 842                      Uses<[DSPCCond]>;
 843
 844 class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
 845                                             NoItinerary, DSPROpnd, DSPROpnd>,
 846                      Uses<[DSPCCond]>;
 847
 848 class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
 849
 850 class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
 851
 852 class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
 853
 854 class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
 855
 856 // Extr
 857 class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
 858                   Uses<[DSPPos]>, Defs<[DSPEFI]>;
 859
 860 class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", MipsEXTP, NoItinerary>,
 861                    Uses<[DSPPos]>, Defs<[DSPEFI]>;
 862
 863 class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", MipsEXTPDP, NoItinerary>,
 864                     Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 865
 866 class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", MipsEXTPDP,
 867                                              NoItinerary>,
 868                      Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
 869
 870 class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", MipsEXTR_W, NoItinerary>,
 871                     Defs<[DSPOutFlag23]>;
 872
 873 class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", MipsEXTR_W,
 874                                              NoItinerary>, Defs<[DSPOutFlag23]>;
 875
 876 class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", MipsEXTR_R_W,
 877                                               NoItinerary>,
 878                       Defs<[DSPOutFlag23]>;
 879
 880 class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", MipsEXTR_R_W,
 881                                                NoItinerary>,
 882                        Defs<[DSPOutFlag23]>;
 883
 884 class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", MipsEXTR_RS_W,
 885                                                NoItinerary>,
 886                        Defs<[DSPOutFlag23]>;
 887
 888 class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", MipsEXTR_RS_W,
 889                                                 NoItinerary>,
 890                         Defs<[DSPOutFlag23]>;
 891
 892 class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", MipsEXTR_S_H,
 893                                               NoItinerary>,
 894                       Defs<[DSPOutFlag23]>;
 895
 896 class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", MipsEXTR_S_H,
 897                                                NoItinerary>,
 898                        Defs<[DSPOutFlag23]>;
 899
 900 class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
 901
 902 class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
 903
 904 class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
 905
 906 class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
 907
 908 class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
 909
 910 class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
 911                   Uses<[DSPPos, DSPSCount]>;
 912
 913 //===----------------------------------------------------------------------===//
 914 // MIPS DSP Rev 2
 915 // Addition/subtraction
 916 class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
 917                                        DSPROpnd, DSPROpnd>, IsCommutable,
 918                      Defs<[DSPOutFlag20]>;
 919
 920 class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
 921                                          NoItinerary, DSPROpnd, DSPROpnd>,
 922                        IsCommutable, Defs<[DSPOutFlag20]>;
 923
 924 class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
 925                                        DSPROpnd, DSPROpnd>,
 926                      Defs<[DSPOutFlag20]>;
 927
 928 class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
 929                                          NoItinerary, DSPROpnd, DSPROpnd>,
 930                        Defs<[DSPOutFlag20]>;
 931
 932 class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
 933                                          NoItinerary, DSPROpnd>, IsCommutable;
 934
 935 class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
 936                                            NoItinerary, DSPROpnd>, IsCommutable;
 937
 938 class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
 939                                          NoItinerary, DSPROpnd>;
 940
 941 class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
 942                                            NoItinerary, DSPROpnd>;
 943
 944 class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
 945                                          NoItinerary, DSPROpnd>, IsCommutable;
 946
 947 class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
 948                                            NoItinerary, DSPROpnd>, IsCommutable;
 949
 950 class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
 951                                          NoItinerary, DSPROpnd>;
 952
 953 class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
 954                                            NoItinerary, DSPROpnd>;
 955
 956 class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
 957                                         NoItinerary, GPR32Opnd>, IsCommutable;
 958
 959 class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
 960                                           NoItinerary, GPR32Opnd>, IsCommutable;
 961
 962 class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
 963                                         NoItinerary, GPR32Opnd>;
 964
 965 class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
 966                                           NoItinerary, GPR32Opnd>;
 967
 968 // Comparison
 969 class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
 970                                                  int_mips_cmpgdu_eq_qb,
 971                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 972                           IsCommutable, Defs<[DSPCCond]>;
 973
 974 class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
 975                                                  int_mips_cmpgdu_lt_qb,
 976                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 977                           Defs<[DSPCCond]>;
 978
 979 class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
 980                                                  int_mips_cmpgdu_le_qb,
 981                                                  NoItinerary, GPR32Opnd, DSPROpnd>,
 982                           Defs<[DSPCCond]>;
 983
 984 // Absolute
 985 class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
 986                                               NoItinerary, DSPROpnd>,
 987                        Defs<[DSPOutFlag20]>;
 988
 989 // Multiplication
 990 class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
 991                                        DSPROpnd>, IsCommutable,
 992                     Defs<[DSPOutFlag21]>;
 993
 994 class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
 995                                          NoItinerary, DSPROpnd>, IsCommutable,
 996                       Defs<[DSPOutFlag21]>;
 997
 998 class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
 999                                          NoItinerary, GPR32Opnd>, IsCommutable,
1000                       Defs<[DSPOutFlag21]>;
1001
1002 class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
1003                                           NoItinerary, GPR32Opnd>, IsCommutable,
1004                        Defs<[DSPOutFlag21]>;
1005
1006 class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
1007                                          NoItinerary, DSPROpnd, DSPROpnd>,
1008                        IsCommutable, Defs<[DSPOutFlag21]>;
1009
1010 // Dot product with accumulate/subtract
1011 class DPA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpa.w.ph", MipsDPA_W_PH>;
1012
1013 class DPS_W_PH_DESC : DPA_W_PH_DESC_BASE<"dps.w.ph", MipsDPS_W_PH>;
1014
1015 class DPAQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_s.w.ph", MipsDPAQX_S_W_PH>,
1016                           Defs<[DSPOutFlag16_19]>;
1017
1018 class DPAQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpaqx_sa.w.ph",
1019                                               MipsDPAQX_SA_W_PH>,
1020                            Defs<[DSPOutFlag16_19]>;
1021
1022 class DPAX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpax.w.ph", MipsDPAX_W_PH>;
1023
1024 class DPSX_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsx.w.ph", MipsDPSX_W_PH>;
1025
1026 class DPSQX_S_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_s.w.ph", MipsDPSQX_S_W_PH>,
1027                           Defs<[DSPOutFlag16_19]>;
1028
1029 class DPSQX_SA_W_PH_DESC : DPA_W_PH_DESC_BASE<"dpsqx_sa.w.ph",
1030                                               MipsDPSQX_SA_W_PH>,
1031                            Defs<[DSPOutFlag16_19]>;
1032
1033 class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH>;
1034
1035 // Precision reduce/expand
1036 class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
1037                                                 int_mips_precr_qb_ph,
1038                                                 NoItinerary, DSPROpnd, DSPROpnd>;
1039
1040 class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
1041                                                      int_mips_precr_sra_ph_w,
1042                                                      NoItinerary, DSPROpnd,
1043                                                      GPR32Opnd>;
1044
1045 class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
1046                                                       int_mips_precr_sra_r_ph_w,
1047                                                        NoItinerary, DSPROpnd,
1048                                                        GPR32Opnd>;
1049
1050 // Shift
1051 class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
1052                                           NoItinerary, DSPROpnd>;
1053
1054 class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
1055                                            NoItinerary, DSPROpnd>;
1056
1057 class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
1058                                             immZExt3, NoItinerary, DSPROpnd>;
1059
1060 class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
1061                                              NoItinerary, DSPROpnd>;
1062
1063 class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
1064                                           NoItinerary, DSPROpnd>;
1065
1066 class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
1067                                            NoItinerary, DSPROpnd>;
1068
1069 // Misc
1070 class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, immZExt5,
1071                                      NoItinerary>;
1072
1073 class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, immZExt2,
1074                                      NoItinerary>;
1075
1076 class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, immZExt5,
1077                                       NoItinerary>;
1078
1079 // Pseudos.
1080 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
1081                                                 NoItinerary>, Uses<[DSPPos]>;
1082
1083 // Instruction defs.
1084 // MIPS DSP Rev 1
1085 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
1086 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
1087 def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
1088 def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
1089 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
1090 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
1091 def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
1092 def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
1093 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
1094 def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
1095 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
1096 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
1097 def MODSUB : MODSUB_ENC, MODSUB_DESC;
1098 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
1099 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
1100 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
1101 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
1102 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
1103 def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
1104 def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
1105 def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
1106 def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
1107 def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
1108 def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
1109 def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
1110 def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
1111 def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
1112 def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
1113 def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
1114 def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
1115 def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
1116 def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
1117 def SHRL_QB : SHRL_QB_ENC, SHRL_QB_DESC;
1118 def SHRLV_QB : SHRLV_QB_ENC, SHRLV_QB_DESC;
1119 def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
1120 def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
1121 def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
1122 def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
1123 def SHRA_PH : SHRA_PH_ENC, SHRA_PH_DESC;
1124 def SHRAV_PH : SHRAV_PH_ENC, SHRAV_PH_DESC;
1125 def SHRA_R_PH : SHRA_R_PH_ENC, SHRA_R_PH_DESC;
1126 def SHRAV_R_PH : SHRAV_R_PH_ENC, SHRAV_R_PH_DESC;
1127 def SHLL_S_W : DspMMRel, SHLL_S_W_ENC, SHLL_S_W_DESC;
1128 def SHLLV_S_W : DspMMRel, SHLLV_S_W_ENC, SHLLV_S_W_DESC;
1129 def SHRA_R_W : SHRA_R_W_ENC, SHRA_R_W_DESC;
1130 def SHRAV_R_W : SHRAV_R_W_ENC, SHRAV_R_W_DESC;
1131 def MULEU_S_PH_QBL : MULEU_S_PH_QBL_ENC, MULEU_S_PH_QBL_DESC;
1132 def MULEU_S_PH_QBR : MULEU_S_PH_QBR_ENC, MULEU_S_PH_QBR_DESC;
1133 def MULEQ_S_W_PHL : MULEQ_S_W_PHL_ENC, MULEQ_S_W_PHL_DESC;
1134 def MULEQ_S_W_PHR : MULEQ_S_W_PHR_ENC, MULEQ_S_W_PHR_DESC;
1135 def MULQ_RS_PH : MULQ_RS_PH_ENC, MULQ_RS_PH_DESC;
1136 def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
1137 def MAQ_S_W_PHL : MAQ_S_W_PHL_ENC, MAQ_S_W_PHL_DESC;
1138 def MAQ_S_W_PHR : MAQ_S_W_PHR_ENC, MAQ_S_W_PHR_DESC;
1139 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
1140 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
1141 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
1142 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
1143 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
1144 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
1145 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
1146 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
1147 def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
1148 def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
1149 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
1150 def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
1151 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
1152 def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
1153 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
1154 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
1155 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
1156 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
1157 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
1158 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
1159 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
1160 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
1161 def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
1162 def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
1163 def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
1164 def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
1165 def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
1166 def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
1167 def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
1168 def BITREV : BITREV_ENC, BITREV_DESC;
1169 def PACKRL_PH : PACKRL_PH_ENC, PACKRL_PH_DESC;
1170 def REPL_QB : REPL_QB_ENC, REPL_QB_DESC;
1171 def REPL_PH : REPL_PH_ENC, REPL_PH_DESC;
1172 def REPLV_QB : REPLV_QB_ENC, REPLV_QB_DESC;
1173 def REPLV_PH : REPLV_PH_ENC, REPLV_PH_DESC;
1174 def PICK_QB : PICK_QB_ENC, PICK_QB_DESC;
1175 def PICK_PH : PICK_PH_ENC, PICK_PH_DESC;
1176 def LWX : LWX_ENC, LWX_DESC;
1177 def LHX : LHX_ENC, LHX_DESC;
1178 def LBUX : LBUX_ENC, LBUX_DESC;
1179 def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
1180 def INSV : DspMMRel, INSV_ENC, INSV_DESC;
1181 def EXTP : EXTP_ENC, EXTP_DESC;
1182 def EXTPV : EXTPV_ENC, EXTPV_DESC;
1183 def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
1184 def EXTPDPV : EXTPDPV_ENC, EXTPDPV_DESC;
1185 def EXTR_W : EXTR_W_ENC, EXTR_W_DESC;
1186 def EXTRV_W : EXTRV_W_ENC, EXTRV_W_DESC;
1187 def EXTR_R_W : EXTR_R_W_ENC, EXTR_R_W_DESC;
1188 def EXTRV_R_W : EXTRV_R_W_ENC, EXTRV_R_W_DESC;
1189 def EXTR_RS_W : EXTR_RS_W_ENC, EXTR_RS_W_DESC;
1190 def EXTRV_RS_W : EXTRV_RS_W_ENC, EXTRV_RS_W_DESC;
1191 def EXTR_S_H : EXTR_S_H_ENC, EXTR_S_H_DESC;
1192 def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC;
1193 def SHILO : SHILO_ENC, SHILO_DESC;
1194 def SHILOV : SHILOV_ENC, SHILOV_DESC;
1195 def MTHLIP : MTHLIP_ENC, MTHLIP_DESC;
1196 def RDDSP : RDDSP_ENC, RDDSP_DESC;
1197 def WRDSP : WRDSP_ENC, WRDSP_DESC;
1198
1199 // MIPS DSP Rev 2
1200 let Predicates = [HasDSPR2] in {
1201
1202 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
1203 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
1204 def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
1205 def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
1206 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
1207 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
1208 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
1209 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
1210 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
1211 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
1212 def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
1213 def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
1214 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
1215 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
1216 def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
1217 def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
1218 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
1219 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
1220 def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
1221 def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
1222 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
1223 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
1224 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
1225 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
1226 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
1227 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
1228 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
1229 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
1230 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
1231 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
1232 def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
1233 def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
1234 def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
1235 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
1236 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
1237 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
1238 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
1239 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
1240 def SHRAV_QB : SHRAV_QB_ENC, SHRAV_QB_DESC;
1241 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
1242 def SHRAV_R_QB : SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;
1243 def SHRL_PH : SHRL_PH_ENC, SHRL_PH_DESC;
1244 def SHRLV_PH : SHRLV_PH_ENC, SHRLV_PH_DESC;
1245 def APPEND : APPEND_ENC, APPEND_DESC;
1246 def BALIGN : BALIGN_ENC, BALIGN_DESC;
1247 def PREPEND : PREPEND_ENC, PREPEND_DESC;
1248
1249 }
1250
1251 // Pseudos.
1252 let isPseudo = 1, isCodeGenOnly = 1 in {
1253   // Pseudo instructions for loading and storing accumulator registers.
1254   def LOAD_ACC64DSP  : Load<"", ACC64DSPOpnd>;
1255   def STORE_ACC64DSP : Store<"", ACC64DSPOpnd>;
1256
1257   // Pseudos for loading and storing ccond field of DSP control register.
1258   def LOAD_CCOND_DSP  : Load<"load_ccond_dsp", DSPCC>;
1259   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
1260 }
1261
1262 // Pseudo CMP and PICK instructions.
1263 class PseudoCMP<Instruction RealInst> :
1264   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
1265   PseudoInstExpansion<(RealInst DSPROpnd:$rs, DSPROpnd:$rt)>, NeverHasSideEffects;
1266
1267 class PseudoPICK<Instruction RealInst> :
1268   PseudoDSP<(outs DSPROpnd:$rd), (ins DSPCC:$cmp, DSPROpnd:$rs, DSPROpnd:$rt), []>,
1269   PseudoInstExpansion<(RealInst DSPROpnd:$rd, DSPROpnd:$rs, DSPROpnd:$rt)>,
1270   NeverHasSideEffects;
1271
1272 def PseudoCMP_EQ_PH : PseudoCMP<CMP_EQ_PH>;
1273 def PseudoCMP_LT_PH : PseudoCMP<CMP_LT_PH>;
1274 def PseudoCMP_LE_PH : PseudoCMP<CMP_LE_PH>;
1275 def PseudoCMPU_EQ_QB : PseudoCMP<CMPU_EQ_QB>;
1276 def PseudoCMPU_LT_QB : PseudoCMP<CMPU_LT_QB>;
1277 def PseudoCMPU_LE_QB : PseudoCMP<CMPU_LE_QB>;
1278
1279 def PseudoPICK_PH : PseudoPICK<PICK_PH>;
1280 def PseudoPICK_QB : PseudoPICK<PICK_QB>;
1281
1282 def PseudoMTLOHI_DSP : PseudoMTLOHI<ACC64DSP, GPR32>;
1283
1284 // Patterns.
1285 class DSPPat<dag pattern, dag result, Predicate pred = HasDSP> :
1286   Pat<pattern, result>, Requires<[pred]>;
1287
1288 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1289                     RegisterClass SrcRC> :
1290    DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1291           (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
1292
1293 def : BitconvertPat<i32, v2i16, GPR32, DSPR>;
1294 def : BitconvertPat<i32, v4i8, GPR32, DSPR>;
1295 def : BitconvertPat<v2i16, i32, DSPR, GPR32>;
1296 def : BitconvertPat<v4i8, i32, DSPR, GPR32>;
1297
1298 def : DSPPat<(v2i16 (load addr:$a)),
1299              (v2i16 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1300 def : DSPPat<(v4i8 (load addr:$a)),
1301              (v4i8 (COPY_TO_REGCLASS (LW addr:$a), DSPR))>;
1302 def : DSPPat<(store (v2i16 DSPR:$val), addr:$a),
1303              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1304 def : DSPPat<(store (v4i8 DSPR:$val), addr:$a),
1305              (SW (COPY_TO_REGCLASS DSPR:$val, GPR32), addr:$a)>;
1306
1307 // Binary operations.
1308 class DSPBinPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1309                 Predicate Pred = HasDSP> :
1310   DSPPat<(Node ValTy:$a, ValTy:$b), (Inst ValTy:$a, ValTy:$b), Pred>;
1311
1312 def : DSPBinPat<ADDQ_PH, v2i16, int_mips_addq_ph>;
1313 def : DSPBinPat<ADDQ_PH, v2i16, add>;
1314 def : DSPBinPat<SUBQ_PH, v2i16, int_mips_subq_ph>;
1315 def : DSPBinPat<SUBQ_PH, v2i16, sub>;
1316 def : DSPBinPat<MUL_PH, v2i16, int_mips_mul_ph, HasDSPR2>;
1317 def : DSPBinPat<MUL_PH, v2i16, mul, HasDSPR2>;
1318 def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
1319 def : DSPBinPat<ADDU_QB, v4i8, add>;
1320 def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
1321 def : DSPBinPat<SUBU_QB, v4i8, sub>;
1322 def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
1323 def : DSPBinPat<ADDSC, i32, addc>;
1324 def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
1325 def : DSPBinPat<ADDWC, i32, adde>;
1326
1327 // Shift immediate patterns.
1328 class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
1329                   SDPatternOperator Imm, Predicate Pred = HasDSP> :
1330   DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
1331
1332 def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
1333 def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
1334 def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
1335 def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
1336 def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
1337 def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
1338 def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
1339 def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
1340 def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
1341 def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
1342 def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
1343 def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;
1344
1345 // SETCC/SELECT_CC patterns.
1346 class DSPSetCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1347                   CondCode CC> :
1348   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1349          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1350                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1351                       (ValTy ZERO)))>;
1352
1353 class DSPSetCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1354                      CondCode CC> :
1355   DSPPat<(ValTy (MipsSETCC_DSP ValTy:$a, ValTy:$b, CC)),
1356          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)),
1357                       (ValTy ZERO),
1358                       (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
1359
1360 class DSPSelectCCPat<Instruction Cmp, Instruction Pick, ValueType ValTy,
1361                      CondCode CC> :
1362   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1363          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $c, $d))>;
1364
1365 class DSPSelectCCPatInv<Instruction Cmp, Instruction Pick, ValueType ValTy,
1366                         CondCode CC> :
1367   DSPPat<(ValTy (MipsSELECT_CC_DSP ValTy:$a, ValTy:$b, ValTy:$c, ValTy:$d, CC)),
1368          (ValTy (Pick (ValTy (Cmp ValTy:$a, ValTy:$b)), $d, $c))>;
1369
1370 def : DSPSetCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1371 def : DSPSetCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1372 def : DSPSetCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1373 def : DSPSetCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1374 def : DSPSetCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1375 def : DSPSetCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1376 def : DSPSetCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1377 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1378 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1379 def : DSPSetCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1380 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1381 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1382
1383 def : DSPSelectCCPat<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETEQ>;
1384 def : DSPSelectCCPat<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETLT>;
1385 def : DSPSelectCCPat<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETLE>;
1386 def : DSPSelectCCPatInv<PseudoCMP_EQ_PH, PseudoPICK_PH, v2i16, SETNE>;
1387 def : DSPSelectCCPatInv<PseudoCMP_LT_PH, PseudoPICK_PH, v2i16, SETGE>;
1388 def : DSPSelectCCPatInv<PseudoCMP_LE_PH, PseudoPICK_PH, v2i16, SETGT>;
1389 def : DSPSelectCCPat<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETEQ>;
1390 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1391 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1392 def : DSPSelectCCPatInv<PseudoCMPU_EQ_QB, PseudoPICK_QB, v4i8, SETNE>;
1393 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1394 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1395
1396 // Extr patterns.
1397 class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
1398   DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
1399          (Instr ACC64DSP:$ac, GPR32:$rs)>;
1400
1401 class EXTR_W_TY1_R1_Pat<SDPatternOperator OpNode, Instruction Instr> :
1402   DSPPat<(i32 (OpNode immZExt5:$shift, ACC64DSP:$ac)),
1403          (Instr ACC64DSP:$ac, immZExt5:$shift)>;
1404
1405 def : EXTR_W_TY1_R1_Pat<MipsEXTP, EXTP>;
1406 def : EXTR_W_TY1_R2_Pat<MipsEXTP, EXTPV>;
1407 def : EXTR_W_TY1_R1_Pat<MipsEXTPDP, EXTPDP>;
1408 def : EXTR_W_TY1_R2_Pat<MipsEXTPDP, EXTPDPV>;
1409 def : EXTR_W_TY1_R1_Pat<MipsEXTR_W, EXTR_W>;
1410 def : EXTR_W_TY1_R2_Pat<MipsEXTR_W, EXTRV_W>;
1411 def : EXTR_W_TY1_R1_Pat<MipsEXTR_R_W, EXTR_R_W>;
1412 def : EXTR_W_TY1_R2_Pat<MipsEXTR_R_W, EXTRV_R_W>;
1413 def : EXTR_W_TY1_R1_Pat<MipsEXTR_RS_W, EXTR_RS_W>;
1414 def : EXTR_W_TY1_R2_Pat<MipsEXTR_RS_W, EXTRV_RS_W>;
1415 def : EXTR_W_TY1_R1_Pat<MipsEXTR_S_H, EXTR_S_H>;
1416 def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
1417
1418 // Indexed load patterns.
1419 class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
1420   DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
1421          (Instr i32:$base, i32:$index)>;
1422
1423 let AddedComplexity = 20 in {
1424   def : IndexedLoadPat<zextloadi8, LBUX>;
1425   def : IndexedLoadPat<sextloadi16, LHX>;
1426   def : IndexedLoadPat<load, LWX>;
1427 }