1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/IR/BasicBlock.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/Mangler.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCSectionELF.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "mips-asm-printer"
56 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
57 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
60 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
61 // Initialize TargetLoweringObjectFile.
62 if (Subtarget->allowMixed16_32())
63 const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
64 .Initialize(OutContext, TM);
65 MipsFI = MF.getInfo<MipsFunctionInfo>();
66 if (Subtarget->inMips16Mode())
69 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
70 it = MipsFI->StubsNeeded.begin();
71 it != MipsFI->StubsNeeded.end(); ++it) {
72 const char *Symbol = it->first;
73 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
74 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
75 StubsNeeded[Symbol] = Signature;
77 MCP = MF.getConstantPool();
79 // In NaCl, all indirect jump targets must be aligned to bundle size.
80 if (Subtarget->isTargetNaCl())
81 NaClAlignIndirectJumpTargets(MF);
83 AsmPrinter::runOnMachineFunction(MF);
87 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
88 MCOp = MCInstLowering.LowerOperand(MO);
89 return MCOp.isValid();
92 #include "MipsGenMCPseudoLowering.inc"
94 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
95 // JALR, or JALR64 as appropriate for the target
96 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
97 const MachineInstr *MI) {
98 bool HasLinkReg = false;
101 if (Subtarget->hasMips64r6()) {
102 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
103 TmpInst0.setOpcode(Mips::JALR64);
105 } else if (Subtarget->hasMips32r6()) {
106 // MIPS32r6 should use (JALR ZERO, $rs)
107 TmpInst0.setOpcode(Mips::JALR);
109 } else if (Subtarget->inMicroMipsMode())
110 // microMIPS should use (JR_MM $rs)
111 TmpInst0.setOpcode(Mips::JR_MM);
113 // Everything else should use (JR $rs)
114 TmpInst0.setOpcode(Mips::JR);
120 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
121 TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
124 lowerOperand(MI->getOperand(0), MCOp);
125 TmpInst0.addOperand(MCOp);
127 EmitToStreamer(OutStreamer, TmpInst0);
130 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
131 MipsTargetStreamer &TS = getTargetStreamer();
132 TS.setCanHaveModuleDir(false);
134 if (MI->isDebugValue()) {
135 SmallString<128> Str;
136 raw_svector_ostream OS(Str);
138 PrintDebugValueComment(MI, OS);
142 // If we just ended a constant pool, mark it as such.
143 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
144 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
145 InConstantPool = false;
147 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
148 // CONSTPOOL_ENTRY - This instruction represents a floating
149 //constant pool in the function. The first operand is the ID#
150 // for this instruction, the second is the index into the
151 // MachineConstantPool that this is, the third is the size in
152 // bytes of this constant pool entry.
153 // The required alignment is specified on the basic block holding this MI.
155 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
156 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
158 // If this is the first entry of the pool, mark it.
159 if (!InConstantPool) {
160 OutStreamer.EmitDataRegion(MCDR_DataRegion);
161 InConstantPool = true;
164 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
166 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
167 if (MCPE.isMachineConstantPoolEntry())
168 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
170 EmitGlobalConstant(MCPE.Val.ConstVal);
175 MachineBasicBlock::const_instr_iterator I = MI;
176 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
179 // Do any auto-generated pseudo lowerings.
180 if (emitPseudoExpansionLowering(OutStreamer, &*I))
183 if (I->getOpcode() == Mips::PseudoReturn ||
184 I->getOpcode() == Mips::PseudoReturn64 ||
185 I->getOpcode() == Mips::PseudoIndirectBranch ||
186 I->getOpcode() == Mips::PseudoIndirectBranch64) {
187 emitPseudoIndirectBranch(OutStreamer, &*I);
191 // The inMips16Mode() test is not permanent.
192 // Some instructions are marked as pseudo right now which
193 // would make the test fail for the wrong reason but
194 // that will be fixed soon. We need this here because we are
195 // removing another test for this situation downstream in the
198 if (I->isPseudo() && !Subtarget->inMips16Mode()
199 && !isLongBranchPseudo(I->getOpcode()))
200 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
203 MCInstLowering.Lower(I, TmpInst0);
204 EmitToStreamer(OutStreamer, TmpInst0);
205 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
208 //===----------------------------------------------------------------------===//
210 // Mips Asm Directives
212 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
213 // Describe the stack frame.
215 // -- Mask directives "(f)mask bitmask, offset"
216 // Tells the assembler which registers are saved and where.
217 // bitmask - contain a little endian bitset indicating which registers are
218 // saved on function prologue (e.g. with a 0x80000000 mask, the
219 // assembler knows the register 31 (RA) is saved at prologue.
220 // offset - the position before stack pointer subtraction indicating where
221 // the first saved register on prologue is located. (e.g. with a
223 // Consider the following function prologue:
226 // .mask 0xc0000000,-8
227 // addiu $sp, $sp, -48
231 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
232 // 30 (FP) are saved at prologue. As the save order on prologue is from
233 // left to right, RA is saved first. A -8 offset means that after the
234 // stack pointer subtration, the first register in the mask (RA) will be
235 // saved at address 48-8=40.
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
241 //===----------------------------------------------------------------------===//
243 // Create a bitmask with all callee saved registers for CPU or Floating Point
244 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
245 void MipsAsmPrinter::printSavedRegsBitmask() {
246 // CPU and FPU Saved Registers Bitmasks
247 unsigned CPUBitmask = 0, FPUBitmask = 0;
248 int CPUTopSavedRegOff, FPUTopSavedRegOff;
250 // Set the CPU and FPU Bitmasks
251 const MachineFrameInfo *MFI = MF->getFrameInfo();
252 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
253 // size of stack area to which FP callee-saved regs are saved.
254 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
255 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
256 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
257 bool HasAFGR64Reg = false;
258 unsigned CSFPRegsSize = 0;
259 unsigned i, e = CSI.size();
262 for (i = 0; i != e; ++i) {
263 unsigned Reg = CSI[i].getReg();
264 if (Mips::GPR32RegClass.contains(Reg))
267 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
268 if (Mips::AFGR64RegClass.contains(Reg)) {
269 FPUBitmask |= (3 << RegNum);
270 CSFPRegsSize += AFGR64RegSize;
275 FPUBitmask |= (1 << RegNum);
276 CSFPRegsSize += FGR32RegSize;
280 for (; i != e; ++i) {
281 unsigned Reg = CSI[i].getReg();
282 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
283 CPUBitmask |= (1 << RegNum);
286 // FP Regs are saved right below where the virtual frame pointer points to.
287 FPUTopSavedRegOff = FPUBitmask ?
288 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
290 // CPU Regs are saved below FP Regs.
291 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
293 MipsTargetStreamer &TS = getTargetStreamer();
295 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
298 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
301 //===----------------------------------------------------------------------===//
302 // Frame and Set directives
303 //===----------------------------------------------------------------------===//
306 void MipsAsmPrinter::emitFrameDirective() {
307 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
309 unsigned stackReg = RI.getFrameRegister(*MF);
310 unsigned returnReg = RI.getRARegister();
311 unsigned stackSize = MF->getFrameInfo()->getStackSize();
313 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
316 /// Emit Set directives.
317 const char *MipsAsmPrinter::getCurrentABIString() const {
318 switch (Subtarget->getTargetABI()) {
319 case MipsSubtarget::O32: return "abi32";
320 case MipsSubtarget::N32: return "abiN32";
321 case MipsSubtarget::N64: return "abi64";
322 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
323 default: llvm_unreachable("Unknown Mips ABI");
327 void MipsAsmPrinter::EmitFunctionEntryLabel() {
328 MipsTargetStreamer &TS = getTargetStreamer();
330 // NaCl sandboxing requires that indirect call instructions are masked.
331 // This means that function entry points should be bundle-aligned.
332 if (Subtarget->isTargetNaCl())
333 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
335 if (Subtarget->inMicroMipsMode())
336 TS.emitDirectiveSetMicroMips();
338 TS.emitDirectiveSetNoMicroMips();
340 if (Subtarget->inMips16Mode())
341 TS.emitDirectiveSetMips16();
343 TS.emitDirectiveSetNoMips16();
345 TS.emitDirectiveEnt(*CurrentFnSym);
346 OutStreamer.EmitLabel(CurrentFnSym);
349 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
350 /// the first basic block in the function.
351 void MipsAsmPrinter::EmitFunctionBodyStart() {
352 MipsTargetStreamer &TS = getTargetStreamer();
354 MCInstLowering.Initialize(&MF->getContext());
356 bool IsNakedFunction =
358 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
360 if (!IsNakedFunction)
361 emitFrameDirective();
363 if (!IsNakedFunction)
364 printSavedRegsBitmask();
366 if (!Subtarget->inMips16Mode()) {
367 TS.emitDirectiveSetNoReorder();
368 TS.emitDirectiveSetNoMacro();
369 TS.emitDirectiveSetNoAt();
373 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
374 /// the last basic block in the function.
375 void MipsAsmPrinter::EmitFunctionBodyEnd() {
376 MipsTargetStreamer &TS = getTargetStreamer();
378 // There are instruction for this macros, but they must
379 // always be at the function end, and we can't emit and
380 // break with BB logic.
381 if (!Subtarget->inMips16Mode()) {
382 TS.emitDirectiveSetAt();
383 TS.emitDirectiveSetMacro();
384 TS.emitDirectiveSetReorder();
386 TS.emitDirectiveEnd(CurrentFnSym->getName());
387 // Make sure to terminate any constant pools that were at the end
391 InConstantPool = false;
392 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
395 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
396 /// exactly one predecessor and the control transfer mechanism between
397 /// the predecessor and this block is a fall-through.
398 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
400 // The predecessor has to be immediately before this block.
401 const MachineBasicBlock *Pred = *MBB->pred_begin();
403 // If the predecessor is a switch statement, assume a jump table
404 // implementation, so it is not a fall through.
405 if (const BasicBlock *bb = Pred->getBasicBlock())
406 if (isa<SwitchInst>(bb->getTerminator()))
409 // If this is a landing pad, it isn't a fall through. If it has no preds,
410 // then nothing falls through to it.
411 if (MBB->isLandingPad() || MBB->pred_empty())
414 // If there isn't exactly one predecessor, it can't be a fall through.
415 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
418 if (PI2 != MBB->pred_end())
421 // The predecessor has to be immediately before this block.
422 if (!Pred->isLayoutSuccessor(MBB))
425 // If the block is completely empty, then it definitely does fall through.
429 // Otherwise, check the last instruction.
430 // Check if the last terminator is an unconditional branch.
431 MachineBasicBlock::const_iterator I = Pred->end();
432 while (I != Pred->begin() && !(--I)->isTerminator()) ;
434 return !I->isBarrier();
437 // Print out an operand for an inline asm expression.
438 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
439 unsigned AsmVariant,const char *ExtraCode,
441 // Does this asm operand have a single letter operand modifier?
442 if (ExtraCode && ExtraCode[0]) {
443 if (ExtraCode[1] != 0) return true; // Unknown modifier.
445 const MachineOperand &MO = MI->getOperand(OpNum);
446 switch (ExtraCode[0]) {
448 // See if this is a generic print operand
449 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
450 case 'X': // hex const int
451 if ((MO.getType()) != MachineOperand::MO_Immediate)
453 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
455 case 'x': // hex const int (low 16 bits)
456 if ((MO.getType()) != MachineOperand::MO_Immediate)
458 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
460 case 'd': // decimal const int
461 if ((MO.getType()) != MachineOperand::MO_Immediate)
465 case 'm': // decimal const int minus 1
466 if ((MO.getType()) != MachineOperand::MO_Immediate)
468 O << MO.getImm() - 1;
471 // $0 if zero, regular printing otherwise
472 if (MO.getType() != MachineOperand::MO_Immediate)
474 int64_t Val = MO.getImm();
481 case 'D': // Second part of a double word register operand
482 case 'L': // Low order register of a double word register operand
483 case 'M': // High order register of a double word register operand
487 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
488 if (!FlagsOP.isImm())
490 unsigned Flags = FlagsOP.getImm();
491 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
492 // Number of registers represented by this operand. We are looking
493 // for 2 for 32 bit mode and 1 for 64 bit mode.
495 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
496 unsigned Reg = MO.getReg();
497 O << '$' << MipsInstPrinter::getRegisterName(Reg);
503 unsigned RegOp = OpNum;
504 if (!Subtarget->isGP64bit()){
505 // Endianess reverses which register holds the high or low value
507 switch(ExtraCode[0]) {
509 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
512 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
514 case 'D': // Always the second part
517 if (RegOp >= MI->getNumOperands())
519 const MachineOperand &MO = MI->getOperand(RegOp);
522 unsigned Reg = MO.getReg();
523 O << '$' << MipsInstPrinter::getRegisterName(Reg);
528 // Print MSA registers for the 'f' constraint
529 // In LLVM, the 'w' modifier doesn't need to do anything.
530 // We can just call printOperand as normal.
535 printOperand(MI, OpNum, O);
539 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
540 unsigned OpNum, unsigned AsmVariant,
541 const char *ExtraCode,
544 // Currently we are expecting either no ExtraCode or 'D'
546 if (ExtraCode[0] == 'D')
549 return true; // Unknown modifier.
552 const MachineOperand &MO = MI->getOperand(OpNum);
553 assert(MO.isReg() && "unexpected inline asm memory operand");
554 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
559 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
561 const DataLayout *DL = TM.getDataLayout();
562 const MachineOperand &MO = MI->getOperand(opNum);
565 if (MO.getTargetFlags())
568 switch(MO.getTargetFlags()) {
569 case MipsII::MO_GPREL: O << "%gp_rel("; break;
570 case MipsII::MO_GOT_CALL: O << "%call16("; break;
571 case MipsII::MO_GOT: O << "%got("; break;
572 case MipsII::MO_ABS_HI: O << "%hi("; break;
573 case MipsII::MO_ABS_LO: O << "%lo("; break;
574 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
575 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
576 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
577 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
578 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
579 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
580 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
581 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
582 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
585 switch (MO.getType()) {
586 case MachineOperand::MO_Register:
588 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
591 case MachineOperand::MO_Immediate:
595 case MachineOperand::MO_MachineBasicBlock:
596 O << *MO.getMBB()->getSymbol();
599 case MachineOperand::MO_GlobalAddress:
600 O << *getSymbol(MO.getGlobal());
603 case MachineOperand::MO_BlockAddress: {
604 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
609 case MachineOperand::MO_ConstantPoolIndex:
610 O << DL->getPrivateGlobalPrefix() << "CPI"
611 << getFunctionNumber() << "_" << MO.getIndex();
613 O << "+" << MO.getOffset();
617 llvm_unreachable("<unknown operand type>");
620 if (closeP) O << ")";
623 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
625 const MachineOperand &MO = MI->getOperand(opNum);
627 O << (unsigned short int)MO.getImm();
629 printOperand(MI, opNum, O);
632 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
634 const MachineOperand &MO = MI->getOperand(opNum);
636 O << (unsigned short int)(unsigned char)MO.getImm();
638 printOperand(MI, opNum, O);
641 void MipsAsmPrinter::
642 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
643 // Load/Store memory operands -- imm($reg)
644 // If PIC target the target is loaded as the
645 // pattern lw $25,%call16($28)
646 printOperand(MI, opNum+1, O);
648 printOperand(MI, opNum, O);
652 void MipsAsmPrinter::
653 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
654 // when using stack locations for not load/store instructions
655 // print the same way as all normal 3 operand instructions.
656 printOperand(MI, opNum, O);
658 printOperand(MI, opNum+1, O);
662 void MipsAsmPrinter::
663 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
664 const char *Modifier) {
665 const MachineOperand &MO = MI->getOperand(opNum);
666 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
669 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
670 // TODO: Need to add -mabicalls and -mno-abicalls flags.
671 // Currently we assume that -mabicalls is the default.
672 bool IsABICalls = true;
674 getTargetStreamer().emitDirectiveAbiCalls();
675 Reloc::Model RM = Subtarget->getRelocationModel();
676 // FIXME: This condition should be a lot more complicated that it is here.
677 // Ideally it should test for properties of the ABI and not the ABI
679 // For the moment, I'm only correcting enough to make MIPS-IV work.
680 if (RM == Reloc::Static && !Subtarget->isABI_N64())
681 getTargetStreamer().emitDirectiveOptionPic0();
684 // Tell the assembler which ABI we are using
685 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
686 OutStreamer.SwitchSection(OutContext.getELFSection(
687 SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
689 // NaN: At the moment we only support:
690 // 1. .nan legacy (default)
692 Subtarget->isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
693 : getTargetStreamer().emitDirectiveNaNLegacy();
695 // TODO: handle O64 ABI
697 if (Subtarget->isABI_EABI()) {
698 if (Subtarget->isGP32bit())
699 OutStreamer.SwitchSection(
700 OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
701 SectionKind::getDataRel()));
703 OutStreamer.SwitchSection(
704 OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
705 SectionKind::getDataRel()));
707 getTargetStreamer().updateABIInfo(*Subtarget);
708 getTargetStreamer().emitDirectiveModuleFP(
709 getTargetStreamer().getABIFlagsSection().FpABI, Subtarget->isABI_O32());
712 void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
714 I.setOpcode(Mips::JAL);
716 MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
717 OutStreamer.EmitInstruction(I, getSubtargetInfo());
720 void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
723 I.addOperand(MCOperand::CreateReg(Reg));
724 OutStreamer.EmitInstruction(I, getSubtargetInfo());
727 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
731 // Because of the current td files for Mips32, the operands for MTC1
732 // appear backwards from their normal assembly order. It's not a trivial
733 // change to fix this in the td file so we adjust for it here.
735 if (Opcode == Mips::MTC1) {
736 unsigned Temp = Reg1;
741 I.addOperand(MCOperand::CreateReg(Reg1));
742 I.addOperand(MCOperand::CreateReg(Reg2));
743 OutStreamer.EmitInstruction(I, getSubtargetInfo());
746 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
747 unsigned Reg2, unsigned Reg3) {
750 I.addOperand(MCOperand::CreateReg(Reg1));
751 I.addOperand(MCOperand::CreateReg(Reg2));
752 I.addOperand(MCOperand::CreateReg(Reg3));
753 OutStreamer.EmitInstruction(I, getSubtargetInfo());
756 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
757 unsigned Reg2, unsigned FPReg1,
758 unsigned FPReg2, bool LE) {
760 unsigned temp = Reg1;
764 EmitInstrRegReg(MovOpc, Reg1, FPReg1);
765 EmitInstrRegReg(MovOpc, Reg2, FPReg2);
768 void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
769 bool LE, bool ToFP) {
770 using namespace Mips16HardFloatInfo;
771 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
774 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
777 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
780 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
781 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
784 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
787 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
788 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
791 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
792 EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
800 MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
802 using namespace Mips16HardFloatInfo;
803 unsigned MovOpc = Mips::MFC1;
806 EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
809 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
812 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
815 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
816 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
823 void MipsAsmPrinter::EmitFPCallStub(
824 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
825 MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
826 using namespace Mips16HardFloatInfo;
827 bool LE = Subtarget->isLittle();
831 OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
834 // make the comment field identifying the return and parameter
835 // types of the floating point stub
836 // # Stub function to call rettype xxxx (params)
838 switch (Signature->RetSig) {
849 RetType = "double complex";
856 switch (Signature->ParamSig) {
861 Parms = "float, float";
864 Parms = "float, double";
870 Parms = "double, double";
873 Parms = "double, float";
879 OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
880 Twine(Symbol) + " (" + Twine(Parms) + ")");
882 // probably not necessary but we save and restore the current section state
884 OutStreamer.PushSection();
886 // .section mips16.call.fpxxxx,"ax",@progbits
888 const MCSectionELF *M = OutContext.getELFSection(
889 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
890 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
891 OutStreamer.SwitchSection(M, nullptr);
895 OutStreamer.EmitValueToAlignment(4);
896 MipsTargetStreamer &TS = getTargetStreamer();
901 TS.emitDirectiveSetNoMips16();
902 TS.emitDirectiveSetNoMicroMips();
904 // .ent __call_stub_fp_xxxx
905 // .type __call_stub_fp_xxxx,@function
906 // __call_stub_fp_xxxx:
908 std::string x = "__call_stub_fp_" + std::string(Symbol);
909 MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
910 TS.emitDirectiveEnt(*Stub);
912 OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
913 OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
914 OutStreamer.EmitLabel(Stub);
916 // we just handle non pic for now. these function will not be
917 // called otherwise. when the full stub generation is moved here
918 // we need to deal with pic.
920 if (Subtarget->getRelocationModel() == Reloc::PIC_)
921 llvm_unreachable("should not be here if we are compiling pic");
922 TS.emitDirectiveSetReorder();
924 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
925 // stubs without raw text but this current patch is for compiler generated
926 // functions and they all return some value.
927 // The calling sequence for non pic is different in that case and we need
928 // to implement %lo and %hi in order to handle the case of no return value
929 // See the corresponding method in Mips16HardFloat for details.
931 // mov the return address to S2.
932 // we have no stack space to store it and we are about to make another call.
933 // We need to make sure that the enclosing function knows to save S2
934 // This should have already been handled.
938 EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
940 EmitSwapFPIntParams(Signature->ParamSig, LE, true);
947 EmitSwapFPIntRetval(Signature->RetSig, LE);
950 // if (Signature->RetSig == NoFPRet)
951 // llvm_unreachable("should not be any stubs here with no return value");
953 EmitInstrReg(Mips::JR, Mips::S2);
955 MCSymbol *Tmp = OutContext.CreateTempSymbol();
956 OutStreamer.EmitLabel(Tmp);
957 const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
958 const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
959 const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
960 OutStreamer.EmitELFSize(Stub, T_min_E);
961 TS.emitDirectiveEnd(x);
962 OutStreamer.PopSection();
965 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
970 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
971 it = StubsNeeded.begin();
972 it != StubsNeeded.end(); ++it) {
973 const char *Symbol = it->first;
974 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
975 EmitFPCallStub(Symbol, Signature);
977 // return to the text section
978 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
981 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
986 // Align all targets of indirect branches on bundle size. Used only if target
988 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
989 // Align all blocks that are jumped to through jump table.
990 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
991 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
992 for (unsigned I = 0; I < JT.size(); ++I) {
993 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
995 for (unsigned J = 0; J < MBBs.size(); ++J)
996 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1000 // If basic block address is taken, block can be target of indirect branch.
1001 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
1003 if (MBB->hasAddressTaken())
1004 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1008 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1009 return (Opcode == Mips::LONG_BRANCH_LUi
1010 || Opcode == Mips::LONG_BRANCH_ADDiu
1011 || Opcode == Mips::LONG_BRANCH_DADDiu);
1014 // Force static initialization.
1015 extern "C" void LLVMInitializeMipsAsmPrinter() {
1016 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
1017 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
1018 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
1019 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);