1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/IR/BasicBlock.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/Mangler.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCSectionELF.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "mips-asm-printer"
56 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
57 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
60 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
61 Subtarget = &TM.getSubtarget<MipsSubtarget>();
63 // Initialize TargetLoweringObjectFile.
64 const_cast<TargetLoweringObjectFile &>(getObjFileLowering())
65 .Initialize(OutContext, TM);
67 MipsFI = MF.getInfo<MipsFunctionInfo>();
68 if (Subtarget->inMips16Mode())
71 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
72 it = MipsFI->StubsNeeded.begin();
73 it != MipsFI->StubsNeeded.end(); ++it) {
74 const char *Symbol = it->first;
75 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
76 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
77 StubsNeeded[Symbol] = Signature;
79 MCP = MF.getConstantPool();
81 // In NaCl, all indirect jump targets must be aligned to bundle size.
82 if (Subtarget->isTargetNaCl())
83 NaClAlignIndirectJumpTargets(MF);
85 AsmPrinter::runOnMachineFunction(MF);
89 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
90 MCOp = MCInstLowering.LowerOperand(MO);
91 return MCOp.isValid();
94 #include "MipsGenMCPseudoLowering.inc"
96 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
97 // JALR, or JALR64 as appropriate for the target
98 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
99 const MachineInstr *MI) {
100 bool HasLinkReg = false;
103 if (Subtarget->hasMips64r6()) {
104 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
105 TmpInst0.setOpcode(Mips::JALR64);
107 } else if (Subtarget->hasMips32r6()) {
108 // MIPS32r6 should use (JALR ZERO, $rs)
109 TmpInst0.setOpcode(Mips::JALR);
111 } else if (Subtarget->inMicroMipsMode())
112 // microMIPS should use (JR_MM $rs)
113 TmpInst0.setOpcode(Mips::JR_MM);
115 // Everything else should use (JR $rs)
116 TmpInst0.setOpcode(Mips::JR);
122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
123 TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
126 lowerOperand(MI->getOperand(0), MCOp);
127 TmpInst0.addOperand(MCOp);
129 EmitToStreamer(OutStreamer, TmpInst0);
132 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
133 MipsTargetStreamer &TS = getTargetStreamer();
134 TS.setCanHaveModuleDir(false);
136 if (MI->isDebugValue()) {
137 SmallString<128> Str;
138 raw_svector_ostream OS(Str);
140 PrintDebugValueComment(MI, OS);
144 // If we just ended a constant pool, mark it as such.
145 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
146 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
147 InConstantPool = false;
149 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
150 // CONSTPOOL_ENTRY - This instruction represents a floating
151 //constant pool in the function. The first operand is the ID#
152 // for this instruction, the second is the index into the
153 // MachineConstantPool that this is, the third is the size in
154 // bytes of this constant pool entry.
155 // The required alignment is specified on the basic block holding this MI.
157 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
158 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
160 // If this is the first entry of the pool, mark it.
161 if (!InConstantPool) {
162 OutStreamer.EmitDataRegion(MCDR_DataRegion);
163 InConstantPool = true;
166 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
168 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
169 if (MCPE.isMachineConstantPoolEntry())
170 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
172 EmitGlobalConstant(MCPE.Val.ConstVal);
177 MachineBasicBlock::const_instr_iterator I = MI;
178 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
181 // Do any auto-generated pseudo lowerings.
182 if (emitPseudoExpansionLowering(OutStreamer, &*I))
185 if (I->getOpcode() == Mips::PseudoReturn ||
186 I->getOpcode() == Mips::PseudoReturn64 ||
187 I->getOpcode() == Mips::PseudoIndirectBranch ||
188 I->getOpcode() == Mips::PseudoIndirectBranch64) {
189 emitPseudoIndirectBranch(OutStreamer, &*I);
193 // The inMips16Mode() test is not permanent.
194 // Some instructions are marked as pseudo right now which
195 // would make the test fail for the wrong reason but
196 // that will be fixed soon. We need this here because we are
197 // removing another test for this situation downstream in the
200 if (I->isPseudo() && !Subtarget->inMips16Mode()
201 && !isLongBranchPseudo(I->getOpcode()))
202 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
205 MCInstLowering.Lower(I, TmpInst0);
206 EmitToStreamer(OutStreamer, TmpInst0);
207 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
210 //===----------------------------------------------------------------------===//
212 // Mips Asm Directives
214 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
215 // Describe the stack frame.
217 // -- Mask directives "(f)mask bitmask, offset"
218 // Tells the assembler which registers are saved and where.
219 // bitmask - contain a little endian bitset indicating which registers are
220 // saved on function prologue (e.g. with a 0x80000000 mask, the
221 // assembler knows the register 31 (RA) is saved at prologue.
222 // offset - the position before stack pointer subtraction indicating where
223 // the first saved register on prologue is located. (e.g. with a
225 // Consider the following function prologue:
228 // .mask 0xc0000000,-8
229 // addiu $sp, $sp, -48
233 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
234 // 30 (FP) are saved at prologue. As the save order on prologue is from
235 // left to right, RA is saved first. A -8 offset means that after the
236 // stack pointer subtration, the first register in the mask (RA) will be
237 // saved at address 48-8=40.
239 //===----------------------------------------------------------------------===//
241 //===----------------------------------------------------------------------===//
243 //===----------------------------------------------------------------------===//
245 // Create a bitmask with all callee saved registers for CPU or Floating Point
246 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
247 void MipsAsmPrinter::printSavedRegsBitmask() {
248 // CPU and FPU Saved Registers Bitmasks
249 unsigned CPUBitmask = 0, FPUBitmask = 0;
250 int CPUTopSavedRegOff, FPUTopSavedRegOff;
252 // Set the CPU and FPU Bitmasks
253 const MachineFrameInfo *MFI = MF->getFrameInfo();
254 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
255 // size of stack area to which FP callee-saved regs are saved.
256 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
257 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
258 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
259 bool HasAFGR64Reg = false;
260 unsigned CSFPRegsSize = 0;
261 unsigned i, e = CSI.size();
264 for (i = 0; i != e; ++i) {
265 unsigned Reg = CSI[i].getReg();
266 if (Mips::GPR32RegClass.contains(Reg))
269 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
270 if (Mips::AFGR64RegClass.contains(Reg)) {
271 FPUBitmask |= (3 << RegNum);
272 CSFPRegsSize += AFGR64RegSize;
277 FPUBitmask |= (1 << RegNum);
278 CSFPRegsSize += FGR32RegSize;
282 for (; i != e; ++i) {
283 unsigned Reg = CSI[i].getReg();
284 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
285 CPUBitmask |= (1 << RegNum);
288 // FP Regs are saved right below where the virtual frame pointer points to.
289 FPUTopSavedRegOff = FPUBitmask ?
290 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
292 // CPU Regs are saved below FP Regs.
293 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
295 MipsTargetStreamer &TS = getTargetStreamer();
297 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
300 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
303 //===----------------------------------------------------------------------===//
304 // Frame and Set directives
305 //===----------------------------------------------------------------------===//
308 void MipsAsmPrinter::emitFrameDirective() {
309 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
311 unsigned stackReg = RI.getFrameRegister(*MF);
312 unsigned returnReg = RI.getRARegister();
313 unsigned stackSize = MF->getFrameInfo()->getStackSize();
315 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
318 /// Emit Set directives.
319 const char *MipsAsmPrinter::getCurrentABIString() const {
320 switch (Subtarget->getTargetABI()) {
321 case MipsSubtarget::O32: return "abi32";
322 case MipsSubtarget::N32: return "abiN32";
323 case MipsSubtarget::N64: return "abi64";
324 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
325 default: llvm_unreachable("Unknown Mips ABI");
329 void MipsAsmPrinter::EmitFunctionEntryLabel() {
330 MipsTargetStreamer &TS = getTargetStreamer();
332 // NaCl sandboxing requires that indirect call instructions are masked.
333 // This means that function entry points should be bundle-aligned.
334 if (Subtarget->isTargetNaCl())
335 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
337 if (Subtarget->inMicroMipsMode())
338 TS.emitDirectiveSetMicroMips();
340 TS.emitDirectiveSetNoMicroMips();
342 if (Subtarget->inMips16Mode())
343 TS.emitDirectiveSetMips16();
345 TS.emitDirectiveSetNoMips16();
347 TS.emitDirectiveEnt(*CurrentFnSym);
348 OutStreamer.EmitLabel(CurrentFnSym);
351 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
352 /// the first basic block in the function.
353 void MipsAsmPrinter::EmitFunctionBodyStart() {
354 MipsTargetStreamer &TS = getTargetStreamer();
356 MCInstLowering.Initialize(&MF->getContext());
358 bool IsNakedFunction =
360 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
362 if (!IsNakedFunction)
363 emitFrameDirective();
365 if (!IsNakedFunction)
366 printSavedRegsBitmask();
368 if (!Subtarget->inMips16Mode()) {
369 TS.emitDirectiveSetNoReorder();
370 TS.emitDirectiveSetNoMacro();
371 TS.emitDirectiveSetNoAt();
375 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
376 /// the last basic block in the function.
377 void MipsAsmPrinter::EmitFunctionBodyEnd() {
378 MipsTargetStreamer &TS = getTargetStreamer();
380 // There are instruction for this macros, but they must
381 // always be at the function end, and we can't emit and
382 // break with BB logic.
383 if (!Subtarget->inMips16Mode()) {
384 TS.emitDirectiveSetAt();
385 TS.emitDirectiveSetMacro();
386 TS.emitDirectiveSetReorder();
388 TS.emitDirectiveEnd(CurrentFnSym->getName());
389 // Make sure to terminate any constant pools that were at the end
393 InConstantPool = false;
394 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
397 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
398 /// exactly one predecessor and the control transfer mechanism between
399 /// the predecessor and this block is a fall-through.
400 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
402 // The predecessor has to be immediately before this block.
403 const MachineBasicBlock *Pred = *MBB->pred_begin();
405 // If the predecessor is a switch statement, assume a jump table
406 // implementation, so it is not a fall through.
407 if (const BasicBlock *bb = Pred->getBasicBlock())
408 if (isa<SwitchInst>(bb->getTerminator()))
411 // If this is a landing pad, it isn't a fall through. If it has no preds,
412 // then nothing falls through to it.
413 if (MBB->isLandingPad() || MBB->pred_empty())
416 // If there isn't exactly one predecessor, it can't be a fall through.
417 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
420 if (PI2 != MBB->pred_end())
423 // The predecessor has to be immediately before this block.
424 if (!Pred->isLayoutSuccessor(MBB))
427 // If the block is completely empty, then it definitely does fall through.
431 // Otherwise, check the last instruction.
432 // Check if the last terminator is an unconditional branch.
433 MachineBasicBlock::const_iterator I = Pred->end();
434 while (I != Pred->begin() && !(--I)->isTerminator()) ;
436 return !I->isBarrier();
439 // Print out an operand for an inline asm expression.
440 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
441 unsigned AsmVariant,const char *ExtraCode,
443 // Does this asm operand have a single letter operand modifier?
444 if (ExtraCode && ExtraCode[0]) {
445 if (ExtraCode[1] != 0) return true; // Unknown modifier.
447 const MachineOperand &MO = MI->getOperand(OpNum);
448 switch (ExtraCode[0]) {
450 // See if this is a generic print operand
451 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
452 case 'X': // hex const int
453 if ((MO.getType()) != MachineOperand::MO_Immediate)
455 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
457 case 'x': // hex const int (low 16 bits)
458 if ((MO.getType()) != MachineOperand::MO_Immediate)
460 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
462 case 'd': // decimal const int
463 if ((MO.getType()) != MachineOperand::MO_Immediate)
467 case 'm': // decimal const int minus 1
468 if ((MO.getType()) != MachineOperand::MO_Immediate)
470 O << MO.getImm() - 1;
473 // $0 if zero, regular printing otherwise
474 if (MO.getType() != MachineOperand::MO_Immediate)
476 int64_t Val = MO.getImm();
483 case 'D': // Second part of a double word register operand
484 case 'L': // Low order register of a double word register operand
485 case 'M': // High order register of a double word register operand
489 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
490 if (!FlagsOP.isImm())
492 unsigned Flags = FlagsOP.getImm();
493 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
494 // Number of registers represented by this operand. We are looking
495 // for 2 for 32 bit mode and 1 for 64 bit mode.
497 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
498 unsigned Reg = MO.getReg();
499 O << '$' << MipsInstPrinter::getRegisterName(Reg);
505 unsigned RegOp = OpNum;
506 if (!Subtarget->isGP64bit()){
507 // Endianess reverses which register holds the high or low value
509 switch(ExtraCode[0]) {
511 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
514 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
516 case 'D': // Always the second part
519 if (RegOp >= MI->getNumOperands())
521 const MachineOperand &MO = MI->getOperand(RegOp);
524 unsigned Reg = MO.getReg();
525 O << '$' << MipsInstPrinter::getRegisterName(Reg);
530 // Print MSA registers for the 'f' constraint
531 // In LLVM, the 'w' modifier doesn't need to do anything.
532 // We can just call printOperand as normal.
537 printOperand(MI, OpNum, O);
541 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
542 unsigned OpNum, unsigned AsmVariant,
543 const char *ExtraCode,
546 // Currently we are expecting either no ExtraCode or 'D'
548 if (ExtraCode[0] == 'D')
551 return true; // Unknown modifier.
554 const MachineOperand &MO = MI->getOperand(OpNum);
555 assert(MO.isReg() && "unexpected inline asm memory operand");
556 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
561 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
563 const DataLayout *DL = TM.getDataLayout();
564 const MachineOperand &MO = MI->getOperand(opNum);
567 if (MO.getTargetFlags())
570 switch(MO.getTargetFlags()) {
571 case MipsII::MO_GPREL: O << "%gp_rel("; break;
572 case MipsII::MO_GOT_CALL: O << "%call16("; break;
573 case MipsII::MO_GOT: O << "%got("; break;
574 case MipsII::MO_ABS_HI: O << "%hi("; break;
575 case MipsII::MO_ABS_LO: O << "%lo("; break;
576 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
577 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
578 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
579 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
580 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
581 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
582 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
583 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
584 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
587 switch (MO.getType()) {
588 case MachineOperand::MO_Register:
590 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
593 case MachineOperand::MO_Immediate:
597 case MachineOperand::MO_MachineBasicBlock:
598 O << *MO.getMBB()->getSymbol();
601 case MachineOperand::MO_GlobalAddress:
602 O << *getSymbol(MO.getGlobal());
605 case MachineOperand::MO_BlockAddress: {
606 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
611 case MachineOperand::MO_ConstantPoolIndex:
612 O << DL->getPrivateGlobalPrefix() << "CPI"
613 << getFunctionNumber() << "_" << MO.getIndex();
615 O << "+" << MO.getOffset();
619 llvm_unreachable("<unknown operand type>");
622 if (closeP) O << ")";
625 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
627 const MachineOperand &MO = MI->getOperand(opNum);
629 O << (unsigned short int)MO.getImm();
631 printOperand(MI, opNum, O);
634 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
636 const MachineOperand &MO = MI->getOperand(opNum);
638 O << (unsigned short int)(unsigned char)MO.getImm();
640 printOperand(MI, opNum, O);
643 void MipsAsmPrinter::
644 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
645 // Load/Store memory operands -- imm($reg)
646 // If PIC target the target is loaded as the
647 // pattern lw $25,%call16($28)
648 printOperand(MI, opNum+1, O);
650 printOperand(MI, opNum, O);
654 void MipsAsmPrinter::
655 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
656 // when using stack locations for not load/store instructions
657 // print the same way as all normal 3 operand instructions.
658 printOperand(MI, opNum, O);
660 printOperand(MI, opNum+1, O);
664 void MipsAsmPrinter::
665 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
666 const char *Modifier) {
667 const MachineOperand &MO = MI->getOperand(opNum);
668 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
671 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
672 // TODO: Need to add -mabicalls and -mno-abicalls flags.
673 // Currently we assume that -mabicalls is the default.
674 bool IsABICalls = true;
676 getTargetStreamer().emitDirectiveAbiCalls();
677 Reloc::Model RM = TM.getRelocationModel();
678 // FIXME: This condition should be a lot more complicated that it is here.
679 // Ideally it should test for properties of the ABI and not the ABI
681 // For the moment, I'm only correcting enough to make MIPS-IV work.
682 if (RM == Reloc::Static && !Subtarget->isABI_N64())
683 getTargetStreamer().emitDirectiveOptionPic0();
686 // Tell the assembler which ABI we are using
687 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
688 OutStreamer.SwitchSection(OutContext.getELFSection(
689 SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
691 // NaN: At the moment we only support:
692 // 1. .nan legacy (default)
694 Subtarget->isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
695 : getTargetStreamer().emitDirectiveNaNLegacy();
697 // TODO: handle O64 ABI
699 if (Subtarget->isABI_EABI()) {
700 if (Subtarget->isGP32bit())
701 OutStreamer.SwitchSection(
702 OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
703 SectionKind::getDataRel()));
705 OutStreamer.SwitchSection(
706 OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
707 SectionKind::getDataRel()));
710 getTargetStreamer().updateABIInfo(*Subtarget);
711 getTargetStreamer().emitDirectiveModuleFP();
713 if (Subtarget->isABI_O32())
714 getTargetStreamer().emitDirectiveModuleOddSPReg(Subtarget->useOddSPReg(),
715 Subtarget->isABI_O32());
718 void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
720 I.setOpcode(Mips::JAL);
722 MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
723 OutStreamer.EmitInstruction(I, getSubtargetInfo());
726 void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
729 I.addOperand(MCOperand::CreateReg(Reg));
730 OutStreamer.EmitInstruction(I, getSubtargetInfo());
733 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
737 // Because of the current td files for Mips32, the operands for MTC1
738 // appear backwards from their normal assembly order. It's not a trivial
739 // change to fix this in the td file so we adjust for it here.
741 if (Opcode == Mips::MTC1) {
742 unsigned Temp = Reg1;
747 I.addOperand(MCOperand::CreateReg(Reg1));
748 I.addOperand(MCOperand::CreateReg(Reg2));
749 OutStreamer.EmitInstruction(I, getSubtargetInfo());
752 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
753 unsigned Reg2, unsigned Reg3) {
756 I.addOperand(MCOperand::CreateReg(Reg1));
757 I.addOperand(MCOperand::CreateReg(Reg2));
758 I.addOperand(MCOperand::CreateReg(Reg3));
759 OutStreamer.EmitInstruction(I, getSubtargetInfo());
762 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
763 unsigned Reg2, unsigned FPReg1,
764 unsigned FPReg2, bool LE) {
766 unsigned temp = Reg1;
770 EmitInstrRegReg(MovOpc, Reg1, FPReg1);
771 EmitInstrRegReg(MovOpc, Reg2, FPReg2);
774 void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
775 bool LE, bool ToFP) {
776 using namespace Mips16HardFloatInfo;
777 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
780 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
783 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
786 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
787 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
790 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
793 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
794 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
797 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
798 EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
806 MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
808 using namespace Mips16HardFloatInfo;
809 unsigned MovOpc = Mips::MFC1;
812 EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
815 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
818 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
821 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
822 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
829 void MipsAsmPrinter::EmitFPCallStub(
830 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
831 MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
832 using namespace Mips16HardFloatInfo;
833 bool LE = Subtarget->isLittle();
837 OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
840 // make the comment field identifying the return and parameter
841 // types of the floating point stub
842 // # Stub function to call rettype xxxx (params)
844 switch (Signature->RetSig) {
855 RetType = "double complex";
862 switch (Signature->ParamSig) {
867 Parms = "float, float";
870 Parms = "float, double";
876 Parms = "double, double";
879 Parms = "double, float";
885 OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
886 Twine(Symbol) + " (" + Twine(Parms) + ")");
888 // probably not necessary but we save and restore the current section state
890 OutStreamer.PushSection();
892 // .section mips16.call.fpxxxx,"ax",@progbits
894 const MCSectionELF *M = OutContext.getELFSection(
895 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
896 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
897 OutStreamer.SwitchSection(M, nullptr);
901 OutStreamer.EmitValueToAlignment(4);
902 MipsTargetStreamer &TS = getTargetStreamer();
907 TS.emitDirectiveSetNoMips16();
908 TS.emitDirectiveSetNoMicroMips();
910 // .ent __call_stub_fp_xxxx
911 // .type __call_stub_fp_xxxx,@function
912 // __call_stub_fp_xxxx:
914 std::string x = "__call_stub_fp_" + std::string(Symbol);
915 MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
916 TS.emitDirectiveEnt(*Stub);
918 OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
919 OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
920 OutStreamer.EmitLabel(Stub);
922 // we just handle non pic for now. these function will not be
923 // called otherwise. when the full stub generation is moved here
924 // we need to deal with pic.
926 if (Subtarget->getRelocationModel() == Reloc::PIC_)
927 llvm_unreachable("should not be here if we are compiling pic");
928 TS.emitDirectiveSetReorder();
930 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
931 // stubs without raw text but this current patch is for compiler generated
932 // functions and they all return some value.
933 // The calling sequence for non pic is different in that case and we need
934 // to implement %lo and %hi in order to handle the case of no return value
935 // See the corresponding method in Mips16HardFloat for details.
937 // mov the return address to S2.
938 // we have no stack space to store it and we are about to make another call.
939 // We need to make sure that the enclosing function knows to save S2
940 // This should have already been handled.
944 EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
946 EmitSwapFPIntParams(Signature->ParamSig, LE, true);
953 EmitSwapFPIntRetval(Signature->RetSig, LE);
956 // if (Signature->RetSig == NoFPRet)
957 // llvm_unreachable("should not be any stubs here with no return value");
959 EmitInstrReg(Mips::JR, Mips::S2);
961 MCSymbol *Tmp = OutContext.CreateTempSymbol();
962 OutStreamer.EmitLabel(Tmp);
963 const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
964 const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
965 const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
966 OutStreamer.EmitELFSize(Stub, T_min_E);
967 TS.emitDirectiveEnd(x);
968 OutStreamer.PopSection();
971 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
976 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
977 it = StubsNeeded.begin();
978 it != StubsNeeded.end(); ++it) {
979 const char *Symbol = it->first;
980 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
981 EmitFPCallStub(Symbol, Signature);
983 // return to the text section
984 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
987 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
992 // Align all targets of indirect branches on bundle size. Used only if target
994 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
995 // Align all blocks that are jumped to through jump table.
996 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
997 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
998 for (unsigned I = 0; I < JT.size(); ++I) {
999 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1001 for (unsigned J = 0; J < MBBs.size(); ++J)
1002 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1006 // If basic block address is taken, block can be target of indirect branch.
1007 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
1009 if (MBB->hasAddressTaken())
1010 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1014 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1015 return (Opcode == Mips::LONG_BRANCH_LUi
1016 || Opcode == Mips::LONG_BRANCH_ADDiu
1017 || Opcode == Mips::LONG_BRANCH_DADDiu);
1020 // Force static initialization.
1021 extern "C" void LLVMInitializeMipsAsmPrinter() {
1022 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
1023 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
1024 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
1025 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);