1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/IR/BasicBlock.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/Mangler.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCSectionELF.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "mips-asm-printer"
56 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
57 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
60 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
61 // Initialize TargetLoweringObjectFile.
62 if (Subtarget->allowMixed16_32())
63 const_cast<TargetLoweringObjectFile&>(getObjFileLowering())
64 .Initialize(OutContext, TM);
65 MipsFI = MF.getInfo<MipsFunctionInfo>();
66 if (Subtarget->inMips16Mode())
69 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
70 it = MipsFI->StubsNeeded.begin();
71 it != MipsFI->StubsNeeded.end(); ++it) {
72 const char *Symbol = it->first;
73 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
74 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
75 StubsNeeded[Symbol] = Signature;
77 MCP = MF.getConstantPool();
79 // In NaCl, all indirect jump targets must be aligned to bundle size.
80 if (Subtarget->isTargetNaCl())
81 NaClAlignIndirectJumpTargets(MF);
83 AsmPrinter::runOnMachineFunction(MF);
87 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
88 MCOp = MCInstLowering.LowerOperand(MO);
89 return MCOp.isValid();
92 #include "MipsGenMCPseudoLowering.inc"
94 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
95 if (MI->isDebugValue()) {
97 raw_svector_ostream OS(Str);
99 PrintDebugValueComment(MI, OS);
103 // If we just ended a constant pool, mark it as such.
104 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
105 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
106 InConstantPool = false;
108 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
109 // CONSTPOOL_ENTRY - This instruction represents a floating
110 //constant pool in the function. The first operand is the ID#
111 // for this instruction, the second is the index into the
112 // MachineConstantPool that this is, the third is the size in
113 // bytes of this constant pool entry.
114 // The required alignment is specified on the basic block holding this MI.
116 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
117 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
119 // If this is the first entry of the pool, mark it.
120 if (!InConstantPool) {
121 OutStreamer.EmitDataRegion(MCDR_DataRegion);
122 InConstantPool = true;
125 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
127 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
128 if (MCPE.isMachineConstantPoolEntry())
129 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
131 EmitGlobalConstant(MCPE.Val.ConstVal);
136 MachineBasicBlock::const_instr_iterator I = MI;
137 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
140 // Do any auto-generated pseudo lowerings.
141 if (emitPseudoExpansionLowering(OutStreamer, &*I))
144 // The inMips16Mode() test is not permanent.
145 // Some instructions are marked as pseudo right now which
146 // would make the test fail for the wrong reason but
147 // that will be fixed soon. We need this here because we are
148 // removing another test for this situation downstream in the
151 if (I->isPseudo() && !Subtarget->inMips16Mode())
152 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
155 MCInstLowering.Lower(I, TmpInst0);
156 EmitToStreamer(OutStreamer, TmpInst0);
157 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
160 //===----------------------------------------------------------------------===//
162 // Mips Asm Directives
164 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
165 // Describe the stack frame.
167 // -- Mask directives "(f)mask bitmask, offset"
168 // Tells the assembler which registers are saved and where.
169 // bitmask - contain a little endian bitset indicating which registers are
170 // saved on function prologue (e.g. with a 0x80000000 mask, the
171 // assembler knows the register 31 (RA) is saved at prologue.
172 // offset - the position before stack pointer subtraction indicating where
173 // the first saved register on prologue is located. (e.g. with a
175 // Consider the following function prologue:
178 // .mask 0xc0000000,-8
179 // addiu $sp, $sp, -48
183 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
184 // 30 (FP) are saved at prologue. As the save order on prologue is from
185 // left to right, RA is saved first. A -8 offset means that after the
186 // stack pointer subtration, the first register in the mask (RA) will be
187 // saved at address 48-8=40.
189 //===----------------------------------------------------------------------===//
191 //===----------------------------------------------------------------------===//
193 //===----------------------------------------------------------------------===//
195 // Create a bitmask with all callee saved registers for CPU or Floating Point
196 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
197 void MipsAsmPrinter::printSavedRegsBitmask() {
198 // CPU and FPU Saved Registers Bitmasks
199 unsigned CPUBitmask = 0, FPUBitmask = 0;
200 int CPUTopSavedRegOff, FPUTopSavedRegOff;
202 // Set the CPU and FPU Bitmasks
203 const MachineFrameInfo *MFI = MF->getFrameInfo();
204 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
205 // size of stack area to which FP callee-saved regs are saved.
206 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
207 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
208 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
209 bool HasAFGR64Reg = false;
210 unsigned CSFPRegsSize = 0;
211 unsigned i, e = CSI.size();
214 for (i = 0; i != e; ++i) {
215 unsigned Reg = CSI[i].getReg();
216 if (Mips::GPR32RegClass.contains(Reg))
219 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
220 if (Mips::AFGR64RegClass.contains(Reg)) {
221 FPUBitmask |= (3 << RegNum);
222 CSFPRegsSize += AFGR64RegSize;
227 FPUBitmask |= (1 << RegNum);
228 CSFPRegsSize += FGR32RegSize;
232 for (; i != e; ++i) {
233 unsigned Reg = CSI[i].getReg();
234 unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg);
235 CPUBitmask |= (1 << RegNum);
238 // FP Regs are saved right below where the virtual frame pointer points to.
239 FPUTopSavedRegOff = FPUBitmask ?
240 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
242 // CPU Regs are saved below FP Regs.
243 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
245 MipsTargetStreamer &TS = getTargetStreamer();
247 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
250 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
253 //===----------------------------------------------------------------------===//
254 // Frame and Set directives
255 //===----------------------------------------------------------------------===//
258 void MipsAsmPrinter::emitFrameDirective() {
259 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
261 unsigned stackReg = RI.getFrameRegister(*MF);
262 unsigned returnReg = RI.getRARegister();
263 unsigned stackSize = MF->getFrameInfo()->getStackSize();
265 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
268 /// Emit Set directives.
269 const char *MipsAsmPrinter::getCurrentABIString() const {
270 switch (Subtarget->getTargetABI()) {
271 case MipsSubtarget::O32: return "abi32";
272 case MipsSubtarget::N32: return "abiN32";
273 case MipsSubtarget::N64: return "abi64";
274 case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64
275 default: llvm_unreachable("Unknown Mips ABI");
279 void MipsAsmPrinter::EmitFunctionEntryLabel() {
280 MipsTargetStreamer &TS = getTargetStreamer();
282 // NaCl sandboxing requires that indirect call instructions are masked.
283 // This means that function entry points should be bundle-aligned.
284 if (Subtarget->isTargetNaCl())
285 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
287 if (Subtarget->inMicroMipsMode())
288 TS.emitDirectiveSetMicroMips();
290 TS.emitDirectiveSetNoMicroMips();
292 if (Subtarget->inMips16Mode())
293 TS.emitDirectiveSetMips16();
295 TS.emitDirectiveSetNoMips16();
297 TS.emitDirectiveEnt(*CurrentFnSym);
298 OutStreamer.EmitLabel(CurrentFnSym);
301 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
302 /// the first basic block in the function.
303 void MipsAsmPrinter::EmitFunctionBodyStart() {
304 MipsTargetStreamer &TS = getTargetStreamer();
306 MCInstLowering.Initialize(&MF->getContext());
308 bool IsNakedFunction =
310 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
312 if (!IsNakedFunction)
313 emitFrameDirective();
315 if (!IsNakedFunction)
316 printSavedRegsBitmask();
318 if (!Subtarget->inMips16Mode()) {
319 TS.emitDirectiveSetNoReorder();
320 TS.emitDirectiveSetNoMacro();
321 TS.emitDirectiveSetNoAt();
325 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
326 /// the last basic block in the function.
327 void MipsAsmPrinter::EmitFunctionBodyEnd() {
328 MipsTargetStreamer &TS = getTargetStreamer();
330 // There are instruction for this macros, but they must
331 // always be at the function end, and we can't emit and
332 // break with BB logic.
333 if (!Subtarget->inMips16Mode()) {
334 TS.emitDirectiveSetAt();
335 TS.emitDirectiveSetMacro();
336 TS.emitDirectiveSetReorder();
338 TS.emitDirectiveEnd(CurrentFnSym->getName());
339 // Make sure to terminate any constant pools that were at the end
343 InConstantPool = false;
344 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
347 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
348 /// exactly one predecessor and the control transfer mechanism between
349 /// the predecessor and this block is a fall-through.
350 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
352 // The predecessor has to be immediately before this block.
353 const MachineBasicBlock *Pred = *MBB->pred_begin();
355 // If the predecessor is a switch statement, assume a jump table
356 // implementation, so it is not a fall through.
357 if (const BasicBlock *bb = Pred->getBasicBlock())
358 if (isa<SwitchInst>(bb->getTerminator()))
361 // If this is a landing pad, it isn't a fall through. If it has no preds,
362 // then nothing falls through to it.
363 if (MBB->isLandingPad() || MBB->pred_empty())
366 // If there isn't exactly one predecessor, it can't be a fall through.
367 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
370 if (PI2 != MBB->pred_end())
373 // The predecessor has to be immediately before this block.
374 if (!Pred->isLayoutSuccessor(MBB))
377 // If the block is completely empty, then it definitely does fall through.
381 // Otherwise, check the last instruction.
382 // Check if the last terminator is an unconditional branch.
383 MachineBasicBlock::const_iterator I = Pred->end();
384 while (I != Pred->begin() && !(--I)->isTerminator()) ;
386 return !I->isBarrier();
389 // Print out an operand for an inline asm expression.
390 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
391 unsigned AsmVariant,const char *ExtraCode,
393 // Does this asm operand have a single letter operand modifier?
394 if (ExtraCode && ExtraCode[0]) {
395 if (ExtraCode[1] != 0) return true; // Unknown modifier.
397 const MachineOperand &MO = MI->getOperand(OpNum);
398 switch (ExtraCode[0]) {
400 // See if this is a generic print operand
401 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
402 case 'X': // hex const int
403 if ((MO.getType()) != MachineOperand::MO_Immediate)
405 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
407 case 'x': // hex const int (low 16 bits)
408 if ((MO.getType()) != MachineOperand::MO_Immediate)
410 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
412 case 'd': // decimal const int
413 if ((MO.getType()) != MachineOperand::MO_Immediate)
417 case 'm': // decimal const int minus 1
418 if ((MO.getType()) != MachineOperand::MO_Immediate)
420 O << MO.getImm() - 1;
423 // $0 if zero, regular printing otherwise
424 if (MO.getType() != MachineOperand::MO_Immediate)
426 int64_t Val = MO.getImm();
433 case 'D': // Second part of a double word register operand
434 case 'L': // Low order register of a double word register operand
435 case 'M': // High order register of a double word register operand
439 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
440 if (!FlagsOP.isImm())
442 unsigned Flags = FlagsOP.getImm();
443 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
444 // Number of registers represented by this operand. We are looking
445 // for 2 for 32 bit mode and 1 for 64 bit mode.
447 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
448 unsigned Reg = MO.getReg();
449 O << '$' << MipsInstPrinter::getRegisterName(Reg);
455 unsigned RegOp = OpNum;
456 if (!Subtarget->isGP64bit()){
457 // Endianess reverses which register holds the high or low value
459 switch(ExtraCode[0]) {
461 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
464 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
466 case 'D': // Always the second part
469 if (RegOp >= MI->getNumOperands())
471 const MachineOperand &MO = MI->getOperand(RegOp);
474 unsigned Reg = MO.getReg();
475 O << '$' << MipsInstPrinter::getRegisterName(Reg);
480 // Print MSA registers for the 'f' constraint
481 // In LLVM, the 'w' modifier doesn't need to do anything.
482 // We can just call printOperand as normal.
487 printOperand(MI, OpNum, O);
491 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
492 unsigned OpNum, unsigned AsmVariant,
493 const char *ExtraCode,
496 // Currently we are expecting either no ExtraCode or 'D'
498 if (ExtraCode[0] == 'D')
501 return true; // Unknown modifier.
504 const MachineOperand &MO = MI->getOperand(OpNum);
505 assert(MO.isReg() && "unexpected inline asm memory operand");
506 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
511 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
513 const DataLayout *DL = TM.getDataLayout();
514 const MachineOperand &MO = MI->getOperand(opNum);
517 if (MO.getTargetFlags())
520 switch(MO.getTargetFlags()) {
521 case MipsII::MO_GPREL: O << "%gp_rel("; break;
522 case MipsII::MO_GOT_CALL: O << "%call16("; break;
523 case MipsII::MO_GOT: O << "%got("; break;
524 case MipsII::MO_ABS_HI: O << "%hi("; break;
525 case MipsII::MO_ABS_LO: O << "%lo("; break;
526 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
527 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
528 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
529 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
530 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
531 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
532 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
533 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
534 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
537 switch (MO.getType()) {
538 case MachineOperand::MO_Register:
540 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
543 case MachineOperand::MO_Immediate:
547 case MachineOperand::MO_MachineBasicBlock:
548 O << *MO.getMBB()->getSymbol();
551 case MachineOperand::MO_GlobalAddress:
552 O << *getSymbol(MO.getGlobal());
555 case MachineOperand::MO_BlockAddress: {
556 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
561 case MachineOperand::MO_ConstantPoolIndex:
562 O << DL->getPrivateGlobalPrefix() << "CPI"
563 << getFunctionNumber() << "_" << MO.getIndex();
565 O << "+" << MO.getOffset();
569 llvm_unreachable("<unknown operand type>");
572 if (closeP) O << ")";
575 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
577 const MachineOperand &MO = MI->getOperand(opNum);
579 O << (unsigned short int)MO.getImm();
581 printOperand(MI, opNum, O);
584 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
586 const MachineOperand &MO = MI->getOperand(opNum);
588 O << (unsigned short int)(unsigned char)MO.getImm();
590 printOperand(MI, opNum, O);
593 void MipsAsmPrinter::
594 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
595 // Load/Store memory operands -- imm($reg)
596 // If PIC target the target is loaded as the
597 // pattern lw $25,%call16($28)
598 printOperand(MI, opNum+1, O);
600 printOperand(MI, opNum, O);
604 void MipsAsmPrinter::
605 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
606 // when using stack locations for not load/store instructions
607 // print the same way as all normal 3 operand instructions.
608 printOperand(MI, opNum, O);
610 printOperand(MI, opNum+1, O);
614 void MipsAsmPrinter::
615 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
616 const char *Modifier) {
617 const MachineOperand &MO = MI->getOperand(opNum);
618 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
621 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
622 // TODO: Need to add -mabicalls and -mno-abicalls flags.
623 // Currently we assume that -mabicalls is the default.
624 bool IsABICalls = true;
626 getTargetStreamer().emitDirectiveAbiCalls();
627 Reloc::Model RM = Subtarget->getRelocationModel();
628 // FIXME: This condition should be a lot more complicated that it is here.
629 // Ideally it should test for properties of the ABI and not the ABI
631 // For the moment, I'm only correcting enough to make MIPS-IV work.
632 if (RM == Reloc::Static && !Subtarget->isABI_N64())
633 getTargetStreamer().emitDirectiveOptionPic0();
636 // Tell the assembler which ABI we are using
637 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
638 OutStreamer.SwitchSection(OutContext.getELFSection(
639 SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
641 // NaN: At the moment we only support:
642 // 1. .nan legacy (default)
644 Subtarget->isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
645 : getTargetStreamer().emitDirectiveNaNLegacy();
647 // TODO: handle O64 ABI
649 if (Subtarget->isABI_EABI()) {
650 if (Subtarget->isGP32bit())
651 OutStreamer.SwitchSection(
652 OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
653 SectionKind::getDataRel()));
655 OutStreamer.SwitchSection(
656 OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
657 SectionKind::getDataRel()));
661 void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
663 I.setOpcode(Mips::JAL);
665 MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
666 OutStreamer.EmitInstruction(I, getSubtargetInfo());
669 void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
672 I.addOperand(MCOperand::CreateReg(Reg));
673 OutStreamer.EmitInstruction(I, getSubtargetInfo());
676 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
680 // Because of the current td files for Mips32, the operands for MTC1
681 // appear backwards from their normal assembly order. It's not a trivial
682 // change to fix this in the td file so we adjust for it here.
684 if (Opcode == Mips::MTC1) {
685 unsigned Temp = Reg1;
690 I.addOperand(MCOperand::CreateReg(Reg1));
691 I.addOperand(MCOperand::CreateReg(Reg2));
692 OutStreamer.EmitInstruction(I, getSubtargetInfo());
695 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
696 unsigned Reg2, unsigned Reg3) {
699 I.addOperand(MCOperand::CreateReg(Reg1));
700 I.addOperand(MCOperand::CreateReg(Reg2));
701 I.addOperand(MCOperand::CreateReg(Reg3));
702 OutStreamer.EmitInstruction(I, getSubtargetInfo());
705 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
706 unsigned Reg2, unsigned FPReg1,
707 unsigned FPReg2, bool LE) {
709 unsigned temp = Reg1;
713 EmitInstrRegReg(MovOpc, Reg1, FPReg1);
714 EmitInstrRegReg(MovOpc, Reg2, FPReg2);
717 void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
718 bool LE, bool ToFP) {
719 using namespace Mips16HardFloatInfo;
720 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
723 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
726 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
729 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
730 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
733 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
736 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
737 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
740 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
741 EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
749 MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
751 using namespace Mips16HardFloatInfo;
752 unsigned MovOpc = Mips::MFC1;
755 EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
758 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
761 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
764 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
765 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
772 void MipsAsmPrinter::EmitFPCallStub(
773 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
774 MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
775 using namespace Mips16HardFloatInfo;
776 bool LE = Subtarget->isLittle();
780 OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
783 // make the comment field identifying the return and parameter
784 // types of the floating point stub
785 // # Stub function to call rettype xxxx (params)
787 switch (Signature->RetSig) {
798 RetType = "double complex";
805 switch (Signature->ParamSig) {
810 Parms = "float, float";
813 Parms = "float, double";
819 Parms = "double, double";
822 Parms = "double, float";
828 OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
829 Twine(Symbol) + " (" + Twine(Parms) + ")");
831 // probably not necessary but we save and restore the current section state
833 OutStreamer.PushSection();
835 // .section mips16.call.fpxxxx,"ax",@progbits
837 const MCSectionELF *M = OutContext.getELFSection(
838 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
839 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
840 OutStreamer.SwitchSection(M, nullptr);
844 OutStreamer.EmitValueToAlignment(4);
845 MipsTargetStreamer &TS = getTargetStreamer();
850 TS.emitDirectiveSetNoMips16();
851 TS.emitDirectiveSetNoMicroMips();
853 // .ent __call_stub_fp_xxxx
854 // .type __call_stub_fp_xxxx,@function
855 // __call_stub_fp_xxxx:
857 std::string x = "__call_stub_fp_" + std::string(Symbol);
858 MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
859 TS.emitDirectiveEnt(*Stub);
861 OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
862 OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
863 OutStreamer.EmitLabel(Stub);
865 // we just handle non pic for now. these function will not be
866 // called otherwise. when the full stub generation is moved here
867 // we need to deal with pic.
869 if (Subtarget->getRelocationModel() == Reloc::PIC_)
870 llvm_unreachable("should not be here if we are compiling pic");
871 TS.emitDirectiveSetReorder();
873 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
874 // stubs without raw text but this current patch is for compiler generated
875 // functions and they all return some value.
876 // The calling sequence for non pic is different in that case and we need
877 // to implement %lo and %hi in order to handle the case of no return value
878 // See the corresponding method in Mips16HardFloat for details.
880 // mov the return address to S2.
881 // we have no stack space to store it and we are about to make another call.
882 // We need to make sure that the enclosing function knows to save S2
883 // This should have already been handled.
887 EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
889 EmitSwapFPIntParams(Signature->ParamSig, LE, true);
896 EmitSwapFPIntRetval(Signature->RetSig, LE);
899 // if (Signature->RetSig == NoFPRet)
900 // llvm_unreachable("should not be any stubs here with no return value");
902 EmitInstrReg(Mips::JR, Mips::S2);
904 MCSymbol *Tmp = OutContext.CreateTempSymbol();
905 OutStreamer.EmitLabel(Tmp);
906 const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
907 const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
908 const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
909 OutStreamer.EmitELFSize(Stub, T_min_E);
910 TS.emitDirectiveEnd(x);
911 OutStreamer.PopSection();
914 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
919 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
920 it = StubsNeeded.begin();
921 it != StubsNeeded.end(); ++it) {
922 const char *Symbol = it->first;
923 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
924 EmitFPCallStub(Symbol, Signature);
926 // return to the text section
927 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
930 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
935 // Align all targets of indirect branches on bundle size. Used only if target
937 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
938 // Align all blocks that are jumped to through jump table.
939 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
940 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
941 for (unsigned I = 0; I < JT.size(); ++I) {
942 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
944 for (unsigned J = 0; J < MBBs.size(); ++J)
945 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
949 // If basic block address is taken, block can be target of indirect branch.
950 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
952 if (MBB->hasAddressTaken())
953 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
957 // Force static initialization.
958 extern "C" void LLVMInitializeMipsAsmPrinter() {
959 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
960 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
961 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
962 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);