1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetStreamer.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineMemOperand.h"
32 #include "llvm/IR/BasicBlock.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/Mangler.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCSection.h"
43 #include "llvm/MC/MCSectionELF.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Support/raw_ostream.h"
48 #include "llvm/Target/TargetLoweringObjectFile.h"
49 #include "llvm/Target/TargetOptions.h"
54 #define DEBUG_TYPE "mips-asm-printer"
56 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
57 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
60 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
61 Subtarget = &TM.getSubtarget<MipsSubtarget>();
63 // Initialize TargetLoweringObjectFile.
64 const_cast<TargetLoweringObjectFile &>(getObjFileLowering())
65 .Initialize(OutContext, TM);
67 MipsFI = MF.getInfo<MipsFunctionInfo>();
68 if (Subtarget->inMips16Mode())
71 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
72 it = MipsFI->StubsNeeded.begin();
73 it != MipsFI->StubsNeeded.end(); ++it) {
74 const char *Symbol = it->first;
75 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
76 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
77 StubsNeeded[Symbol] = Signature;
79 MCP = MF.getConstantPool();
81 // In NaCl, all indirect jump targets must be aligned to bundle size.
82 if (Subtarget->isTargetNaCl())
83 NaClAlignIndirectJumpTargets(MF);
85 AsmPrinter::runOnMachineFunction(MF);
89 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
90 MCOp = MCInstLowering.LowerOperand(MO);
91 return MCOp.isValid();
94 #include "MipsGenMCPseudoLowering.inc"
96 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
97 // JALR, or JALR64 as appropriate for the target
98 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
99 const MachineInstr *MI) {
100 bool HasLinkReg = false;
103 if (Subtarget->hasMips64r6()) {
104 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
105 TmpInst0.setOpcode(Mips::JALR64);
107 } else if (Subtarget->hasMips32r6()) {
108 // MIPS32r6 should use (JALR ZERO, $rs)
109 TmpInst0.setOpcode(Mips::JALR);
111 } else if (Subtarget->inMicroMipsMode())
112 // microMIPS should use (JR_MM $rs)
113 TmpInst0.setOpcode(Mips::JR_MM);
115 // Everything else should use (JR $rs)
116 TmpInst0.setOpcode(Mips::JR);
122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
123 TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
126 lowerOperand(MI->getOperand(0), MCOp);
127 TmpInst0.addOperand(MCOp);
129 EmitToStreamer(OutStreamer, TmpInst0);
132 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
133 MipsTargetStreamer &TS = getTargetStreamer();
134 TS.forbidModuleDirective();
136 if (MI->isDebugValue()) {
137 SmallString<128> Str;
138 raw_svector_ostream OS(Str);
140 PrintDebugValueComment(MI, OS);
144 // If we just ended a constant pool, mark it as such.
145 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
146 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
147 InConstantPool = false;
149 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
150 // CONSTPOOL_ENTRY - This instruction represents a floating
151 //constant pool in the function. The first operand is the ID#
152 // for this instruction, the second is the index into the
153 // MachineConstantPool that this is, the third is the size in
154 // bytes of this constant pool entry.
155 // The required alignment is specified on the basic block holding this MI.
157 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
158 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
160 // If this is the first entry of the pool, mark it.
161 if (!InConstantPool) {
162 OutStreamer.EmitDataRegion(MCDR_DataRegion);
163 InConstantPool = true;
166 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
168 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
169 if (MCPE.isMachineConstantPoolEntry())
170 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
172 EmitGlobalConstant(MCPE.Val.ConstVal);
177 MachineBasicBlock::const_instr_iterator I = MI;
178 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
181 // Do any auto-generated pseudo lowerings.
182 if (emitPseudoExpansionLowering(OutStreamer, &*I))
185 if (I->getOpcode() == Mips::PseudoReturn ||
186 I->getOpcode() == Mips::PseudoReturn64 ||
187 I->getOpcode() == Mips::PseudoIndirectBranch ||
188 I->getOpcode() == Mips::PseudoIndirectBranch64) {
189 emitPseudoIndirectBranch(OutStreamer, &*I);
193 // The inMips16Mode() test is not permanent.
194 // Some instructions are marked as pseudo right now which
195 // would make the test fail for the wrong reason but
196 // that will be fixed soon. We need this here because we are
197 // removing another test for this situation downstream in the
200 if (I->isPseudo() && !Subtarget->inMips16Mode()
201 && !isLongBranchPseudo(I->getOpcode()))
202 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
205 MCInstLowering.Lower(I, TmpInst0);
206 EmitToStreamer(OutStreamer, TmpInst0);
207 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
210 //===----------------------------------------------------------------------===//
212 // Mips Asm Directives
214 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
215 // Describe the stack frame.
217 // -- Mask directives "(f)mask bitmask, offset"
218 // Tells the assembler which registers are saved and where.
219 // bitmask - contain a little endian bitset indicating which registers are
220 // saved on function prologue (e.g. with a 0x80000000 mask, the
221 // assembler knows the register 31 (RA) is saved at prologue.
222 // offset - the position before stack pointer subtraction indicating where
223 // the first saved register on prologue is located. (e.g. with a
225 // Consider the following function prologue:
228 // .mask 0xc0000000,-8
229 // addiu $sp, $sp, -48
233 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
234 // 30 (FP) are saved at prologue. As the save order on prologue is from
235 // left to right, RA is saved first. A -8 offset means that after the
236 // stack pointer subtration, the first register in the mask (RA) will be
237 // saved at address 48-8=40.
239 //===----------------------------------------------------------------------===//
241 //===----------------------------------------------------------------------===//
243 //===----------------------------------------------------------------------===//
245 // Create a bitmask with all callee saved registers for CPU or Floating Point
246 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
247 void MipsAsmPrinter::printSavedRegsBitmask() {
248 // CPU and FPU Saved Registers Bitmasks
249 unsigned CPUBitmask = 0, FPUBitmask = 0;
250 int CPUTopSavedRegOff, FPUTopSavedRegOff;
252 // Set the CPU and FPU Bitmasks
253 const MachineFrameInfo *MFI = MF->getFrameInfo();
254 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
255 // size of stack area to which FP callee-saved regs are saved.
256 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
257 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
258 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
259 bool HasAFGR64Reg = false;
260 unsigned CSFPRegsSize = 0;
261 unsigned i, e = CSI.size();
264 for (i = 0; i != e; ++i) {
265 unsigned Reg = CSI[i].getReg();
266 if (Mips::GPR32RegClass.contains(Reg))
270 TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg);
271 if (Mips::AFGR64RegClass.contains(Reg)) {
272 FPUBitmask |= (3 << RegNum);
273 CSFPRegsSize += AFGR64RegSize;
278 FPUBitmask |= (1 << RegNum);
279 CSFPRegsSize += FGR32RegSize;
283 for (; i != e; ++i) {
284 unsigned Reg = CSI[i].getReg();
286 TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg);
287 CPUBitmask |= (1 << RegNum);
290 // FP Regs are saved right below where the virtual frame pointer points to.
291 FPUTopSavedRegOff = FPUBitmask ?
292 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
294 // CPU Regs are saved below FP Regs.
295 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
297 MipsTargetStreamer &TS = getTargetStreamer();
299 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
302 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
305 //===----------------------------------------------------------------------===//
306 // Frame and Set directives
307 //===----------------------------------------------------------------------===//
310 void MipsAsmPrinter::emitFrameDirective() {
311 const TargetRegisterInfo &RI = *TM.getSubtargetImpl()->getRegisterInfo();
313 unsigned stackReg = RI.getFrameRegister(*MF);
314 unsigned returnReg = RI.getRARegister();
315 unsigned stackSize = MF->getFrameInfo()->getStackSize();
317 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
320 /// Emit Set directives.
321 const char *MipsAsmPrinter::getCurrentABIString() const {
322 switch (Subtarget->getABI().GetEnumValue()) {
323 case MipsABIInfo::ABI::O32: return "abi32";
324 case MipsABIInfo::ABI::N32: return "abiN32";
325 case MipsABIInfo::ABI::N64: return "abi64";
326 case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64
327 default: llvm_unreachable("Unknown Mips ABI");
331 void MipsAsmPrinter::EmitFunctionEntryLabel() {
332 MipsTargetStreamer &TS = getTargetStreamer();
334 // NaCl sandboxing requires that indirect call instructions are masked.
335 // This means that function entry points should be bundle-aligned.
336 if (Subtarget->isTargetNaCl())
337 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
339 if (Subtarget->inMicroMipsMode())
340 TS.emitDirectiveSetMicroMips();
342 TS.emitDirectiveSetNoMicroMips();
344 if (Subtarget->inMips16Mode())
345 TS.emitDirectiveSetMips16();
347 TS.emitDirectiveSetNoMips16();
349 TS.emitDirectiveEnt(*CurrentFnSym);
350 OutStreamer.EmitLabel(CurrentFnSym);
353 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
354 /// the first basic block in the function.
355 void MipsAsmPrinter::EmitFunctionBodyStart() {
356 MipsTargetStreamer &TS = getTargetStreamer();
358 MCInstLowering.Initialize(&MF->getContext());
360 bool IsNakedFunction =
362 getAttributes().hasAttribute(AttributeSet::FunctionIndex,
364 if (!IsNakedFunction)
365 emitFrameDirective();
367 if (!IsNakedFunction)
368 printSavedRegsBitmask();
370 if (!Subtarget->inMips16Mode()) {
371 TS.emitDirectiveSetNoReorder();
372 TS.emitDirectiveSetNoMacro();
373 TS.emitDirectiveSetNoAt();
377 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
378 /// the last basic block in the function.
379 void MipsAsmPrinter::EmitFunctionBodyEnd() {
380 MipsTargetStreamer &TS = getTargetStreamer();
382 // There are instruction for this macros, but they must
383 // always be at the function end, and we can't emit and
384 // break with BB logic.
385 if (!Subtarget->inMips16Mode()) {
386 TS.emitDirectiveSetAt();
387 TS.emitDirectiveSetMacro();
388 TS.emitDirectiveSetReorder();
390 TS.emitDirectiveEnd(CurrentFnSym->getName());
391 // Make sure to terminate any constant pools that were at the end
395 InConstantPool = false;
396 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
399 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
400 /// exactly one predecessor and the control transfer mechanism between
401 /// the predecessor and this block is a fall-through.
402 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
404 // The predecessor has to be immediately before this block.
405 const MachineBasicBlock *Pred = *MBB->pred_begin();
407 // If the predecessor is a switch statement, assume a jump table
408 // implementation, so it is not a fall through.
409 if (const BasicBlock *bb = Pred->getBasicBlock())
410 if (isa<SwitchInst>(bb->getTerminator()))
413 // If this is a landing pad, it isn't a fall through. If it has no preds,
414 // then nothing falls through to it.
415 if (MBB->isLandingPad() || MBB->pred_empty())
418 // If there isn't exactly one predecessor, it can't be a fall through.
419 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
422 if (PI2 != MBB->pred_end())
425 // The predecessor has to be immediately before this block.
426 if (!Pred->isLayoutSuccessor(MBB))
429 // If the block is completely empty, then it definitely does fall through.
433 // Otherwise, check the last instruction.
434 // Check if the last terminator is an unconditional branch.
435 MachineBasicBlock::const_iterator I = Pred->end();
436 while (I != Pred->begin() && !(--I)->isTerminator()) ;
438 return !I->isBarrier();
441 // Print out an operand for an inline asm expression.
442 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
443 unsigned AsmVariant,const char *ExtraCode,
445 // Does this asm operand have a single letter operand modifier?
446 if (ExtraCode && ExtraCode[0]) {
447 if (ExtraCode[1] != 0) return true; // Unknown modifier.
449 const MachineOperand &MO = MI->getOperand(OpNum);
450 switch (ExtraCode[0]) {
452 // See if this is a generic print operand
453 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
454 case 'X': // hex const int
455 if ((MO.getType()) != MachineOperand::MO_Immediate)
457 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
459 case 'x': // hex const int (low 16 bits)
460 if ((MO.getType()) != MachineOperand::MO_Immediate)
462 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
464 case 'd': // decimal const int
465 if ((MO.getType()) != MachineOperand::MO_Immediate)
469 case 'm': // decimal const int minus 1
470 if ((MO.getType()) != MachineOperand::MO_Immediate)
472 O << MO.getImm() - 1;
475 // $0 if zero, regular printing otherwise
476 if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
480 // If not, call printOperand as normal.
483 case 'D': // Second part of a double word register operand
484 case 'L': // Low order register of a double word register operand
485 case 'M': // High order register of a double word register operand
489 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
490 if (!FlagsOP.isImm())
492 unsigned Flags = FlagsOP.getImm();
493 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
494 // Number of registers represented by this operand. We are looking
495 // for 2 for 32 bit mode and 1 for 64 bit mode.
497 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
498 unsigned Reg = MO.getReg();
499 O << '$' << MipsInstPrinter::getRegisterName(Reg);
505 unsigned RegOp = OpNum;
506 if (!Subtarget->isGP64bit()){
507 // Endianess reverses which register holds the high or low value
509 switch(ExtraCode[0]) {
511 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
514 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
516 case 'D': // Always the second part
519 if (RegOp >= MI->getNumOperands())
521 const MachineOperand &MO = MI->getOperand(RegOp);
524 unsigned Reg = MO.getReg();
525 O << '$' << MipsInstPrinter::getRegisterName(Reg);
530 // Print MSA registers for the 'f' constraint
531 // In LLVM, the 'w' modifier doesn't need to do anything.
532 // We can just call printOperand as normal.
537 printOperand(MI, OpNum, O);
541 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
542 unsigned OpNum, unsigned AsmVariant,
543 const char *ExtraCode,
546 // Currently we are expecting either no ExtraCode or 'D'
548 if (ExtraCode[0] == 'D')
551 return true; // Unknown modifier.
554 const MachineOperand &MO = MI->getOperand(OpNum);
555 assert(MO.isReg() && "unexpected inline asm memory operand");
556 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
561 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
563 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
564 const MachineOperand &MO = MI->getOperand(opNum);
567 if (MO.getTargetFlags())
570 switch(MO.getTargetFlags()) {
571 case MipsII::MO_GPREL: O << "%gp_rel("; break;
572 case MipsII::MO_GOT_CALL: O << "%call16("; break;
573 case MipsII::MO_GOT: O << "%got("; break;
574 case MipsII::MO_ABS_HI: O << "%hi("; break;
575 case MipsII::MO_ABS_LO: O << "%lo("; break;
576 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
577 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
578 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
579 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
580 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
581 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
582 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
583 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
584 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
587 switch (MO.getType()) {
588 case MachineOperand::MO_Register:
590 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
593 case MachineOperand::MO_Immediate:
597 case MachineOperand::MO_MachineBasicBlock:
598 O << *MO.getMBB()->getSymbol();
601 case MachineOperand::MO_GlobalAddress:
602 O << *getSymbol(MO.getGlobal());
605 case MachineOperand::MO_BlockAddress: {
606 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
611 case MachineOperand::MO_ConstantPoolIndex:
612 O << DL->getPrivateGlobalPrefix() << "CPI"
613 << getFunctionNumber() << "_" << MO.getIndex();
615 O << "+" << MO.getOffset();
619 llvm_unreachable("<unknown operand type>");
622 if (closeP) O << ")";
625 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
627 const MachineOperand &MO = MI->getOperand(opNum);
629 O << (unsigned short int)MO.getImm();
631 printOperand(MI, opNum, O);
634 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
636 const MachineOperand &MO = MI->getOperand(opNum);
638 O << (unsigned short int)(unsigned char)MO.getImm();
640 printOperand(MI, opNum, O);
643 void MipsAsmPrinter::
644 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
645 // Load/Store memory operands -- imm($reg)
646 // If PIC target the target is loaded as the
647 // pattern lw $25,%call16($28)
649 // opNum can be invalid if instruction has reglist as operand.
650 // MemOperand is always last operand of instruction (base + offset).
651 switch (MI->getOpcode()) {
656 opNum = MI->getNumOperands() - 2;
660 printOperand(MI, opNum+1, O);
662 printOperand(MI, opNum, O);
666 void MipsAsmPrinter::
667 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
668 // when using stack locations for not load/store instructions
669 // print the same way as all normal 3 operand instructions.
670 printOperand(MI, opNum, O);
672 printOperand(MI, opNum+1, O);
676 void MipsAsmPrinter::
677 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
678 const char *Modifier) {
679 const MachineOperand &MO = MI->getOperand(opNum);
680 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
683 void MipsAsmPrinter::
684 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
685 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
686 if (i != opNum) O << ", ";
687 printOperand(MI, i, O);
691 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
692 bool IsABICalls = Subtarget->isABICalls();
694 getTargetStreamer().emitDirectiveAbiCalls();
695 Reloc::Model RM = TM.getRelocationModel();
696 // FIXME: This condition should be a lot more complicated that it is here.
697 // Ideally it should test for properties of the ABI and not the ABI
699 // For the moment, I'm only correcting enough to make MIPS-IV work.
700 if (RM == Reloc::Static && !Subtarget->isABI_N64())
701 getTargetStreamer().emitDirectiveOptionPic0();
704 // Tell the assembler which ABI we are using
705 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
706 OutStreamer.SwitchSection(OutContext.getELFSection(
707 SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
709 // NaN: At the moment we only support:
710 // 1. .nan legacy (default)
712 Subtarget->isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
713 : getTargetStreamer().emitDirectiveNaNLegacy();
715 // TODO: handle O64 ABI
717 if (Subtarget->isABI_EABI()) {
718 if (Subtarget->isGP32bit())
719 OutStreamer.SwitchSection(
720 OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
721 SectionKind::getDataRel()));
723 OutStreamer.SwitchSection(
724 OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
725 SectionKind::getDataRel()));
728 getTargetStreamer().updateABIInfo(*Subtarget);
730 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
731 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
732 // -mfp64) and omit it otherwise.
733 if (Subtarget->isABI_O32() && (Subtarget->isABI_FPXX() ||
734 Subtarget->isFP64bit()))
735 getTargetStreamer().emitDirectiveModuleFP();
737 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
738 // accept it. We therefore emit it when it contradicts the default or an
739 // option has changed the default (i.e. FPXX) and omit it otherwise.
740 if (Subtarget->isABI_O32() && (!Subtarget->useOddSPReg() ||
741 Subtarget->isABI_FPXX()))
742 getTargetStreamer().emitDirectiveModuleOddSPReg(Subtarget->useOddSPReg(),
743 Subtarget->isABI_O32());
746 void MipsAsmPrinter::emitInlineAsmStart(
747 const MCSubtargetInfo &StartInfo) const {
748 MipsTargetStreamer &TS = getTargetStreamer();
750 TS.emitDirectiveSetPush();
751 TS.emitDirectiveSetAt();
752 TS.emitDirectiveSetMacro();
753 TS.emitDirectiveSetReorder();
754 OutStreamer.AddBlankLine();
757 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
758 const MCSubtargetInfo *EndInfo) const {
759 OutStreamer.AddBlankLine();
760 getTargetStreamer().emitDirectiveSetPop();
763 void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
765 I.setOpcode(Mips::JAL);
767 MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
768 OutStreamer.EmitInstruction(I, getSubtargetInfo());
771 void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
774 I.addOperand(MCOperand::CreateReg(Reg));
775 OutStreamer.EmitInstruction(I, getSubtargetInfo());
778 void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
782 // Because of the current td files for Mips32, the operands for MTC1
783 // appear backwards from their normal assembly order. It's not a trivial
784 // change to fix this in the td file so we adjust for it here.
786 if (Opcode == Mips::MTC1) {
787 unsigned Temp = Reg1;
792 I.addOperand(MCOperand::CreateReg(Reg1));
793 I.addOperand(MCOperand::CreateReg(Reg2));
794 OutStreamer.EmitInstruction(I, getSubtargetInfo());
797 void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
798 unsigned Reg2, unsigned Reg3) {
801 I.addOperand(MCOperand::CreateReg(Reg1));
802 I.addOperand(MCOperand::CreateReg(Reg2));
803 I.addOperand(MCOperand::CreateReg(Reg3));
804 OutStreamer.EmitInstruction(I, getSubtargetInfo());
807 void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
808 unsigned Reg2, unsigned FPReg1,
809 unsigned FPReg2, bool LE) {
811 unsigned temp = Reg1;
815 EmitInstrRegReg(MovOpc, Reg1, FPReg1);
816 EmitInstrRegReg(MovOpc, Reg2, FPReg2);
819 void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
820 bool LE, bool ToFP) {
821 using namespace Mips16HardFloatInfo;
822 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
825 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
828 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
831 EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
832 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
835 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
838 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
839 EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
842 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
843 EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
851 MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
853 using namespace Mips16HardFloatInfo;
854 unsigned MovOpc = Mips::MFC1;
857 EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
860 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
863 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
866 EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
867 EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
874 void MipsAsmPrinter::EmitFPCallStub(
875 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
876 MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
877 using namespace Mips16HardFloatInfo;
878 bool LE = Subtarget->isLittle();
882 OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
885 // make the comment field identifying the return and parameter
886 // types of the floating point stub
887 // # Stub function to call rettype xxxx (params)
889 switch (Signature->RetSig) {
900 RetType = "double complex";
907 switch (Signature->ParamSig) {
912 Parms = "float, float";
915 Parms = "float, double";
921 Parms = "double, double";
924 Parms = "double, float";
930 OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
931 Twine(Symbol) + " (" + Twine(Parms) + ")");
933 // probably not necessary but we save and restore the current section state
935 OutStreamer.PushSection();
937 // .section mips16.call.fpxxxx,"ax",@progbits
939 const MCSectionELF *M = OutContext.getELFSection(
940 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
941 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
942 OutStreamer.SwitchSection(M, nullptr);
946 OutStreamer.EmitValueToAlignment(4);
947 MipsTargetStreamer &TS = getTargetStreamer();
952 TS.emitDirectiveSetNoMips16();
953 TS.emitDirectiveSetNoMicroMips();
955 // .ent __call_stub_fp_xxxx
956 // .type __call_stub_fp_xxxx,@function
957 // __call_stub_fp_xxxx:
959 std::string x = "__call_stub_fp_" + std::string(Symbol);
960 MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
961 TS.emitDirectiveEnt(*Stub);
963 OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
964 OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
965 OutStreamer.EmitLabel(Stub);
967 // we just handle non pic for now. these function will not be
968 // called otherwise. when the full stub generation is moved here
969 // we need to deal with pic.
971 if (TM.getRelocationModel() == Reloc::PIC_)
972 llvm_unreachable("should not be here if we are compiling pic");
973 TS.emitDirectiveSetReorder();
975 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
976 // stubs without raw text but this current patch is for compiler generated
977 // functions and they all return some value.
978 // The calling sequence for non pic is different in that case and we need
979 // to implement %lo and %hi in order to handle the case of no return value
980 // See the corresponding method in Mips16HardFloat for details.
982 // mov the return address to S2.
983 // we have no stack space to store it and we are about to make another call.
984 // We need to make sure that the enclosing function knows to save S2
985 // This should have already been handled.
989 EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
991 EmitSwapFPIntParams(Signature->ParamSig, LE, true);
998 EmitSwapFPIntRetval(Signature->RetSig, LE);
1001 // if (Signature->RetSig == NoFPRet)
1002 // llvm_unreachable("should not be any stubs here with no return value");
1004 EmitInstrReg(Mips::JR, Mips::S2);
1006 MCSymbol *Tmp = OutContext.CreateTempSymbol();
1007 OutStreamer.EmitLabel(Tmp);
1008 const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
1009 const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
1010 const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
1011 OutStreamer.EmitELFSize(Stub, T_min_E);
1012 TS.emitDirectiveEnd(x);
1013 OutStreamer.PopSection();
1016 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
1017 // Emit needed stubs
1021 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
1022 it = StubsNeeded.begin();
1023 it != StubsNeeded.end(); ++it) {
1024 const char *Symbol = it->first;
1025 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1026 EmitFPCallStub(Symbol, Signature);
1028 // return to the text section
1029 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
1032 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1037 // Align all targets of indirect branches on bundle size. Used only if target
1039 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1040 // Align all blocks that are jumped to through jump table.
1041 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1042 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1043 for (unsigned I = 0; I < JT.size(); ++I) {
1044 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1046 for (unsigned J = 0; J < MBBs.size(); ++J)
1047 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1051 // If basic block address is taken, block can be target of indirect branch.
1052 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
1054 if (MBB->hasAddressTaken())
1055 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1059 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1060 return (Opcode == Mips::LONG_BRANCH_LUi
1061 || Opcode == Mips::LONG_BRANCH_ADDiu
1062 || Opcode == Mips::LONG_BRANCH_DADDiu);
1065 // Force static initialization.
1066 extern "C" void LLVMInitializeMipsAsmPrinter() {
1067 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
1068 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
1069 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
1070 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);