1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MipsAsmPrinter.h"
20 #include "MipsInstrInfo.h"
21 #include "MipsMCInstLower.h"
22 #include "MipsTargetMachine.h"
23 #include "MipsTargetStreamer.h"
24 #include "llvm/ADT/SmallString.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/Twine.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/IR/BasicBlock.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/InlineAsm.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/Mangler.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCSection.h"
44 #include "llvm/MC/MCSectionELF.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ELF.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetLoweringObjectFile.h"
50 #include "llvm/Target/TargetOptions.h"
55 #define DEBUG_TYPE "mips-asm-printer"
57 MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
58 return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
61 bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
62 Subtarget = &MF.getSubtarget<MipsSubtarget>();
64 // Initialize TargetLoweringObjectFile.
65 const_cast<TargetLoweringObjectFile &>(getObjFileLowering())
66 .Initialize(OutContext, TM);
68 MipsFI = MF.getInfo<MipsFunctionInfo>();
69 if (Subtarget->inMips16Mode())
72 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
73 it = MipsFI->StubsNeeded.begin();
74 it != MipsFI->StubsNeeded.end(); ++it) {
75 const char *Symbol = it->first;
76 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
77 if (StubsNeeded.find(Symbol) == StubsNeeded.end())
78 StubsNeeded[Symbol] = Signature;
80 MCP = MF.getConstantPool();
82 // In NaCl, all indirect jump targets must be aligned to bundle size.
83 if (Subtarget->isTargetNaCl())
84 NaClAlignIndirectJumpTargets(MF);
86 AsmPrinter::runOnMachineFunction(MF);
90 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
91 MCOp = MCInstLowering.LowerOperand(MO);
92 return MCOp.isValid();
95 #include "MipsGenMCPseudoLowering.inc"
97 // Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
98 // JALR, or JALR64 as appropriate for the target
99 void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
100 const MachineInstr *MI) {
101 bool HasLinkReg = false;
104 if (Subtarget->hasMips64r6()) {
105 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
106 TmpInst0.setOpcode(Mips::JALR64);
108 } else if (Subtarget->hasMips32r6()) {
109 // MIPS32r6 should use (JALR ZERO, $rs)
110 TmpInst0.setOpcode(Mips::JALR);
112 } else if (Subtarget->inMicroMipsMode())
113 // microMIPS should use (JR_MM $rs)
114 TmpInst0.setOpcode(Mips::JR_MM);
116 // Everything else should use (JR $rs)
117 TmpInst0.setOpcode(Mips::JR);
123 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
124 TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
127 lowerOperand(MI->getOperand(0), MCOp);
128 TmpInst0.addOperand(MCOp);
130 EmitToStreamer(OutStreamer, TmpInst0);
133 void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
134 MipsTargetStreamer &TS = getTargetStreamer();
135 TS.forbidModuleDirective();
137 if (MI->isDebugValue()) {
138 SmallString<128> Str;
139 raw_svector_ostream OS(Str);
141 PrintDebugValueComment(MI, OS);
145 // If we just ended a constant pool, mark it as such.
146 if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
147 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
148 InConstantPool = false;
150 if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
151 // CONSTPOOL_ENTRY - This instruction represents a floating
152 //constant pool in the function. The first operand is the ID#
153 // for this instruction, the second is the index into the
154 // MachineConstantPool that this is, the third is the size in
155 // bytes of this constant pool entry.
156 // The required alignment is specified on the basic block holding this MI.
158 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
159 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
161 // If this is the first entry of the pool, mark it.
162 if (!InConstantPool) {
163 OutStreamer.EmitDataRegion(MCDR_DataRegion);
164 InConstantPool = true;
167 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
169 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
170 if (MCPE.isMachineConstantPoolEntry())
171 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
173 EmitGlobalConstant(MCPE.Val.ConstVal);
178 MachineBasicBlock::const_instr_iterator I = MI;
179 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
182 // Do any auto-generated pseudo lowerings.
183 if (emitPseudoExpansionLowering(OutStreamer, &*I))
186 if (I->getOpcode() == Mips::PseudoReturn ||
187 I->getOpcode() == Mips::PseudoReturn64 ||
188 I->getOpcode() == Mips::PseudoIndirectBranch ||
189 I->getOpcode() == Mips::PseudoIndirectBranch64) {
190 emitPseudoIndirectBranch(OutStreamer, &*I);
194 // The inMips16Mode() test is not permanent.
195 // Some instructions are marked as pseudo right now which
196 // would make the test fail for the wrong reason but
197 // that will be fixed soon. We need this here because we are
198 // removing another test for this situation downstream in the
201 if (I->isPseudo() && !Subtarget->inMips16Mode()
202 && !isLongBranchPseudo(I->getOpcode()))
203 llvm_unreachable("Pseudo opcode found in EmitInstruction()");
206 MCInstLowering.Lower(I, TmpInst0);
207 EmitToStreamer(OutStreamer, TmpInst0);
208 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
211 //===----------------------------------------------------------------------===//
213 // Mips Asm Directives
215 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
216 // Describe the stack frame.
218 // -- Mask directives "(f)mask bitmask, offset"
219 // Tells the assembler which registers are saved and where.
220 // bitmask - contain a little endian bitset indicating which registers are
221 // saved on function prologue (e.g. with a 0x80000000 mask, the
222 // assembler knows the register 31 (RA) is saved at prologue.
223 // offset - the position before stack pointer subtraction indicating where
224 // the first saved register on prologue is located. (e.g. with a
226 // Consider the following function prologue:
229 // .mask 0xc0000000,-8
230 // addiu $sp, $sp, -48
234 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
235 // 30 (FP) are saved at prologue. As the save order on prologue is from
236 // left to right, RA is saved first. A -8 offset means that after the
237 // stack pointer subtration, the first register in the mask (RA) will be
238 // saved at address 48-8=40.
240 //===----------------------------------------------------------------------===//
242 //===----------------------------------------------------------------------===//
244 //===----------------------------------------------------------------------===//
246 // Create a bitmask with all callee saved registers for CPU or Floating Point
247 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
248 void MipsAsmPrinter::printSavedRegsBitmask() {
249 // CPU and FPU Saved Registers Bitmasks
250 unsigned CPUBitmask = 0, FPUBitmask = 0;
251 int CPUTopSavedRegOff, FPUTopSavedRegOff;
253 // Set the CPU and FPU Bitmasks
254 const MachineFrameInfo *MFI = MF->getFrameInfo();
255 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
256 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
257 // size of stack area to which FP callee-saved regs are saved.
258 unsigned CPURegSize = Mips::GPR32RegClass.getSize();
259 unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
260 unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
261 bool HasAFGR64Reg = false;
262 unsigned CSFPRegsSize = 0;
263 unsigned i, e = CSI.size();
266 for (i = 0; i != e; ++i) {
267 unsigned Reg = CSI[i].getReg();
268 if (Mips::GPR32RegClass.contains(Reg))
271 unsigned RegNum = TRI->getEncodingValue(Reg);
272 if (Mips::AFGR64RegClass.contains(Reg)) {
273 FPUBitmask |= (3 << RegNum);
274 CSFPRegsSize += AFGR64RegSize;
279 FPUBitmask |= (1 << RegNum);
280 CSFPRegsSize += FGR32RegSize;
284 for (; i != e; ++i) {
285 unsigned Reg = CSI[i].getReg();
286 unsigned RegNum = TRI->getEncodingValue(Reg);
287 CPUBitmask |= (1 << RegNum);
290 // FP Regs are saved right below where the virtual frame pointer points to.
291 FPUTopSavedRegOff = FPUBitmask ?
292 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
294 // CPU Regs are saved below FP Regs.
295 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
297 MipsTargetStreamer &TS = getTargetStreamer();
299 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
302 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
305 //===----------------------------------------------------------------------===//
306 // Frame and Set directives
307 //===----------------------------------------------------------------------===//
310 void MipsAsmPrinter::emitFrameDirective() {
311 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
313 unsigned stackReg = RI.getFrameRegister(*MF);
314 unsigned returnReg = RI.getRARegister();
315 unsigned stackSize = MF->getFrameInfo()->getStackSize();
317 getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
320 /// Emit Set directives.
321 const char *MipsAsmPrinter::getCurrentABIString() const {
322 switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
323 case MipsABIInfo::ABI::O32: return "abi32";
324 case MipsABIInfo::ABI::N32: return "abiN32";
325 case MipsABIInfo::ABI::N64: return "abi64";
326 case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64
327 default: llvm_unreachable("Unknown Mips ABI");
331 void MipsAsmPrinter::EmitFunctionEntryLabel() {
332 MipsTargetStreamer &TS = getTargetStreamer();
334 // NaCl sandboxing requires that indirect call instructions are masked.
335 // This means that function entry points should be bundle-aligned.
336 if (Subtarget->isTargetNaCl())
337 EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
339 if (Subtarget->inMicroMipsMode())
340 TS.emitDirectiveSetMicroMips();
342 TS.emitDirectiveSetNoMicroMips();
344 if (Subtarget->inMips16Mode())
345 TS.emitDirectiveSetMips16();
347 TS.emitDirectiveSetNoMips16();
349 TS.emitDirectiveEnt(*CurrentFnSym);
350 OutStreamer.EmitLabel(CurrentFnSym);
353 /// EmitFunctionBodyStart - Targets can override this to emit stuff before
354 /// the first basic block in the function.
355 void MipsAsmPrinter::EmitFunctionBodyStart() {
356 MipsTargetStreamer &TS = getTargetStreamer();
358 MCInstLowering.Initialize(&MF->getContext());
360 bool IsNakedFunction = MF->getFunction()->hasFnAttribute(Attribute::Naked);
361 if (!IsNakedFunction)
362 emitFrameDirective();
364 if (!IsNakedFunction)
365 printSavedRegsBitmask();
367 if (!Subtarget->inMips16Mode()) {
368 TS.emitDirectiveSetNoReorder();
369 TS.emitDirectiveSetNoMacro();
370 TS.emitDirectiveSetNoAt();
374 /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
375 /// the last basic block in the function.
376 void MipsAsmPrinter::EmitFunctionBodyEnd() {
377 MipsTargetStreamer &TS = getTargetStreamer();
379 // There are instruction for this macros, but they must
380 // always be at the function end, and we can't emit and
381 // break with BB logic.
382 if (!Subtarget->inMips16Mode()) {
383 TS.emitDirectiveSetAt();
384 TS.emitDirectiveSetMacro();
385 TS.emitDirectiveSetReorder();
387 TS.emitDirectiveEnd(CurrentFnSym->getName());
388 // Make sure to terminate any constant pools that were at the end
392 InConstantPool = false;
393 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
396 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
397 /// exactly one predecessor and the control transfer mechanism between
398 /// the predecessor and this block is a fall-through.
399 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
401 // The predecessor has to be immediately before this block.
402 const MachineBasicBlock *Pred = *MBB->pred_begin();
404 // If the predecessor is a switch statement, assume a jump table
405 // implementation, so it is not a fall through.
406 if (const BasicBlock *bb = Pred->getBasicBlock())
407 if (isa<SwitchInst>(bb->getTerminator()))
410 // If this is a landing pad, it isn't a fall through. If it has no preds,
411 // then nothing falls through to it.
412 if (MBB->isLandingPad() || MBB->pred_empty())
415 // If there isn't exactly one predecessor, it can't be a fall through.
416 MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
419 if (PI2 != MBB->pred_end())
422 // The predecessor has to be immediately before this block.
423 if (!Pred->isLayoutSuccessor(MBB))
426 // If the block is completely empty, then it definitely does fall through.
430 // Otherwise, check the last instruction.
431 // Check if the last terminator is an unconditional branch.
432 MachineBasicBlock::const_iterator I = Pred->end();
433 while (I != Pred->begin() && !(--I)->isTerminator()) ;
435 return !I->isBarrier();
438 // Print out an operand for an inline asm expression.
439 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
440 unsigned AsmVariant,const char *ExtraCode,
442 // Does this asm operand have a single letter operand modifier?
443 if (ExtraCode && ExtraCode[0]) {
444 if (ExtraCode[1] != 0) return true; // Unknown modifier.
446 const MachineOperand &MO = MI->getOperand(OpNum);
447 switch (ExtraCode[0]) {
449 // See if this is a generic print operand
450 return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
451 case 'X': // hex const int
452 if ((MO.getType()) != MachineOperand::MO_Immediate)
454 O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
456 case 'x': // hex const int (low 16 bits)
457 if ((MO.getType()) != MachineOperand::MO_Immediate)
459 O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
461 case 'd': // decimal const int
462 if ((MO.getType()) != MachineOperand::MO_Immediate)
466 case 'm': // decimal const int minus 1
467 if ((MO.getType()) != MachineOperand::MO_Immediate)
469 O << MO.getImm() - 1;
472 // $0 if zero, regular printing otherwise
473 if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
477 // If not, call printOperand as normal.
480 case 'D': // Second part of a double word register operand
481 case 'L': // Low order register of a double word register operand
482 case 'M': // High order register of a double word register operand
486 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
487 if (!FlagsOP.isImm())
489 unsigned Flags = FlagsOP.getImm();
490 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
491 // Number of registers represented by this operand. We are looking
492 // for 2 for 32 bit mode and 1 for 64 bit mode.
494 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
495 unsigned Reg = MO.getReg();
496 O << '$' << MipsInstPrinter::getRegisterName(Reg);
502 unsigned RegOp = OpNum;
503 if (!Subtarget->isGP64bit()){
504 // Endianess reverses which register holds the high or low value
506 switch(ExtraCode[0]) {
508 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
511 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
513 case 'D': // Always the second part
516 if (RegOp >= MI->getNumOperands())
518 const MachineOperand &MO = MI->getOperand(RegOp);
521 unsigned Reg = MO.getReg();
522 O << '$' << MipsInstPrinter::getRegisterName(Reg);
527 // Print MSA registers for the 'f' constraint
528 // In LLVM, the 'w' modifier doesn't need to do anything.
529 // We can just call printOperand as normal.
534 printOperand(MI, OpNum, O);
538 bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
539 unsigned OpNum, unsigned AsmVariant,
540 const char *ExtraCode,
543 // Currently we are expecting either no ExtraCode or 'D'
545 if (ExtraCode[0] == 'D')
548 return true; // Unknown modifier.
551 const MachineOperand &MO = MI->getOperand(OpNum);
552 assert(MO.isReg() && "unexpected inline asm memory operand");
553 O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
558 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
560 const DataLayout *DL = TM.getDataLayout();
561 const MachineOperand &MO = MI->getOperand(opNum);
564 if (MO.getTargetFlags())
567 switch(MO.getTargetFlags()) {
568 case MipsII::MO_GPREL: O << "%gp_rel("; break;
569 case MipsII::MO_GOT_CALL: O << "%call16("; break;
570 case MipsII::MO_GOT: O << "%got("; break;
571 case MipsII::MO_ABS_HI: O << "%hi("; break;
572 case MipsII::MO_ABS_LO: O << "%lo("; break;
573 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
574 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
575 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
576 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
577 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
578 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
579 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
580 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
581 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
584 switch (MO.getType()) {
585 case MachineOperand::MO_Register:
587 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
590 case MachineOperand::MO_Immediate:
594 case MachineOperand::MO_MachineBasicBlock:
595 O << *MO.getMBB()->getSymbol();
598 case MachineOperand::MO_GlobalAddress:
599 O << *getSymbol(MO.getGlobal());
602 case MachineOperand::MO_BlockAddress: {
603 MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
608 case MachineOperand::MO_ConstantPoolIndex:
609 O << DL->getPrivateGlobalPrefix() << "CPI"
610 << getFunctionNumber() << "_" << MO.getIndex();
612 O << "+" << MO.getOffset();
616 llvm_unreachable("<unknown operand type>");
619 if (closeP) O << ")";
622 void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
624 const MachineOperand &MO = MI->getOperand(opNum);
626 O << (unsigned short int)MO.getImm();
628 printOperand(MI, opNum, O);
631 void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
633 const MachineOperand &MO = MI->getOperand(opNum);
635 O << (unsigned short int)(unsigned char)MO.getImm();
637 printOperand(MI, opNum, O);
640 void MipsAsmPrinter::
641 printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
642 // Load/Store memory operands -- imm($reg)
643 // If PIC target the target is loaded as the
644 // pattern lw $25,%call16($28)
646 // opNum can be invalid if instruction has reglist as operand.
647 // MemOperand is always last operand of instruction (base + offset).
648 switch (MI->getOpcode()) {
653 opNum = MI->getNumOperands() - 2;
657 printOperand(MI, opNum+1, O);
659 printOperand(MI, opNum, O);
663 void MipsAsmPrinter::
664 printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
665 // when using stack locations for not load/store instructions
666 // print the same way as all normal 3 operand instructions.
667 printOperand(MI, opNum, O);
669 printOperand(MI, opNum+1, O);
673 void MipsAsmPrinter::
674 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
675 const char *Modifier) {
676 const MachineOperand &MO = MI->getOperand(opNum);
677 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
680 void MipsAsmPrinter::
681 printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
682 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
683 if (i != opNum) O << ", ";
684 printOperand(MI, i, O);
688 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
690 // Compute MIPS architecture attributes based on the default subtarget
691 // that we'd have constructed. Module level directives aren't LTO
693 // FIXME: For ifunc related functions we could iterate over and look
694 // for a feature string that doesn't match the default one.
695 StringRef TT = TM.getTargetTriple();
697 MIPS_MC::selectMipsCPU(TM.getTargetTriple(), TM.getTargetCPU());
698 StringRef FS = TM.getTargetFeatureString();
699 const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
700 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM);
702 bool IsABICalls = STI.isABICalls();
703 const MipsABIInfo &ABI = MTM.getABI();
705 getTargetStreamer().emitDirectiveAbiCalls();
706 Reloc::Model RM = TM.getRelocationModel();
707 // FIXME: This condition should be a lot more complicated that it is here.
708 // Ideally it should test for properties of the ABI and not the ABI
710 // For the moment, I'm only correcting enough to make MIPS-IV work.
711 if (RM == Reloc::Static && !ABI.IsN64())
712 getTargetStreamer().emitDirectiveOptionPic0();
715 // Tell the assembler which ABI we are using
716 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
717 OutStreamer.SwitchSection(
718 OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS, 0));
720 // NaN: At the moment we only support:
721 // 1. .nan legacy (default)
723 STI.isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
724 : getTargetStreamer().emitDirectiveNaNLegacy();
726 // TODO: handle O64 ABI
730 OutStreamer.SwitchSection(OutContext.getELFSection(".gcc_compiled_long32",
731 ELF::SHT_PROGBITS, 0));
733 OutStreamer.SwitchSection(OutContext.getELFSection(".gcc_compiled_long64",
734 ELF::SHT_PROGBITS, 0));
737 getTargetStreamer().updateABIInfo(STI);
739 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
740 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
741 // -mfp64) and omit it otherwise.
742 if (ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit()))
743 getTargetStreamer().emitDirectiveModuleFP();
745 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
746 // accept it. We therefore emit it when it contradicts the default or an
747 // option has changed the default (i.e. FPXX) and omit it otherwise.
748 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
749 getTargetStreamer().emitDirectiveModuleOddSPReg(STI.useOddSPReg(),
753 void MipsAsmPrinter::emitInlineAsmStart() const {
754 MipsTargetStreamer &TS = getTargetStreamer();
756 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
757 // and 'reorder') is different from LLVM's choice for generated code ('noat',
758 // 'nomacro' and 'noreorder').
759 // In order to maintain compatibility with inline assembly code which depends
760 // on GCC's assembler options being used, we have to switch to those options
761 // for the duration of the inline assembly block and then switch back.
762 TS.emitDirectiveSetPush();
763 TS.emitDirectiveSetAt();
764 TS.emitDirectiveSetMacro();
765 TS.emitDirectiveSetReorder();
766 OutStreamer.AddBlankLine();
769 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
770 const MCSubtargetInfo *EndInfo) const {
771 OutStreamer.AddBlankLine();
772 getTargetStreamer().emitDirectiveSetPop();
775 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
777 I.setOpcode(Mips::JAL);
779 MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
780 OutStreamer.EmitInstruction(I, STI);
783 void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
787 I.addOperand(MCOperand::CreateReg(Reg));
788 OutStreamer.EmitInstruction(I, STI);
791 void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
792 unsigned Opcode, unsigned Reg1,
796 // Because of the current td files for Mips32, the operands for MTC1
797 // appear backwards from their normal assembly order. It's not a trivial
798 // change to fix this in the td file so we adjust for it here.
800 if (Opcode == Mips::MTC1) {
801 unsigned Temp = Reg1;
806 I.addOperand(MCOperand::CreateReg(Reg1));
807 I.addOperand(MCOperand::CreateReg(Reg2));
808 OutStreamer.EmitInstruction(I, STI);
811 void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
812 unsigned Opcode, unsigned Reg1,
813 unsigned Reg2, unsigned Reg3) {
816 I.addOperand(MCOperand::CreateReg(Reg1));
817 I.addOperand(MCOperand::CreateReg(Reg2));
818 I.addOperand(MCOperand::CreateReg(Reg3));
819 OutStreamer.EmitInstruction(I, STI);
822 void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
823 unsigned MovOpc, unsigned Reg1,
824 unsigned Reg2, unsigned FPReg1,
825 unsigned FPReg2, bool LE) {
827 unsigned temp = Reg1;
831 EmitInstrRegReg(STI, MovOpc, Reg1, FPReg1);
832 EmitInstrRegReg(STI, MovOpc, Reg2, FPReg2);
835 void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
836 Mips16HardFloatInfo::FPParamVariant PV,
837 bool LE, bool ToFP) {
838 using namespace Mips16HardFloatInfo;
839 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
842 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
845 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
848 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
849 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
852 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
855 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
856 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
859 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
860 EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
867 void MipsAsmPrinter::EmitSwapFPIntRetval(
868 const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
870 using namespace Mips16HardFloatInfo;
871 unsigned MovOpc = Mips::MFC1;
874 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
877 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
880 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
883 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
884 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
891 void MipsAsmPrinter::EmitFPCallStub(
892 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
893 MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
894 using namespace Mips16HardFloatInfo;
895 bool LE = getDataLayout().isLittleEndian();
896 // Construct a local MCSubtargetInfo here.
897 // This is because the MachineFunction won't exist (but have not yet been
898 // freed) and since we're at the global level we can use the default
899 // constructed subtarget.
900 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
901 TM.getTargetTriple(), TM.getTargetCPU(), TM.getTargetFeatureString()));
906 OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
909 // make the comment field identifying the return and parameter
910 // types of the floating point stub
911 // # Stub function to call rettype xxxx (params)
913 switch (Signature->RetSig) {
924 RetType = "double complex";
931 switch (Signature->ParamSig) {
936 Parms = "float, float";
939 Parms = "float, double";
945 Parms = "double, double";
948 Parms = "double, float";
954 OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
955 Twine(Symbol) + " (" + Twine(Parms) + ")");
957 // probably not necessary but we save and restore the current section state
959 OutStreamer.PushSection();
961 // .section mips16.call.fpxxxx,"ax",@progbits
963 const MCSectionELF *M = OutContext.getELFSection(
964 ".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
965 ELF::SHF_ALLOC | ELF::SHF_EXECINSTR);
966 OutStreamer.SwitchSection(M, nullptr);
970 OutStreamer.EmitValueToAlignment(4);
971 MipsTargetStreamer &TS = getTargetStreamer();
976 TS.emitDirectiveSetNoMips16();
977 TS.emitDirectiveSetNoMicroMips();
979 // .ent __call_stub_fp_xxxx
980 // .type __call_stub_fp_xxxx,@function
981 // __call_stub_fp_xxxx:
983 std::string x = "__call_stub_fp_" + std::string(Symbol);
984 MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
985 TS.emitDirectiveEnt(*Stub);
987 OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
988 OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
989 OutStreamer.EmitLabel(Stub);
991 // Only handle non-pic for now.
992 assert(TM.getRelocationModel() != Reloc::PIC_ &&
993 "should not be here if we are compiling pic");
994 TS.emitDirectiveSetReorder();
996 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
997 // stubs without raw text but this current patch is for compiler generated
998 // functions and they all return some value.
999 // The calling sequence for non pic is different in that case and we need
1000 // to implement %lo and %hi in order to handle the case of no return value
1001 // See the corresponding method in Mips16HardFloat for details.
1003 // mov the return address to S2.
1004 // we have no stack space to store it and we are about to make another call.
1005 // We need to make sure that the enclosing function knows to save S2
1006 // This should have already been handled.
1010 EmitInstrRegRegReg(*STI, Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
1012 EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
1016 EmitJal(*STI, MSymbol);
1018 // fix return values
1019 EmitSwapFPIntRetval(*STI, Signature->RetSig, LE);
1022 // if (Signature->RetSig == NoFPRet)
1023 // llvm_unreachable("should not be any stubs here with no return value");
1025 EmitInstrReg(*STI, Mips::JR, Mips::S2);
1027 MCSymbol *Tmp = OutContext.CreateTempSymbol();
1028 OutStreamer.EmitLabel(Tmp);
1029 const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
1030 const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
1031 const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
1032 OutStreamer.EmitELFSize(Stub, T_min_E);
1033 TS.emitDirectiveEnd(x);
1034 OutStreamer.PopSection();
1037 void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
1038 // Emit needed stubs
1042 const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
1043 it = StubsNeeded.begin();
1044 it != StubsNeeded.end(); ++it) {
1045 const char *Symbol = it->first;
1046 const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1047 EmitFPCallStub(Symbol, Signature);
1049 // return to the text section
1050 OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
1053 void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1058 // Align all targets of indirect branches on bundle size. Used only if target
1060 void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1061 // Align all blocks that are jumped to through jump table.
1062 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1063 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1064 for (unsigned I = 0; I < JT.size(); ++I) {
1065 const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
1067 for (unsigned J = 0; J < MBBs.size(); ++J)
1068 MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1072 // If basic block address is taken, block can be target of indirect branch.
1073 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
1075 if (MBB->hasAddressTaken())
1076 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1080 bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1081 return (Opcode == Mips::LONG_BRANCH_LUi
1082 || Opcode == Mips::LONG_BRANCH_ADDiu
1083 || Opcode == Mips::LONG_BRANCH_DADDiu);
1086 // Force static initialization.
1087 extern "C" void LLVMInitializeMipsAsmPrinter() {
1088 RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
1089 RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
1090 RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
1091 RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);