1 //===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes Mips64 instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Mips Operand, Complex Patterns and Transformations Definitions.
16 //===----------------------------------------------------------------------===//
19 def uimm5_64 : Operand<i64> {
20 let PrintMethod = "printUnsignedImm";
23 def uimm16_64 : Operand<i64> {
24 let PrintMethod = "printUnsignedImm";
28 def simm10_64 : Operand<i64>;
30 // Transformation Function - get Imm - 32.
31 def Subtract32 : SDNodeXForm<imm, [{
32 return getImm(N, (unsigned)N->getZExtValue() - 32);
35 // shamt must fit in 6 bits.
36 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
38 // Node immediate fits as 10-bit sign extended on target immediate.
40 def immSExt10_64 : PatLeaf<(i64 imm),
41 [{ return isInt<10>(N->getSExtValue()); }]>;
43 def immZExt16_64 : PatLeaf<(i64 imm),
44 [{ return isInt<16>(N->getZExtValue()); }]>;
46 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
48 // Transformation function: get log2 of low 32 bits of immediate
49 def Log2LO : SDNodeXForm<imm, [{
50 return getImm(N, Log2_64((unsigned) N->getZExtValue()));
53 // Transformation function: get log2 of high 32 bits of immediate
54 def Log2HI : SDNodeXForm<imm, [{
55 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
58 // Predicate: True if immediate is a power of 2 and fits 32 bits
59 def PowerOf2LO : PatLeaf<(imm), [{
60 if (N->getValueType(0) == MVT::i64) {
61 uint64_t Imm = N->getZExtValue();
62 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm;
68 // Predicate: True if immediate is a power of 2 and exceeds 32 bits
69 def PowerOf2HI : PatLeaf<(imm), [{
70 if (N->getValueType(0) == MVT::i64) {
71 uint64_t Imm = N->getZExtValue();
72 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
78 //===----------------------------------------------------------------------===//
79 // Instructions specific format
80 //===----------------------------------------------------------------------===//
81 let usesCustomInserter = 1 in {
82 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
83 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
84 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
85 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
86 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
87 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
88 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
89 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
92 /// Pseudo instructions for loading and storing accumulator registers.
93 let isPseudo = 1, isCodeGenOnly = 1 in {
94 def LOAD_ACC128 : Load<"", ACC128>;
95 def STORE_ACC128 : Store<"", ACC128>;
98 //===----------------------------------------------------------------------===//
99 // Instruction definition
100 //===----------------------------------------------------------------------===//
101 let DecoderNamespace = "Mips64" in {
102 /// Arithmetic Instructions (ALU Immediate)
103 def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
104 ISA_MIPS3_NOT_32R6_64R6;
105 def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
107 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
109 let isCodeGenOnly = 1 in {
110 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
112 def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
114 def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
116 def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
118 def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
120 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
123 /// Arithmetic Instructions (3-Operand, R-Type)
124 def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
126 def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
128 def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
130 def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
133 let isCodeGenOnly = 1 in {
134 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
135 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
136 def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
137 def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
138 def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
139 def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
142 /// Shift Instructions
143 def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
144 SRA_FM<0x38, 0>, ISA_MIPS3;
145 def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
146 SRA_FM<0x3a, 0>, ISA_MIPS3;
147 def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
148 SRA_FM<0x3b, 0>, ISA_MIPS3;
149 def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
150 SRLV_FM<0x14, 0>, ISA_MIPS3;
151 def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
152 SRLV_FM<0x16, 0>, ISA_MIPS3;
153 def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
154 SRLV_FM<0x17, 0>, ISA_MIPS3;
155 def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
156 SRA_FM<0x3c, 0>, ISA_MIPS3;
157 def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
158 SRA_FM<0x3e, 0>, ISA_MIPS3;
159 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
160 SRA_FM<0x3f, 0>, ISA_MIPS3;
162 // Rotate Instructions
163 def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
165 SRA_FM<0x3a, 1>, ISA_MIPS64R2;
166 def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
167 SRLV_FM<0x16, 1>, ISA_MIPS64R2;
168 def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
169 SRA_FM<0x3e, 1>, ISA_MIPS64R2;
171 /// Load and Store Instructions
173 let isCodeGenOnly = 1 in {
174 def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
175 def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
176 def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
177 def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
178 def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
179 def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>;
180 def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
181 def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
184 def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
185 def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
186 def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
188 /// load/store left/right
189 let isCodeGenOnly = 1 in {
190 def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
191 def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
192 def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
193 def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
196 def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
197 ISA_MIPS3_NOT_32R6_64R6;
198 def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
199 ISA_MIPS3_NOT_32R6_64R6;
200 def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
201 ISA_MIPS3_NOT_32R6_64R6;
202 def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
203 ISA_MIPS3_NOT_32R6_64R6;
205 /// Load-linked, Store-conditional
206 def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6;
207 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
209 /// Jump and Branch Instructions
210 let isCodeGenOnly = 1 in {
211 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
212 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
213 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
214 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
215 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
216 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
217 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
218 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
219 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
220 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
223 def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>;
224 def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>;
226 /// Multiply and Divide Instructions.
227 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
228 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6;
229 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
230 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6;
231 def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
232 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6;
233 def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
234 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6;
235 def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
236 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6;
237 def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
238 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6;
239 def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
240 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
241 def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
242 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6;
244 let isCodeGenOnly = 1 in {
245 def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>,
246 ISA_MIPS3_NOT_32R6_64R6;
247 def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>,
248 ISA_MIPS3_NOT_32R6_64R6;
249 def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>,
250 ISA_MIPS3_NOT_32R6_64R6;
251 def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>,
252 ISA_MIPS3_NOT_32R6_64R6;
253 def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>,
254 ISA_MIPS3_NOT_32R6_64R6;
255 def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
256 ISA_MIPS3_NOT_32R6_64R6;
257 def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
259 /// Sign Ext In Register Instructions.
260 def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
262 def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
267 def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6;
268 def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6;
270 /// Double Word Swap Bytes/HalfWords
271 def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2;
272 def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2;
274 def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
276 let isCodeGenOnly = 1 in
277 def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
279 let AdditionalPredicates = [NotInMicroMips] in {
280 def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
281 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
282 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
285 def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
286 def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
287 def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
289 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
290 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
291 "dsll\t$rd, $rt, 32", [], II_DSLL>;
292 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
293 "sll\t$rd, $rt, 0", [], II_SLL>;
294 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
295 "sll\t$rd, $rt, 0", [], II_SLL>;
298 // We need the following pseudo instruction to avoid offset calculation for
299 // long branches. See the comment in file MipsLongBranch.cpp for detailed
302 // Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
303 // where %PART may be %hi or %lo, depending on the relocation kind
304 // that $tgt is annotated with.
305 def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
306 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
308 // Cavium Octeon cnMIPS instructions
309 let DecoderNamespace = "CnMips",
310 EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
311 AdditionalPredicates = [HasCnMips] in {
313 class Count1s<string opstr, RegisterOperand RO>:
314 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
315 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
316 let TwoOperandAliasConstraint = "$rd = $rs";
319 class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
320 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
321 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"),
322 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))],
323 NoItinerary, FrmR, opstr> {
324 let TwoOperandAliasConstraint = "$rt = $rs";
327 class SetCC64_R<string opstr, PatFrag cond_op> :
328 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
329 !strconcat(opstr, "\t$rd, $rs, $rt"),
330 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
332 II_SEQ_SNE, FrmR, opstr> {
333 let TwoOperandAliasConstraint = "$rd = $rs";
336 class SetCC64_I<string opstr, PatFrag cond_op>:
337 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
338 !strconcat(opstr, "\t$rt, $rs, $imm10"),
339 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
340 immSExt10_64:$imm10)))],
341 II_SEQI_SNEI, FrmI, opstr> {
342 let TwoOperandAliasConstraint = "$rt = $rs";
345 class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
346 RegisterOperand RO, bits<64> shift = 1> :
347 InstSE<(outs), (ins RO:$rs, uimm5_64:$p, opnd:$offset),
348 !strconcat(opstr, "\t$rs, $p, $offset"),
349 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
350 bb:$offset)], II_BBIT, FrmI, opstr> {
352 let isTerminator = 1;
353 let hasDelaySlot = 1;
357 class MFC2OP<string asmstr, RegisterOperand RO> :
358 InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
359 !strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>;
362 let Pattern = [(set GPR64Opnd:$rd,
363 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
364 def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
367 // Branch on Bit Clear /+32
368 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd>, BBIT_FM<0x32>;
369 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, 0x100000000>,
372 // Branch on Bit Set /+32
373 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd>, BBIT_FM<0x3a>;
374 def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, 0x100000000>,
377 // Multiply Doubleword to GPR
378 let Defs = [HI0, LO0, P0, P1, P2] in
379 def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
382 // Extract a signed bit field /+32
383 def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
384 def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
386 // Clear and insert a bit field /+32
387 def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
388 def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
390 // Move to multiplier/product register
391 def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
392 def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
393 def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
394 def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
395 def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
396 def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
398 // Count Ones in a Word/Doubleword
399 def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
400 def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
402 // Set on equal/not equal
403 def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
404 def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
405 def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
406 def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
408 // 192-bit x 64-bit Unsigned Multiply and Add
409 let Defs = [P0, P1, P2] in
410 def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
413 // 64-bit Unsigned Multiply and Add Move
414 let Defs = [MPL0, P0, P1, P2] in
415 def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
418 // 64-bit Unsigned Multiply and Add
419 let Defs = [MPL1, MPL2, P0, P1, P2] in
420 def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
423 // Move between CPU and coprocessor registers
424 def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>;
425 def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>;
430 /// Move between CPU and coprocessor registers
431 let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
432 def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd>, MFC3OP_FM<0x10, 1>, ISA_MIPS3;
433 def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
434 def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
435 def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
438 //===----------------------------------------------------------------------===//
439 // Arbitrary patterns that map to one or more instructions
440 //===----------------------------------------------------------------------===//
443 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
444 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
445 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
446 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
449 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
450 def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
451 def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
452 def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
453 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
454 def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
456 def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
457 def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
458 def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
459 def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
460 def : MipsPat<(MipsLo tglobaltlsaddr:$in),
461 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
462 def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
464 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
465 (DADDiu GPR64:$hi, tglobaladdr:$lo)>;
466 def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
467 (DADDiu GPR64:$hi, tblockaddress:$lo)>;
468 def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
469 (DADDiu GPR64:$hi, tjumptable:$lo)>;
470 def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
471 (DADDiu GPR64:$hi, tconstpool:$lo)>;
472 def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
473 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
475 def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
476 def : WrapperPat<tconstpool, DADDiu, GPR64>;
477 def : WrapperPat<texternalsym, DADDiu, GPR64>;
478 def : WrapperPat<tblockaddress, DADDiu, GPR64>;
479 def : WrapperPat<tjumptable, DADDiu, GPR64>;
480 def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
482 defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
485 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
486 (BLEZ64 i64:$lhs, bb:$dst)>;
487 def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
488 (BGEZ64 i64:$lhs, bb:$dst)>;
491 defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
492 defm : SetlePats<GPR64, SLT64, SLTu64>;
493 defm : SetgtPats<GPR64, SLT64, SLTu64>;
494 defm : SetgePats<GPR64, SLT64, SLTu64>;
495 defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
498 def : MipsPat<(trunc (assertsext GPR64:$src)),
499 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
500 def : MipsPat<(trunc (assertzext GPR64:$src)),
501 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
502 def : MipsPat<(i32 (trunc GPR64:$src)),
503 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
505 // variable shift instructions patterns
506 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
507 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
508 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
509 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
510 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
511 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
512 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
513 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
515 // 32-to-64-bit extension
516 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
517 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
518 def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
520 // Sign extend in register
521 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
522 (SLL64_64 GPR64:$src)>;
525 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
528 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
529 (DSUBu GPR64:$lhs, GPR64:$rhs)>;
530 let AdditionalPredicates = [NotDSP] in {
531 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
532 (DADDu GPR64:$lhs, GPR64:$rhs)>;
533 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
534 (DADDiu GPR64:$lhs, imm:$imm)>;
537 // Octeon bbit0/bbit1 MipsPattern
538 let Predicates = [HasMips64, HasCnMips] in {
539 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
540 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
541 def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
542 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
543 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
544 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
545 def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
546 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
549 // Atomic load patterns.
550 def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>;
551 def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>;
552 def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>;
553 def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>;
555 // Atomic store patterns.
556 def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>;
557 def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>;
558 def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>;
559 def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>;
561 //===----------------------------------------------------------------------===//
562 // Instruction aliases
563 //===----------------------------------------------------------------------===//
564 def : MipsInstAlias<"move $dst, $src",
565 (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
567 def : MipsInstAlias<"move $dst, $src",
568 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
570 def : MipsInstAlias<"daddu $rs, $rt, $imm",
571 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
573 def : MipsInstAlias<"dadd $rs, $rt, $imm",
574 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
575 0>, ISA_MIPS3_NOT_32R6_64R6;
576 def : MipsInstAlias<"daddu $rs, $imm",
577 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
579 def : MipsInstAlias<"dadd $rs, $imm",
580 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
581 0>, ISA_MIPS3_NOT_32R6_64R6;
582 def : MipsInstAlias<"dsll $rd, $rt, $rs",
583 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
585 def : MipsInstAlias<"dneg $rt, $rs",
586 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
588 def : MipsInstAlias<"dneg $rt",
589 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
591 def : MipsInstAlias<"dnegu $rt, $rs",
592 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
594 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
595 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
596 InvertedImOperand64:$imm), 0>, ISA_MIPS3;
597 def : MipsInstAlias<"dsubi $rs, $rt, $imm",
598 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
599 InvertedImOperand64:$imm),
600 0>, ISA_MIPS3_NOT_32R6_64R6;
601 def : MipsInstAlias<"dsubi $rs, $imm",
602 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
603 InvertedImOperand64:$imm),
604 0>, ISA_MIPS3_NOT_32R6_64R6;
605 def : MipsInstAlias<"dsub $rs, $rt, $imm",
606 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
607 InvertedImOperand64:$imm),
608 0>, ISA_MIPS3_NOT_32R6_64R6;
609 def : MipsInstAlias<"dsub $rs, $imm",
610 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
611 InvertedImOperand64:$imm),
612 0>, ISA_MIPS3_NOT_32R6_64R6;
613 def : MipsInstAlias<"dsubu $rs, $imm",
614 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
615 InvertedImOperand64:$imm),
617 def : MipsInstAlias<"dsra $rd, $rt, $rs",
618 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
620 def : MipsInstAlias<"dsrl $rd, $rt, $rs",
621 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
624 // Two operand (implicit 0 selector) versions:
625 def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>;
626 def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
627 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
628 def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
630 let Predicates = [HasMips64, HasCnMips] in {
631 def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
632 def : MipsInstAlias<"syncs", (SYNC 0x6), 0>;
633 def : MipsInstAlias<"syncw", (SYNC 0x4), 0>;
634 def : MipsInstAlias<"syncws", (SYNC 0x5), 0>;
637 //===----------------------------------------------------------------------===//
638 // Assembler Pseudo Instructions
639 //===----------------------------------------------------------------------===//
641 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
642 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64),
643 !strconcat(instr_asm, "\t$rt, $imm64")> ;
644 def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>;
646 def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr),
648 def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64),